KR100261887B1 - Data interface method using pci bus - Google Patents

Abstract

PURPOSE: A method for interfacing data via a PCI(Peripheral Component Interconnect) bus is provided to perform a function of a PCI interface module which does not have a master logic block and thus has a simple structure. CONSTITUTION: The control information necessary for data transmission is stored in a local memory(202). The control information stored in the local memory is read by arbitration of a memory arbitration block(204). A start address of data that will be transmitted and the amount of the data is transferred to a packet transmission module(206). An interrupt for a transmission mode is generated, and an interrupt flag bit is set(208). A host reads a start address register and a data amount information register in the packet transmission module, and a flag register of a memory control block, and thereby recognizes that a current interrupt is for the data transmission(210). The host reads the data to be transmitted from its memory, and stores the read data in the packet transmission module via a slave logic block(212). Header information is added to the data stored in the packet transmission module, and then transmitted to a network(214).

Description

Data interface method using PCI bus

The present invention relates to a method of performing a network interface using a host bus, and more particularly, to a data interface method suitable for performing a data interface between a host and an ATM network using a PCI bus.

In general, when performing a data interface between a host and a network using a PCI bus as a host bus, the network transceiver frequently requests data transmission from the network transceiver to the host. Contains logic to perform slave functions.

Here, the master function refers to a function of applying a bus occupancy request signal to the bus to perform a data transfer operation on the bus after obtaining a permission, and the slave function always monitors a signal on the bus and assigns an address to which it is assigned. When a signal is received to perform a read or write operation on an area, a function of putting data on the bus in the own area or storing data on the bus in the own area according to a command applied on the bus.

A typical conventional data interface device for performing a data interface between a host and an ATM network using a PCI bus as described above is shown in FIG.

That is, as shown in FIG. 4, the conventional data interface device includes a PCI module 402, a memory control block 404, a local memory 406, a packet transfer module 408, a cell transfer module 410, and a memory. An arbitration block 412 and a cell receive block 414, and the PCI module 402 also includes a master logic block 4021 and a slave logic block 4023.

Referring to FIG. 4, the master logic block 4021 performs a data transfer operation on the PCI bus S41 after obtaining a permission by applying a bus occupancy request signal to the PCI bus S41. The cell data provided from the host is transferred to the packet transfer module 408 through the PCI bus S41, and the reception cell data provided from the packet transfer module 408 is not shown through the PCI bus S41 in the reception mode. To the corresponding memory area (ie, the designated area) of the host (eg PC).

In addition, the slave logic block 4023 always monitors a signal on the PCI bus S41 and receives a command to perform a read or write operation in an address area allocated to the slave logic block 4023. In accordance with the present invention, the data is stored in the PCI bus S41 in its own area or the data on the PCI bus S41 is stored in its own area. For this purpose, the operation of the memory control block 404 is controlled. In addition, the local memory 406 stores information about cells and channels to be transmitted from the host.

Next, the memory control block 404 reads and writes data in the cell transfer block 410, the cell receive block 414, and the local memory 406 according to the control from the slave logic block 4023 described above. do. At this time, the local memory 406 stores the size and location information of the data to be transmitted in the transmission mode, and also the control information analyzed in the header information of the cell received in the reception mode and information about the buffer of the host (that is, , Location information of a host side buffer for storing the received cell data).

On the other hand, the packet transfer module 408 reads the data to be transmitted at the designated position (that is, the position of the data to be transmitted from the host) after obtaining the license of the PCI bus S41 through the master logic block 4021. The received cell data transmitted from the cell transmission block 410 or the cell reception block 414 is transferred to and stored in a designated location of the host.

At this time, the designated position and size information of the data to be transmitted and the designated position and size information to be stored in the received data are stored in the local memory 406, and the storage of such control information is initialized or operated in the local memory 406. It is performed by the host at the time.

On the other hand, the cell transport block 410 may include header information such as Generic Flow Control (GFC), Virtual Path Identifier (VPI), and Virtual Channel (VCI) in the cell data provided from the packet transmission module 408 in the transmission mode. 5 bytes of header information of Identifier (PT), Payload Type (PT), Cell Loss Priority (CLP), and HEC (Header Error Control) are added to 48 bytes of payload information and then sent to the ATM network for transmission to the target host. Is sent.

In addition, the cell transport block 410 requests mediation to the memory arbitration block 412 when using the local memory 406, and reads control information when the use of the local memory 406 from the memory arbitration block 412 is approved. The local memory 406 is searched for, and based on the search result, it checks at which location in the host memory to acquire data, and requests the transfer of data to be transmitted to the packet transmission module 408 according to the result of the check. . At this time, the request signal provided to the packet transmission module 408 includes information about the start address of the data to be transmitted and the number of data.

Here, the 4-bit GFC section in the header information performs a media access control function. Also, the 8-bit VPI section and the 16-bit VCI section identify the virtual path and the virtual channel identification number to distinguish cells belonging to the same connection. It is a section indicating.

In addition, the 3-bit PT section is used to indicate whether or not the user information, the 1-bit CLP section indicates the cell abandon priority information indicating whether or not to give up the cell when the communication jam occurs, the 8-bit HEC section is the cell header As a cyclic redundancy check byte for error checking of intervals, this information is used to detect and correct errors in cells and to detect cell headers. The 1-bit cell discard priority information is information used to perform selective discarding of a cell when a cell is received in a cell buffer in an ATM exchange.

Meanwhile, the cell receiving block 414 analyzes the header information of the received cell when the cell data is received through the ATM network, and searches the local memory 406 to host the control information and the host of the channel associated with the received cell data. After reading the information on the buffer of the (e.g., location information of the host-side buffer for storing the received cell data, etc.), the packet transfer module 408 is requested to read the received cell data.

At this time, the request signal includes the start address of the buffer in which the received data is to be stored, the number of data currently transmitted, and the transfer request signal. In addition, the cell receive block 414 requests mediation to the memory arbitration block 412 when using the local memory 406, and reads control information when the use of the local memory 406 from the memory arbitration block 412 is approved. Search for local memory 406.

In addition, the memory control block 404, the local memory 406, the cell transmission block 410, the cell receiving block 414, and the memory arbitration block 412 are organically connected to each other through the local memory bus S42, In addition, the local memory 406 is configured in a form shared by the host, the cell transmission block 410 and the cell receiving block 414, the memory arbitration block 412 in the local memory based on the memory request from each component (406) Mediate use.

That is, the conventional data interface device using the PCI bus having the configuration as described above, in order to bring the data to be transmitted in the packet transmission module 408 from the host or to bring the received data to the designated memory location of the host, The transfer module 408 reads the data from the designated location or writes the data to the designated location after obtaining the permission (bus occupancy permission) of the PCI bus S41 through the master logic block 4021. Module 402 includes a master logic block 4021 and a slave logic block 4023.

However, since the master logic block 4021 that performs the function of requesting bus occupancy permission in the transmit mode or the receive mode has a relatively large logic configuration compared to the slave logic block 4023, these blocks 4021 and 4023 ) Takes up a very large area when implemented in hardware.

That is, the conventional data interface device using the PCI bus is not only a big obstacle to the thin and short size of the entire system due to the increase in the size of the PCI module (ie, the PCI interface module), but also a large factor that increases the manufacturing cost of the entire system. It's happening.

Accordingly, the present invention is to solve the above problems of the prior art, a data interface using a PCI bus that can perform the same function as the conventional PCI interface module using a simple PCI interface module having no master logic block. The purpose is to provide a method.

The present invention according to the above consistent point to achieve the object, the slave logic block connected to the host via the PCI bus for the data interface, local memory for storing control information for data transmission or reception, ATM data in the transmission mode In the data interface device including a cell transport block for transmitting the cell data of the predetermined N byte unit to the network and a cell receiving block for receiving cell data of the predetermined N byte unit via the ATM network in the reception mode. 10. A method of interfacing data using a method, the method comprising: recording, by the host, control information of a channel related to a transmission in the local memory; Searching for the local memory, reading start address information in the host memory and information on the number of data to be transmitted, storing the data in each register, and setting a flag of a register for a transfer mode; Generating an interrupt signal on the PCI bus via the slave logic block; When the interrupt signal is generated, the contents of the registers are read to recognize the type of the generated interrupt as a transmission interrupt, and the stored data to be transmitted are retrieved from the transmission start address as a starting point and loaded on the PCI bus. Providing fetched data to the cell transport block by using a next slave function; And a n-byte header information added to the extracted data and transmitted to the ATM network in units of N-byte cells.

According to another aspect of the present invention, there is provided a slave logic block connected to a host through a PCI bus for a data interface, a local memory storing control information for data transmission or reception, and ATM data in a transmission mode. In the data interface device including a cell transport block for transmitting the cell data of the predetermined N byte unit to the network and a cell receiving block for receiving cell data of the predetermined N byte unit via the ATM network in the reception mode. A method of interfacing data using a method, the method comprising: recording control information of a channel related to reception by the host in the local memory; When cell data is received in the cell receiving block through the ATM network, the header information of the received cell data is read, the local memory is searched, and the header information of the received data is analyzed based on control information of a channel related to the received data. Process of doing; Extracting control information of the host memory from the local memory and storing the control information in each register and setting a flag of a register for a reception mode; Generating an interrupt signal on the PCI bus via the slave logic block; When the interrupt signal is generated, the host reads the contents of each register to recognize the generated interrupt type as a reception interrupt, and grasps the memory location in the host where the received data is to be stored and the number of data to be received. Process of doing; And reading the received data onto the PCI bus using the slave logic block and storing the received data in a corresponding memory location of the host.

1 is a block diagram of a data interface device suitable for applying a data interface method according to the present invention;

2 is a flowchart illustrating a process of performing a data interface between a host and an ATM network using a PCI bus in a transmission mode according to a preferred embodiment of the present invention;

3 is a flowchart illustrating a process of performing a data interface between a host and an ATM network using a PCI bus in a reception mode according to a preferred embodiment of the present invention;

Figure 4 is a block diagram of a conventional data interface device using a PCI bus.

<Description of the code | symbol about the principal part of drawing>

102: slave logic block 104: memory control block

106: local memory 108: packet transfer module

110: cell transport block 112: memory arbitration block

114: cell receiving block

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a block diagram of a data interface device suitable for applying a data interface method according to the present invention.

As shown in the figure, the data interface device comprises a slave logic block 102, a memory control block 104, a local memory 106, a packet transfer module 108, a cell transfer module 110, a memory arbitration block ( 112 and cell receive block 114.

As can be seen from the comparison between FIG. 1 and FIG. 4 showing a conventional device, a data interface device suitable for application of the present invention configures a PCI interface module using only the slave logic block 102, and this slave logic block The most technical feature of performing the data interface between the host and the ATM network by using the 102. For this purpose, the slave logic block 102 uses a PCI bus (S11) through a line L11 in a transmission mode or a reception mode. In this case, the interrupt signal corresponding to the mode is recognized by the host (not shown).

At this time, the packet transmission module 108 includes a transmission start address register and a transmission number information register, and includes a reception start address register, a reception number information register and a reception cell status register, and the transmission start in the packet transmission module 108 is performed. The address register stores the start address of data to be transmitted from the host provided from the cell transfer block 110 in the transfer mode, and the transfer count information register stores the start address of the host for transfer provided from the cell transfer block 110 in the transfer mode. Information on the number of data to be read is stored. In this case, the reception cell status register stores information on whether the received cell data is in error or the current network status.

That is, the cell transfer block 110 reads the control information from the local memory 106 in the transfer mode, checks where in the host memory how much data is to be obtained, and then requests the data transfer module 108 to transmit the data. In this case, the data delivered in such a request includes a start address of the data to be transmitted (i.e., a transfer data start address of the host memory), the number of data to be read for transmission, and a request signal.

At this time, the local memory 106 has specified position and size information (ie, transmission start address and data number information) of data to be transmitted, a channel related to reception, and designated position and size information (ie, reception) at which the received data is to be stored. Storage start address and data number information of the stored data) are stored, and the storage of such control information is performed by the host upon initialization or operation of the local memory 106.

Next, the packet transfer module 108 instructs the signal to generate an interrupt for the transfer mode when the request signal for data transfer is applied from the cell transfer block 110 (i.e., to activate the signal of the interrupt pin). Is generated and provided to the slave logic block 102 and at the same time the flag for distinguishing the interrupt type is set in the memory control block 104, for example, the flag bit is set to "1" in the transmission mode, and the reception mode is selected. Set the flag bit to "0".

Accordingly, in the host not shown, each register of the packet transfer module 108 and the memory control block 104 (i.e., the slave logic block 102) is used when the interrupt is generated through the line L11 in the slave logic block 102. Reads the transfer start address register, the transfer count information register, and the flag setting register and stores the corresponding data at the corresponding address in the corresponding buffer of the packet transfer module 108 using the slave function of the slave logic block 102. do. In this case, the data stored in the buffer for transmission may be performed, for example, in units of 53 bytes.

As a result, the cell transport block 110 transmits the header information (5 bytes) to the ATM network, not shown, by using data provided from the packet transmission module 108 in units of cells.

On the other hand, the start address to be stored in the host memory in the reception mode is stored in the reception start address register in the packet transmission module 108, and the cell data received through the cell reception block 114 in the reception mode in the reception number information register. Information about the number of data to be delivered for storage in the host memory is provided when the cell data is received with the request signal.

Next, the packet transmission module 108 instructs the command signal to generate an interrupt for the reception mode (i.e., activate the signal of the interrupt pin) when the request signal for cell data reception from the cell reception block 114 is applied. Is generated and provided to the slave logic block 102, and at the same time, the flag for distinguishing the interrupt type is set in the memory control block 104, for example, the flag bit is set to "1" in the transmit mode, and the receive mode is set. Set the flag bit to "0".

Accordingly, in the host not shown, each register of the packet transfer module 108 and the memory control block 104 (i.e., the slave logic block 102) is used when the interrupt is generated through the line L11 in the slave logic block 102. After receiving the start address register, the receive number information register, and the flag setting register, the number of received cell data stored in the buffer of the packet transmission module 108 is transferred using the slave function of the slave logic block 102. It reads from the corresponding buffer of the transmission module 108 and stores it in its own set buffer area. In this case, the data received and stored in the host buffer may be performed in units of 53 bytes, for example.

Next, a process of performing a data interface between a host and an ATM network using the data interface device having the above-described configuration will be described.

First, a process of performing a data transfer operation using an interrupt technique in the transfer mode will be described.

2 is a flowchart illustrating a process of performing a data interface between a host and an ATM network using a PCI bus in a transmission mode according to a preferred embodiment of the present invention.

Referring to FIG. 2, first, in the local memory 106, control information (eg, start address information of data to be transmitted, information on the number of data to be transmitted, etc.) necessary for data transmission are stored in a slave logic block 102. (Step 202), the cell transport block 110 reads the control information stored in the local memory 106 through mediation of the memory arbitration block 112 in the transmission mode, that is, the host memory. Determine how much data should be taken from which location (step 204).

Next, in the cell transmission block 110, after confirming the control information necessary for data transmission, the packet transmission module 108 requests the corresponding data transmission, that is, the start address information of the data to be transmitted from the host and the data to be transmitted. A request signal is transmitted along with the number of pieces of information, which are stored in the transmission start address register and the transmission number information register of the packet transmission module 108, respectively (step 206).

As a result, when the request signal for data transmission is applied from the cell transmission block 110, the packet transmission module 108 generates a command signal to generate an interrupt for the transmission mode, and provides the command signal to the slave logic block 102 and at the same time the memory. In the control block 104, the flag bit for interrupt type classification is set to "1" (step 208). Thus, the slave logic block 102 generates an interrupt signal for data transfer on the PCI bus S11 via line L11.

Next, when an interrupt occurs on the PCI bus S11, the host reads the transfer start address register and the transfer number information register of the packet transfer module 108 using the slave logic block 102, and furthermore, the memory control block ( After reading the flag setting register of 104, it recognizes that the interrupt currently generated is an interrupt for data transmission (step 210), and reads a predetermined number of corresponding data whose transmission is determined from its own memory, and then slave logic block 102. Via the corresponding buffer of the packet transfer module 108 (step 212).

Then, the data stored in the buffer of the packet transmission module 108 is transferred to the cell transport block 110, in which the header information of 5 bytes preset in the cell data unit is added to the protocol. And then to an ATM network, not shown (step 214).

Therefore, a data interface between a host and an ATM network for transmitting data to another remote host is performed by executing the data transfer mode using the interrupt technique as described above.

Next, a process of performing a data reception operation using an interrupt technique in the reception mode will be described.

3 is a flowchart illustrating a process of performing a data interface between a host and an ATM network using a PCI bus in a reception mode according to a preferred embodiment of the present invention.

Referring to FIG. 3, the cell reception block 114 reads header information of a received cell when cell data arrives from an ATM network, and receives corresponding control information and a host of a channel associated with the same through a memory arbitration block 112. Information about the memory of the data is read from the local memory 106, and the header information of the received cell data is analyzed based on the read control information (step 302).

Next, the cell receiving block 114 requests the packet transmission module 108 to read the received data after removing the header information of the analyzed cell data. At this time, the request signal provided to the packet transmission module 108 includes start address information of the buffer in the host where the received data is to be stored and information on the number of data to be transmitted (step 304).

Therefore, when the request signal for receiving cell data is applied, the packet transmission module 108 stores the start address information and the number of data to be transmitted currently in the reception start address register and the reception data number information register, respectively, A command signal for generating an interrupt for the control signal is generated to the slave logic block 102 and the flag bit for classifying the interrupt type is set to "0" in the memory control block 104 (step 306). As a result, the slave logic block 102 generates an interrupt signal for receiving data on the PCI bus S11 via the line L11.

On the other hand, when an interrupt occurs on the PCI bus S11, the host reads the reception start address register and the reception number information register of the packet transfer module 108 using the slave logic block 102, and further, the memory control block 104. After reading the flag setting register (), it is recognized that the currently generated interrupt is an interrupt for receiving data (step 308).

As a result, the host reads the received data stored in the buffer of the packet transfer module 108 through the slave function of the slave logic block 102 (step 310), and the read data is stored in its corresponding buffer area (step 310). Step 312).

Therefore, the data interface between the host and the ATM network, which stores cell data received from another remote host via the ATM network in its own predetermined buffer area, is executed by executing the data reception mode using the interrupt scheme as described above.

As described above, according to the present invention, as in the conventional method, the slave module does not comprise a master logic block and a slave logic block having a large hardware configuration of a PCI module necessary for data interface between a host and an ATM network using a PCI bus. Data interface between a host using an PCI bus and an ATM network by implementing data transmission from a host using a PCI bus to an ATM network based on an interrupt scheme employing a block only, and also receiving data from the host through an ATM network. Not only can the system be made light and small, but the manufacturing cost of the entire system can be effectively suppressed.

Claims (2)

Slave logic block connected to host through PCI bus for data interface, local memory for storing control information for data transmission or reception, cell for transmitting data of predetermined N bytes of cell data to ATM network in transmission mode A method of interfacing data using a PCI bus in a data interface device including a transmission block and a cell reception block configured to receive cell data of a predetermined N-byte unit through the ATM network in a reception mode. Recording, by the host, control information of a channel related to transmission in the local memory; Searching for the local memory, reading start address information in the host memory and information on the number of data to be transmitted, storing the data in each register, and setting a flag of a register for a transfer mode; Generating an interrupt signal on the PCI bus via the slave logic block; When the interrupt signal is generated, the contents of the registers are read to recognize the type of the generated interrupt as a transmission interrupt, and the stored data to be transmitted are retrieved from the transmission start address as a starting point and loaded on the PCI bus. Providing fetched data to the cell transport block by using a next slave function; And And n-byte header information is added to the extracted data to transmit the N-byte cell information to the ATM network. Slave logic block connected to host through PCI bus for data interface, local memory for storing control information for data transmission or reception, cell for transmitting data of predetermined N bytes of cell data to ATM network in transmission mode A method of interfacing data using a PCI bus in a data interface device including a transmission block and a cell reception block configured to receive cell data of a predetermined N-byte unit through the ATM network in a reception mode. Recording, by the host, control information of a channel related to reception in the local memory; When cell data is received in the cell receiving block through the ATM network, the header information of the received cell data is read, the local memory is searched, and the header information of the received data is analyzed based on control information of a channel related to the received data. Process of doing; Extracting control information of the host memory from the local memory and storing the control information in each register and setting a flag of a register for a reception mode; Generating an interrupt signal on the PCI bus via the slave logic block; When the interrupt signal is generated, the host reads the contents of each register to recognize the generated interrupt type as a reception interrupt, and grasps the memory location in the host where the received data is to be stored and the number of data to be received. Process of doing; And And reading the received data onto the PCI bus using the slave logic block and storing the received data in a corresponding memory location of the host.

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