KR100256803B1 - Method for forming shallow junction in semiconductor device - Google Patents
Method for forming shallow junction in semiconductor device Download PDFInfo
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- KR100256803B1 KR100256803B1 KR1019930012708A KR930012708A KR100256803B1 KR 100256803 B1 KR100256803 B1 KR 100256803B1 KR 1019930012708 A KR1019930012708 A KR 1019930012708A KR 930012708 A KR930012708 A KR 930012708A KR 100256803 B1 KR100256803 B1 KR 100256803B1
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- film
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- polycrystalline silicon
- titanium
- diffusion
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000009792 diffusion process Methods 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 13
- 229910052719 titanium Inorganic materials 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 2
- 239000012153 distilled water Substances 0.000 claims description 2
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000011259 mixed solution Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 229910021332 silicide Inorganic materials 0.000 abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 230000010354 integration Effects 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1a도 내지 제1e도는 본 발명의 티타늄 실리사이드를 이용한 얇은 접합 형성방법을 도시한 단면도.1a to 1e are cross-sectional views showing a method of forming a thin junction using the titanium silicide of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막 4 : 다결정 실리콘 게이트3: gate oxide film 4: polycrystalline silicon gate
5 : 마스크 산화막 6 : 산화막 스페이서5: mask oxide film 6: oxide film spacer
7 : 다결정 실리콘막 9 : N+또는 P+확산층7: polycrystalline silicon film 9: N + or P + diffusion layer
10 : 티타늄막 11 : 티타늄 실리사이드막10 titanium film 11: titanium silicide film
본 발명은 고집적 반도체 소자의 제조공정에서 필수적인 얇은 접합(Shallow Junction) 형성방법에 관한 것으로, 특히 다결정 또는 비정질 실리콘을 확산원으로 사용하여 얇은 접합을 형성할 때에 다결정 실리콘을 티타늄과 반응시켜 티타늄 실리사이드막을 형성함으로써, 티타늄 실리사이드막 형성시의 접합 소모를 방지하고 접합의 면저항도 감소시키는 얇은 접합 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a thin junction, which is essential in the fabrication of highly integrated semiconductor devices. In particular, when a thin junction is formed using polycrystalline or amorphous silicon as a diffusion source, polysilicon is reacted with titanium to form a titanium silicide film. The present invention relates to a thin junction formation method that prevents the consumption of the junction in forming the titanium silicide film and also reduces the sheet resistance of the junction.
일반적으로, 반도체 소자의 성능을 저하시키지 않고 집적도를 증가시키기 위해서는 얇은 접합을 형성하는 것이 중요하며, 얇은 접합을 형성하기 위한 고체 확산원(Solid Diffusion Source) 방법 중에서 다결정 실리콘을 이용한 얇은 접합 형성방법이 많이 사용되고 있다.In general, it is important to form a thin junction in order to increase the degree of integration without degrading the performance of a semiconductor device, and a thin junction formation method using polycrystalline silicon is one of the solid diffusion source methods for forming a thin junction. It is used a lot.
한편, 집적도의 증가에 따라 접합의 저항이 증가함에 따라, 이를 감소시키기 위하여 티타늄 실리사이드를 이용한 접합의 금속화 연구가 진행되고는 있으나, 티타늄 실리사이드막 형성시 접합의 실리콘이 소모되어 접합 누설 전류가 증가하게 되는 문제점이 있다.On the other hand, as the resistance of the junction increases as the degree of integration increases, the metallization of the junction using titanium silicide has been conducted to reduce this, but the junction leakage current increases because the silicon of the junction is consumed when forming the titanium silicide layer. There is a problem.
따라서, 본 발명에서는 다결정 실리콘을 이용하여 접합 부분에 확산층을 형성하고, 확산이 완료된 후에 다결정 실리콘 상부에 티타늄을 증착하고 열처리 공정을 실시하여 확산층 위에 남아 있는 다결정 실리콘을 티타늄 실리사이드화하여, 확산층이 소모도 방지하고, 확산층의 면저항도 작은 얇은 접합을 형성시키는데 그 목적이 있다.Therefore, in the present invention, a diffusion layer is formed on the junction portion using polycrystalline silicon, and after diffusion is completed, titanium is deposited on the polycrystalline silicon and a heat treatment is performed to titanium silicide the polycrystalline silicon remaining on the diffusion layer, thereby consuming the diffusion layer. The purpose is to prevent thin films and to form thin junctions with small sheet resistance of the diffusion layer.
이하, 첨부된 도면을 참조하여 본 발명의 얇은 접합 형성방법을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a thin junction formation method of the present invention.
제1a도 내지 제1e도는 본 발명의 티타늄 실리사이드를 이용한 얇은 접합 형성방법을 도시한 단면도이다.1A to 1E are cross-sectional views showing a method of forming a thin junction using the titanium silicide of the present invention.
제1a도는 실리콘 기판(1) 상부에 소자 분리를 위한 필드 산화막(2)을 형성한 후, 소자가 형성될 영역에 게이트 산화막(3)과 다결정 실리콘 게이트(4)를 증착하고, 후속 공정에서 접합 부분과 게이트가 단락되는 것을 방지하기 위해 마스크 산화막(5)을 다결정 실리콘 게이트(4) 상부에 증착한 다음, 사진 식각 공정으로 게이트를 형성하고, 그 상부 표면을 따라 산화막을 증착한 후에 에치백(Etch Back)공정을 실시하여 게이트의 측면에 산화막 스페이서(6)를 형성한 단면도이다.FIG. 1A illustrates forming a field oxide film 2 for device isolation on a silicon substrate 1, depositing a gate oxide film 3 and a polycrystalline silicon gate 4 in a region where the device is to be formed, and bonding in a subsequent process. A mask oxide film 5 is deposited on top of the polycrystalline silicon gate 4 to prevent a short circuit between the portion and the gate, and then a gate is formed by a photolithography process, and an oxide film is deposited along the upper surface thereof. It is sectional drawing in which the oxide film spacer 6 was formed in the side surface of the gate by performing an etching back process.
상기의 마스크 산화막(5)이 없다면 게이트 상부에 형성된 다결정 실리콘막을 제거하기 위한 후속공정에서 마스크 작업을 할때에 공정 여유가 산화막 스페이서 (6)의 폭 정도밖에 되지 않아 후속 공정인 실리사이드막 형성 공정에서 게이트와 접합 간에 단락이 발생하게 된다.If the mask oxide film 5 is not present, the process margin is only about the width of the oxide spacer 6 in the subsequent process for removing the polycrystalline silicon film formed on the gate. There will be a short circuit between the gate and the junction.
제1b도는 제1a도의 공정 후에 확산층을 형성하기 위한 확산원으로 상부 표면을 따라 다결정 실리콘막(7)을 증착한 단면도이다.FIG. 1B is a cross-sectional view of depositing the polycrystalline silicon film 7 along the upper surface as a diffusion source for forming the diffusion layer after the process of FIG. 1A.
제1c도는 사진 식각공정을 실시하여 접합이 형성된 영역의 상부에 형성된 다결정 실리콘막(7)을 제외한 나머지 부분의 다결정 실리콘막(7)을 제거한 다음, 접합이 형성될 영역에 불순물 이온 주입공정을 실시한 단면도이다.FIG. 1C is a photolithography process to remove the polycrystalline silicon film 7 except for the polycrystalline silicon film 7 formed on the region where the junction is formed, and then perform an impurity ion implantation process on the region where the junction is to be formed. It is a cross section.
제1d도는 제1c도의 공정에서 다결정 실리콘막(7)에 주입된 불순물 이온을 일정 온도 및 시간하에서 확산공정을 실시하여 N+또는 P+확산층(9)을 형성하고, N+또는 P+확산층(9) 상부에 남아 있는 다결정 실리콘막(7)을 실리사이드화하기 위하여 전체 표면을 따라 티타늄막(10)을 증착한 단면도이다.FIG. 1D illustrates a process of diffusing impurity ions implanted into the polycrystalline silicon film 7 in the process of FIG. 1C under a constant temperature and time to form an N + or P + diffusion layer 9, and an N + or P + diffusion layer ( 9) A cross-sectional view of the titanium film 10 deposited along the entire surface in order to silicide the polycrystalline silicon film 7 remaining thereon.
제1e도는 제1d도의 공정에서 증착된 티타늄막(10)을 일정 온도 및 시간하에서 열처리함으로써, 티타늄막(10)과 N+또는 P+확산층(9) 상부에 남아 있는 다결정 실리콘막(7)을 반응시켜 티타늄 실리사이드막(11)을 형성하고, 산화막 상부에 있는 미반응 티타늄은 암모니아수, 과산화수소수, 증류수가 1 : 1 : 5의 비율로 혼합된 용액을 사용하여 제거한 후에 다시 한번 열처리 공정을 실시하여 비저항이 낮은 최종의 티타늄 실리사이드막(11)을 형성함으로써, 티타늄 실리사이드막(11)과 N+또는 P+확산층(9)으로 구성되며 낮은 면저항을 갖는 얇은 접합을 완성한 단면도이다.FIG. 1e shows the polycrystalline silicon film 7 remaining on the titanium film 10 and the N + or P + diffusion layer 9 by heat-treating the titanium film 10 deposited in the process of FIG. 1d at a constant temperature and time. React to form a titanium silicide film 11, and remove the unreacted titanium on the oxide film by using a mixed solution of ammonia water, hydrogen peroxide water, and distilled water in a ratio of 1: 1: 5 and then heat treatment again. By forming the final titanium silicide film 11 having a low specific resistance, it is a cross-sectional view of a thin junction composed of the titanium silicide film 11 and the N + or P + diffusion layer 9 and having a low sheet resistance.
상기 제1a도 내지 제1e도에서 설명한 본 발명의 얇은 접합 형성방법을 사용하게 되면, 다결정 실리콘을 확산원으로 확산층을 형성하고, 이때 남겨진 다결정 실리콘을 티타늄과 반응시켜 티타늄 실리사이드막을 형성시켜 얇은 접합을 완성함으로써, 접합의 소모가 없고, 얇은 접합의 면저항이 낮아지는 효과를 얻게 된다.When the thin junction formation method of the present invention described in FIGS. 1A to 1E is used, a diffusion layer is formed using polycrystalline silicon as a diffusion source, and at this time, the remaining polycrystalline silicon is reacted with titanium to form a titanium silicide film to form a thin junction. By the completion, there is no consumption of the bonding and the sheet resistance of the thin bonding is lowered.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930012708A KR100256803B1 (en) | 1993-07-07 | 1993-07-07 | Method for forming shallow junction in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930012708A KR100256803B1 (en) | 1993-07-07 | 1993-07-07 | Method for forming shallow junction in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR950004400A KR950004400A (en) | 1995-02-18 |
| KR100256803B1 true KR100256803B1 (en) | 2000-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019930012708A KR100256803B1 (en) | 1993-07-07 | 1993-07-07 | Method for forming shallow junction in semiconductor device |
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| Country | Link |
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| KR (1) | KR100256803B1 (en) |
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1993
- 1993-07-07 KR KR1019930012708A patent/KR100256803B1/en not_active IP Right Cessation
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| KR950004400A (en) | 1995-02-18 |
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