KR100254919B1 - Data receiving apparatus and method of deinterleaving data - Google Patents

Abstract

When frame information (F1) C2, which defines the frame type in the transport protocol format, is received in the pager, the data of the following interleaving portion is received. The receiving buffer circuit converts the received data from serial data to parallel data according to the frame type, and the deinterleaving circuit reproduces (deinterleaves) the converted parallel data.

The converting means converts the data received by one of the plurality of receiving means into parallel data corresponding to the format data indicating the data modulation mode and / or data transmission rate.

Description

Data receiver and data deinterleaving method

To date, NTT and POCSAG systems are known as paging (radio calling) systems.

For example, the POCSAG system uses binary frequency shift keying (FSK) as the modulation mode and sets a frame rate of 512 bps (bits / sec). When paging is performed, the paging service company transmits the digital data modulated by FSK to the called pager at the specified frame rate. In this way, a service for a communication message has been performed.

Meanwhile, recent advances in mobile telecommunications technology have reduced the burden of telecommunications services. Thus, mobile communication has been widely used among operators, individuals, especially young people, which has led to an increase in subscribers. As a result, subscriber addresses were scarce and traffic was always crowded. Therefore, the conventional POCSAG system has faced difficulties in providing satisfactory service to subscribers.

As the demand for paging services has increased and serviceable menus have recently increased, there is a need to improve paging systems. As a result, the future use of the "RCR STD-43" has been defined as the following standard system.

The above-described paging system (hereinafter referred to as "STD-43") will be briefly described. The data structure used for STD-43 is shown in FIG. In relation to Fig. 32, the symbol "A" represents a data structure transmitted in one hour period and "B" represents one cycle of the data structure "A". The symbol "C" represents the data structure in one frame of the cycle structure "B". The symbol "D" represents a block structure of one frame. The data structure "A" consists of 15 cycles, each given by the numbers "No. 0" to No. 14 ".

The cycle structure "B " is composed of 128 frames transmitted in four-minute periods, each given by the numbers " No. 0 " to " No. 127 ". One frame has a data length of 1.875 seconds. Data in one frame of the frame structure cycle is divided into eight sections corresponding to the data contents.

The eight sections of the data content, as shown in the data structure "C" and the block structure "D", are synchronized to synchronization 1 (S1) C1 and frame information (F1) C2 and synchronization 2 (S2) C3, as shown earlier. Synchronized structure D1, block information (B1) C4, address field (AF) C5, vector field (VF) C6, message field (MF) C7 and idle block (IB) C8 arranged and transmitted to 115 ms (milliseconds) And an interleaved block structure D2 arranged to be transmitted at a frame rate of 160 ms for each block so that 11 blocks are transmitted. In the synchronization signal part D, the synchronization 1 (S1) C1 comprises frame pattern data including 112-bit 2-level FM data (in detail, binary FSK modulation data) of 1600 bps and including information of frame reception timing, This timing receives 1600 bps data and a transmission type selected from the following four frame types / rates at which the interleaving block portion D1 is interleaved / transmitted.

2-level FM 1600bps (binary FSK modulation / 1600bps)

2. 2-level FM 3200bps (binary FSK modulation / 3200bps)

3-level FM 3200bps (quadruple FSK modulation / 3200bps)

4. 4-level FM 6400bps (Finary FSK Modulation / 6400bps)

Frame information (F1) C2 consists of 32-bit two-levels of 1600 bps and data of the number of cycles (4 bits) of the cycle of the data structure "A" to which this frame belongs, and data of the frame number of the cycle to which this frame belongs. (7 bits), instruction information and a transfer operation number of a plurality of transfer operations.

A block structure D2 formed of synchronization 2 (S2) C3 and block information (B1) C4 to idle block (IB) C8 and interleaved is data transmitted in the frame type designated by synchronization 1 (S1) C1. Synchronization 2 (S2) C3 provides timing information to the interleaved block structure D2 transmitted at the frame rate specified by synchronization 1 (S1) C1 to enable the modulation scheme and the pager to have interleaved block structure D2. Block for

Block information (BI) C4 is data composed of one word located in block # 0 of the interleaved block structure D2. The block information (BI) C4 is the starting point of the address field (AF) C5 described later and the ending point of the field so that real-time information, time zones and system messages are recorded if the ID of the broadcasting system and the number of frames is zero. Block information (1) for storing the number of words (2 bits) used, the words (6 bits) used as the starting point of the vector field (VF) C6, and the information of the block information items (2, 3, 4). ).

The address field AF5 is a field for storing address data stored in a short address (32 bits) or a long address (64 bits) in the called pager.

The vector field (VF) C6 and the address field (AF) C5 form a pair, and the vector field (VF) C6 is a word starting in the message field (MF) C7 whose message is described later, and a word of the message data thereof. This field is used to store the length (hereafter simply referred to as "message length") and the data format of its own message data.

The message field MF C7 is a field for storing message data corresponding to the information specified by the vector field VF C6. Idle block (IB) C8 is an unused block in which a pattern composed of "1" or "0" is set.

The signal formats shown in Fig. 32 are interleaved / transmitted in parallel in a time sequential manner regardless of the four phases "a", "b", "c", and "d". That is, if STD-43 is used, the paging service company uses any one of the above four phases or two to four phases so that multiplexing is possible so that data in one frame having different contents can be transmitted simultaneously.

In STD-43, the relationship between the phases of the frame rates is adjusted as follows.

1600bps: Any one of phase "a", "b", "c", "d" is used (degree of multiplexing: 1)

3200bps: Phase "a" and "c" or a pair of "b" and "d" is used (degree of multiplexing: 2)

6400bps: All of phases "a", "b", "c", and "d" are used (degree of multiplexing: 4)

Hereinafter, the block structure of the interleaved block structure D2 will be described. Referring to FIG. 32, one block is designed such that the frame rate is 160 ms. One block stores eight rows (called one row as one word) in parallel for one phase. Each row consists of the following 32 bits.

Information (information bit): 21 bits

Parity (check bit): 10 bits

CK (even parit bit): 1 bit

The number of data bits in a block depends on the frame rate. The relationship between the frame rate and the number of data bits in one block is as follows.

1600 bps: 1 phase × 8 words × 32 bits = 256 bits

3200 bps: 2 phases × 8 words × 32 bits = 512 bits

6400 bps: 4 phases × 8 words × 32 bits = 1024 bits

Hereinafter, bit data structures in one block at each frame rate will be described with reference to FIGS. 33 to 35. 33 shows a bit data structure in one block at a frame rate of 1600 bps, FIG. 34 shows a bit data structure in one block at a frame rate of 3200 bps, and FIG. 35 is in one block at a frame rate of 6400 bps. A bit data structure is shown.

When the interleaved block structure D2 is transmitted at 1600 bps, the bit data structure in one block shown in FIG. 33 is used. The order of transfer of bit data is W (word) 0a1, W1a1, W2al, ..., W5a32, W6a32, and W7a32 in the arrow? Display direction shown in FIG.

When the transmission is performed at 3200bps, the bit data structure in one block shown in Fig. 34 is used. The order of transfer of bit data is W0a1, W0c1, W1al, ..., W6c32, W7a32, W7c32 for 2-level FM in the direction of arrow (beta) shown in Fig. 34, and W0a1 and W0c1 for 4-level FM. , W1a1 and W1c1, W2al and W2c1, ..., W6a32 and W6c32, W7a32 and W7c32. When transmission is performed at 6400bps, the structure of the bit data in one block is used as shown in FIG. The order of transfer of bit data is W0a1 and W0b1, W0c1 and W0d1, W1a1 and W1b1, W1c1 and W1d1, ..., W6a32 and W6b32, W6c32 in the four-level FM in the arrow? Display direction shown in FIG. And W6d32, W7a32 and W7b32, W7c32 and W7d32.

As described above, the STD-43 involves the number of bits of data in one block received at each frame rate and in other interleaving modes. In addition, in the case of the 3200bps frame rate, the bit data structure varies depending on whether the modulation mode is 2-level FM or 4-level.

When the paging system uses the paging system STD-43, it is selected from four types of frame type / rate in synchronization 1 (S1) C1 of synchronization structure D1. Therefore, the number of data bits can be arbitrarily changed in one frame transmitted to the called pager.

Therefore, if the called pager has consistently received, amplified and digitized data transmitted wirelessly in order to simply convert the two-level FM serial data into parallel data as has been done by a conventional POCSAG system, then a meaningless serial Data is sent unintentionally. Therefore, a data reproducing method applicable to the STD-43 and capable of rearranging bit data to correspond to the received frame type should be provided to the pager.

The following method has been proposed for reproducing received data provided to a pager.

(1) a method in which a plurality of types of hardware devices (decoders) applicable to each frame rate and degree of multiplexing are mounted in the pager; Any one of the mounted hardware devices is selected such that data transmitted at any one of the frame rates is received; The bit data of the interleaved block structure D2 of the data is reproduced according to the degree of multiplexing and by the selected deinterleaving circuit.

(2) one type of hardware is mounted to the pager; Software for performing control to rearrange the bit data in the interleaved block structure D2 according to the frame type of the received data is installed so that the received data is reproduced.

When the method (1) is used, the pager includes an S / P conversion circuit for converting serial data into parallel data according to a frame type of the received data; A rearrangement circuit is provided for rearranging parallel data in each phase to separate the data.

When the method (2) is used, an S / P conversion circuit and a rearrangement circuit are provided which are controlled by software. However, in the above mentioned case (1), the number of hardware to be received and reproduced and provided to the pager increases. Moreover, since the structure of each circuit has a complicated structure, the size of the receiving processing circuit after being mounted cannot be reduced. In the case of (2), the software has to perform heavy work, making the structure of the system more complicated.

The present invention provides a data receiving apparatus and data for reproducing data transmitted by a modulation mode of a frame rate (or transmission rate) and an interleaving mode arbitrarily selected in a predetermined modulation mode and a frame rate and deinterleaving mode. A method for deinterleaving.

1 is a block diagram showing a circuit of a pager as a first embodiment of a data receiving apparatus according to the present invention.

FIG. 2 is a circuit diagram showing an example of the internal structure of the reception data buffer circuit 304 shown in FIG.

FIG. 3 shows the relationship between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh) for 64-bit data supplied to the reception data buffer circuit 304 shown in FIG. Shows the correspondence.

FIG. 4 shows a frame type for one block, i.e. 1600 bps (2-level FM), transmitted at a frame rate of 1600 bps as shown in FIG. 32 and received by the receive data buffer circuit 304 shown in FIG. The correspondence between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh) is shown for the bit data (phase " a ") in the range α.

FIG. 5 shows a frame type for one block, i.e., 3200bps (2-level FM) and transmitted at a frame rate of 3200bps as shown in FIG. 34 and received by the receive data buffer circuit 304 shown in FIG. And latches 3043 (La to La) for bit data (a pair of phases "a" and "c") in the range "α1" first transmitted in the range α to The correspondence between the outputs from Lh) is shown.

FIG. 6 is a block, i.e., 3200bps (2-level FM) and is transmitted at a frame rate of 3200bps as shown in FIG. 34 and ranges for the frame type received by the receive data buffer circuit 304 shown in FIG. From the inputs to the registers 3042 (Ra to Rh) and latches 3043 (La to Lh) for the bit data (a pair of phases "a" and "c") in the range "α2" transmitted second from α. The correspondence between the outputs of

7 shows a frame type for one block, i.e., 3200bps (4-level FM) and transmitted at a frame rate of 3200bps as shown in FIG. 34 and received by the receive data buffer circuit 304 shown in FIG. And latches 3043 (La to La) for bit data (a pair of phases "a" and "c") in the range "α1" first transmitted in the range α to The correspondence between the outputs from Lh) is shown.

FIG. 8 shows a frame type for one block, i.e., 3200 bps (4-level FM) and transmitted at a frame rate of 3200 bps as shown in FIG. 34 and received by the receive data buffer circuit 304 shown in FIG. Input and latch 3043 (La to Lh) to register 3042 (Ra to Rh) for bit data (a pair of phases "a" and "c") in the range "α2" transmitted second in the range α Shows the correspondence between the outputs from

FIG. 9 shows a frame type for one block, i.e., 6400 bps (4-level FM), transmitted at a frame rate of 1600 bps as shown in FIG. 35 and received by the receive data buffer circuit 304 shown in FIG. For the bit data in the range " α1 " transmitted first in the range [alpha], the correspondence between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh).

FIG. 10 shows a frame type for one block, i.e., 6400 bps (4-level FM), transmitted at a frame rate of 6400 bps as shown in FIG. 35 and received by the receive data buffer circuit 304 shown in FIG. For bit data in the range " α2 " transmitted second in the range [alpha], the correspondence between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh).

FIG. 11 shows a frame type for one block, i.e., 6400 bps (4-level FM), transmitted at a frame rate of 6400 bps as shown in FIG. 35 and received by the receive data buffer circuit 304 shown in FIG. For the bit data in the range " α3 " transmitted third in the range α, the correspondence between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh) is shown.

FIG. 12 shows a frame type for one block, i.e., 6400 bps (4-level FM), transmitted at a frame rate of 6400 bps as shown in FIG. 35 and received by the receive data buffer circuit 304 shown in FIG. For the bit data in the range " α4 " transmitted fourth in the range [alpha], the correspondence between the input to the registers 3042 (Ra to Rh) and the output from the latches 3043 (La to Lh) is shown.

FIG. 13 is a diagram showing an example of a memory area structure of the RAM 403 shown in FIG.

FIG. 14 is a block diagram showing a structural example of the deinterleaving circuit 5 shown in FIG.

15 shows a rearrangement operation performed by the rearrangement circuit 502.

16 shows the rearrangement operation performed by the rearrangement circuit 503.

17 shows the rearrangement operation performed by the rearrangement circuit 504.

FIG. 18 is a circuit diagram showing an example of the internal structure of the address comparison circuit 6 shown in FIG.

19A and 19B are flowcharts showing a data receiving operation executed by the pager according to the first embodiment of the present invention.

20 is a flowchart illustrating a data receiving operation performed by the pager according to the first embodiment of the present invention.

21A and 21B are flowcharts showing a data receiving operation executed by the pager according to the first embodiment of the present invention.

22 is a flowchart illustrating a data receiving operation executed by the pager according to the first embodiment of the present invention.

Fig. 23 is a flowchart showing a reproducing operation performed by the deinterleaving circuit 5 of the pager according to the first embodiment of the present invention.

24 is a block diagram showing a circuit of a pager according to a second embodiment of the present invention.

FIG. 25 shows an example of the structure of a memory area in the RAM 404 shown in FIG.

26A and 26B are flowcharts illustrating a data receiving operation executed by a pager according to a second embodiment of the present invention.

27 is a flowchart showing a data receiving operation executed by the pager according to the second embodiment of the present invention.

28 is a flowchart showing a data receiving operation executed by the pager according to the second embodiment of the present invention.

29 is a flowchart illustrating a data receiving operation executed by a pager according to a second embodiment of the present invention.

30 is a timing diagram showing a data transfer operation and a reception operation performed by the DMA circuit 11 when the data reception operation is performed.

Fig. 31 is a block diagram showing the structure of a change circuit according to the second embodiment of the present invention.

32 shows an example of the structure of transmission data used in the pager system "RCR STD-43".

33 shows the structure of one block of the interleaved block structure D2 when the frame rate is 1600 bps (phase "a").

34 shows the structure of one block of the interleaved block structure D2 when the frame rate is 3200 bps (pair of phases "a" and "c").

35 shows the structure of one block of the interleaved block structure D2 when the frame rate is 6400 bp.

Accordingly, the present invention has been made to solve the foreseeable problems that occur in wireless pagers that receive and reproduce when the STD-43 standard is used. It is therefore an object of the present invention to provide a data receiving apparatus and a method for reproducing received data which can maintain a balance between hardware and software in order to receive and reproduce data and to reduce the size of hardware and the load caused by software. .

Still another object of the present invention is to provide a data receiving apparatus capable of applying the above-described data transmission method, maintaining a balanced balance between hardware and software, and reducing the size and burden of a circuit caused by a CPU. It is to provide a method for reproducing data.

According to the present invention for achieving the above object, receiving means for receiving data;

A plurality of reproducing means capable of reproducing the received data having a format recognizable by the data receiving apparatus;

Form data receiving means for receiving form data;

There is provided a data receiving apparatus including selection means for selecting one of the plurality of reproduction means in accordance with the format data received by the format data receiving means.

Therefore, the burden distributed between hardware and software can be balanced to reduce the size of the circuit and the burden on the CPU.

The format data indicates the frame rate and the reproducing means is selected according to the received frame rate. The reproduction processing speed of the reproduction means is controlled in accordance with the frame rate received by the format data receiving means.

The formal data indicates the modulation mode and the reproducing means is selected in accordance with the received modulation method. The received data is converted into parallel data according to the modulation scheme.

The format data indicates the frame rate and the modulation mode, and the reproducing means is selected according to the received frame rate and the modulation method. The reproduction processing speed of the reproduction means is controlled in accordance with the frame rate received by the format data receiving means. The received data is converted into parallel data according to the modulation scheme.

The data reproduction processing speed of the reproduction means is controlled in accordance with the interleaving mode. The received data is converted into parallel data according to the data interleaving mode.

Since the received data is converted into parallel data according to the data interleaving mode, the burden distributed to hardware and software can be balanced. Therefore, the size of the circuit and the burden caused by the CPU can be reduced.

A plurality of registers are provided that are used to convert the received data into parallel data.

Since the parallel data is divided into predetermined devices so as to be stored sequentially, the stored parallel data is read sequentially in the storage order so as to be supplied to the selected reproduction mode, and the reproduced parallel data is stored in the storage position to be read out, and in the data transfer process The operations required for data transfer are for example executed by the DMA circuit instead of the CPU. Therefore, the burden on the CPU can be further reduced.

When data to be reproduced in one operation by the reproducing means selected by the selecting means is stored in the data storing means, and when the timing of the reproducing means selected by the selecting means is detected, the parallel data is sequentially transferred from the data storing means to the reproducing means. The parallel data transmitted and simultaneously transferred by the converting means are sequentially stored by the data storing means, and the operations necessary for transmitting and receiving the data in the data transfer processing are executed by, for example, the DMA circuit instead of the CPU. Therefore, the burden on the CPU can be further reduced.

The format data received by the format data receiving means is stored until this data is next received.

The radio call ID code of the data receiving apparatus is stored. If the ID code is detected in the reproduced data while continuing the reproducing operation of the reproducing means, the detected ID code and the stored ID code are compared with each other. If the ID codes do not match with each other, the reproducing operation of the reproducing means is interrupted.

By providing the interface, the data receiving operation of the data receiving apparatus is controlled according to the control data supplied from the external apparatus connected via the interface. Therefore, even data that cannot be processed only by the data receiving apparatus can be processed under the control of the connected external apparatus.

According to another aspect of the present invention, data received by the plurality of rearrangement circuits

Receiving format data;

A method for deinterleaving data reproduced with data comprising selecting one of the plurality of rearrangement circuits according to received format data is provided.

According to the above method, when the data type information (synchronization 1 (S1) C1) is received, the rearrangement circuit is selected from the plurality of rearrangement circuits according to the data type information. Thus, the received data is reproduced by the selected rearrangement circuit.

Therefore, the processing burden distributed to hardware and software can be balanced. Accordingly, the size of the circuit and the burden on the CPU can be reduced.

Hereinafter, a preferred embodiment of a data receiving apparatus and a method of reproducing received data according to the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments use the data structure C and the block structure D shown in FIG.

(First embodiment)

1 is a block diagram showing a circuit structure of a pager as a first embodiment of a data receiving apparatus according to the present invention. The pager includes an antenna (1), a receiver circuit (2), a decoder (3), a controller (4), a deinterleaving circuit (5), an address comparison circuit (6), a display device (7), a notification unit (8). And a power supply circuit 9.

The antenna 1 receives and transmits the data transmitted from the transmitting station of the pager service company to the receiver circuit 2, for example, in the format shown in FIG.

The receiver circuit 2 is connected to the decoder section 3 and arranged to operate in response to a control signal supplied from the decoder section 3 to demodulate and detect the received data. The receiver circuit 2 fetches synchronization 1 (S1) C1 to select and output serial bit data according to a two-level FM or four-level FM modulation scheme. That is, only "d" is output when two-level FM modulation is performed. When 4-level FM modulation is performed, the MSB signal of the 4-level FM bit data is output to "d" and the LSB signal is output to "e".

The data contained in the frame pattern data obtained in the synchronization 1 (S1) C1 and obtained in connection with the modulation scheme are supplied to the level determining circuit 301 through the output "d", while the data relating to the frame rate is determined by the frame rate. Supplied to circuit 302. The decoder unit 3 outputs the line selection signal " a " output from the level determination circuit 301, the shift clock signal " b " output from the frame rate determination circuit 302, and the timing control circuit 303. In response to the data trigger "c", the frame pattern of the interleaved block structure D2 following synchronization 2 (S2) C3 is determined. The decoder unit 3 also converts the detected digital signal into 8-bit parallel data according to a modulation scheme and supplies it to the bus line "B".

The decoder unit 3 includes a level determination circuit 301, a frame rate determination circuit 302, a timing control circuit 303, and a reception data buffer circuit 304. Each of the level determining circuit 301 and the frame rate determining circuit 302 includes a buffer memory (not shown). The buffer memory stores control data output from the CPU of the controller 4 when the initialization is executed, data included in the received frame type data relating to the modulation method, and frame rate and related data. The buffer memory also stores control data output from the CPU 401 of the controller 4.

The level determining circuit 301 receives the serial bit data "d" (data of synchronization 1 (S1) C1) output from the receiver circuit 2 to generate the circuit selection signal "a" and modulates the received data. Determine.

The frame rate determining circuit 302 receives the serial data "d" (data of synchronization 1 (S1) C1) output from the receiver circuit 2 to determine the frame shape of the received data. In more detail, the frame rate determination circuit 302 determines the frame type in the following four types.

2-level FM 1600bps (binary FSK modulation / 1600bps)

2. 2-level FM 3200bps (binary FSK modulation / 3200bps)

3-level FM 3200bps (quadruple FSK modulation / 3200bps)

4. 4-level FM 6400bps (Finary FSK modulation / 6400bps)

The frame rate determination circuit 302 generates a shift clock signal " b " after determining the frame shape.

The timing controller 303 includes a buffer for temporarily storing timing control information obtained from the CPU 401 when the synchronization signal unit D1 is received. Therefore, the timing control circuit 303 controls bit-synchronization and frame-synchronization of the decoder unit 3. The timing control circuit 303 also generates a data trigger " c " for controlling the output timing of 8-bit parallel data from the received data buffer circuit 304.

The received data buffer circuit 304 converts the serial bit data (outputs "d" and "e") output from the receiver circuit 2 into 8-bit parallel data so as to output 8-bit parallel data to the bus line "B". Convert. The reception data buffer circuit 304 outputs the line selection signal " a " output from the level determining circuit 301 and the shift clock signal " b output from the frame rate determining circuit 302 so as to sequentially output 8-bit parallel data. And the above bit data in 64-bit units according to the data trigger " c " output from the timing control circuit 303.

The control unit 4 includes a CPU 401, a ROM 402, and a RAM 403, and controls the overall operation of the pager in accordance with a control program stored in the ROM 402.

The CPU 401 is, for example, a buffer memory 4011 for temporarily storing the frame pattern data read in the synchronization 1 (S1) C1, and data (cycle number, frame) read in the frame information (F1) C2. Buffer memory 4012 for temporarily storing the number and the plurality of output operation numbers, and data read from the block information (BI) C4 and the vector field (VF) C5 (address field (AF) C4 and vector filter (VF). A buffer memory 4013 for storing the start word of C5, the unique message data in the message field (MF) C6, and the message length in the message field (MF) C6), and playback in units of blocks for correcting errors. A buffer memory 4014 for storing the old data and a clock generator 4015 for generating a clock used for adjusting timing such as reception processing are provided.

The CPU 401 controls the circuit part connected for each data and the clock contained in the above one frame.

The ROM 402 indicates various frequency programs for operating the CPU 401 and frequency band information that the pager should receive, frame data and address data which are ID codes unique to the pager, and phases in which the ID code is stored. Remember the data.

As shown in Fig. 13, the RAM 403 stores a work area WA used for the operation of the CPU 401, a data reading memory area RDA used for reproducing the received data, and for storing the received message data. A memory area MMA for processing is provided.

The memory area RDA is a memory area for temporarily storing 8-bit parallel data read by the decoder unit 3 before being output to the deinterleaving circuit 5 described later. The number of bits of data that can be reproduced when the output timing to the deinterleaving circuit 5 is detected under the control of the CPU 401 (16 bits if the frame rate is 3200bps and 32 bits if the 6400bps) is the deinterleaving circuit 5 )

For each phase, the deinterleaving circuit 5 outputs the reproduced data to the bus line "b" according to the frame pattern, 16 bit data of 3200bps (2-level FM), 16 bit of 3200bps (4-level FM). 32-bit data of 6400 bps (4-level FM) are reproduced.

The address comparison circuit 6 operates according to the data trigger " c " output from the timing control circuit 303 and compares whether the address data contained in the reproduced address field AF5 matches with the own pager address data. Contrast.

The display device 7 is, for example, a circuit portion formed by a liquid crystal panel, a display buffer or a driver so as to display information such as a message on the liquid crystal panel.

The notification unit 8 includes, for example, a notification means including an LED for turning on or blinking to notify the reception of a message, a speaker for generating a sound for notifying the reception of the message, and a vibrating device vibrating to notify the reception of the message.

The power supply circuit 9 supplies power to the entire circuit of the pager when the power switch (not shown) is turned on.

The decoder unit 3 will be described in detail below. 2 is a circuit diagram showing the internal structure of the reception data buffer circuit 304 in the decoder unit 3. As shown in FIG. The receiving data buffer circuit 304 shown in Fig. 2 is a register for sequentially storing the serial bit data output from the receiver circuit 2 through 8 " B0 through B7 " Eight registers 3042 composed of (Ra to Rh); Eight latches 3043 each composed of La to Lh corresponding to the above-described registers 3042; A circuit selection circuit 3044 is provided.

The operation principle of the decoder unit 3 for converting serial bit data into 64-bit of 8-bit parallel will be described below. Fig. 3 shows the correspondence between the input to the registers 3042 (Ra to Rh) and the output at the latches 3043 (La to Lh) for 64-bit data input from the receive data buffer circuit 304 in one input operation. To show.

As can be seen from the table shown in FIG. 3, the serial bit data supplied to B7 of the register Rh of the register 3042 shown in FIG. 2 is 8-bit parallel data and the latch Lh of the latch 3043. Is output to D7. The serial bit data supplied to B4 of the register Rd of the register 3042 is output to D3 of the latch Le of the latch 3043 as 8-bit parallel data.

4 to 12 show that in the following cases, namely, frame type / rate 1600bps (when 2-level FM: phase "a" is received), 3200bps (2-level FM: pair of phases "a" and "c" are received. ), 3200 bps (4-level FM: when a pair of phases “a” and “c” are received), and 6400 bps (4-level), among the bit data in one block shown in FIGS. 32 to 35. The correspondence between the input to the registers 3042 (Ra to Rh) and the output at the latches 3043 (La to Lh) for the bit data in the range α is shown.

In the received data buffer circuit 304, the shift clock signal " b " output from the frame rate determination circuit 302 is supplied to each of the registers 3042, while the circuit selection signal output from the level determination circuit 301 is output. "a" is supplied to the reception data buffer circuit 304. The data trigger "c" output from the timing control circuit 303 is supplied to each of the latches 3043.

When the two-level FM bit data is output from the receiver circuit 2, the registers 3042 (Ra to Rh) input to the registers pull out 64-bit data through the output " d ". When 4-level FM bit data is output from the receiver circuit 2, the register 3042 has the MSB (high bit) of 64-bit data through the output "d" and LSB (low bit) through the output "e". To draw.

The bit data thus extracted is the line selection signal " a " output from the level determination circuit 301, the shift clock signal " b " output from the frame rate determination circuit 302, and the timing control circuit 302. By the data trigger "c", the bit data is controlled as follows so that the bit data is output as 8-bit parallel data corresponding to each frame type / rate.

1.If the frame type is 1600 bps (2-level FM: when phase "a" is received):

Bit data, i.e., a frame type of 1600 bps (2-level FM), is outputted as W (word) 0al, W1a1, W2a1, W3al, ..., in the direction of arrow (β) shown in FIG. The bit data sequentially output from the receiver circuit 2 through d "are W (word) 0al, W2al, W3al, ..., W5a8, W6a8, W7a8, and B0 of the registers 3042 (Ra) in the vertical direction. To B304 in the registers 3042 (Rh). When the data trigger " c " is supplied, 62 bits are output in 8-bit units to the bus line B through the D0 to D7 of the latches 3043 (La to Lh).

Since 8-bit parallel data of this frame type was received in a single phase, the data reproduction process is completed at this time. Therefore, data is actually output to the buffer memory 4014 via the bus line "B". The CPU 401 then performs an error correction process.

In addition, 8-bit × 8 columns, i.e., 8-byte data output from the receive data buffer circuit 304 during one output operation use only one phase, so that bit data in one block is equal to each other in the case shown in FIG. By performing the above operation four times for 64 bits, the data is converted into 8 bits of parallel data for one block.

2. If the frame type is 3200 bps (2-level FM: when a pair of phases "a" and "c" are received):

In the case where the frame type is 3200 bps (2-level FM), the bit data in phases "a" and "c" are multiplexed and drawn out. Therefore, data reproducing processing is performed in the deinterleaving circuit 5 so that parallel data passes through the RDA of the RAM 403 and the received data is separated into respective phases. Then, the reproduced data is stored in the buffer memory 4014 via the bus line "B", and then transferred to the error correction process in the CPU 401.

In a portion within the range α indicated by α1, the receiver circuit 2 through the output " d " as W0a1, W0c1, W1a1, ..., in the direction indicated by the arrow β in FIG. 34 as shown in FIG. The bit data sequentially outputted from are in the vertical order from W0a1, W0c1, W1a1, ..., W6c4, W7a4 and W7c4 to B7 of the register 3042 (Rh) by B0 of the register 3042 (Ra). Withdrawn. When the data trigger " c " is supplied, 64 bits are output to the bus line " B " in units of 8 bits via D0 to D7 of the latches 3043 (La to Lh).

In a portion within the range α indicated by α2, the output " d " is output to the receiver circuit 2 as W0a5, W0c5, W1a5, ... in the direction indicated by the arrow β in FIG. 34 as shown in FIG. The bit data sequentially outputted from are fetched in the vertical order from B0 of register 3042 (Ra) to W0a5, W0c5, W1a5, ..., W6c8, W7a8 and W7c8 to B7 of register 3042 (Rh). do. When the data trigger " c " is supplied, 64 bits are output to the bus line " B " in units of 8 bits via D0 to D7 of the latches 3043 (La to Lh).

3. If the frame type is 3200 bps (4-repel FM: when a pair of phase "a" and "c" is received):

If the frame type is 3200 bps (4-level FM), the bit data in phases "a" and "c" are multiplexed and drawn out. Therefore, data reproducing processing is performed in the deinterleaving circuit 5 so that parallel data passes through the RDA of the RAM 403 and the received data is separated into respective phases. Then, the reproduced data is stored in the buffer memory 4014 via the bus line "B", and then transferred to the error correction process in the CPU 401.

In this case, one bit each included in the upper "a" and the upper "c" is given to obtain two bits (one symbol). Therefore, the serial bit data includes a data buffer circuit (1) in which one bit data in the upper "a" and one data in the upper "c" are received through the outputs d and e of the receiver circuit 2 as MSB and LSB, respectively. 304 in parallel.

Therefore, data in the LSB of one symbol data is stored in the front portion (Ra to Rd) of the register 3042, while data in the MSB of the same symbol data is stored in the rear portion (Re to Rh).

In a portion within the range α indicated by α1, through the output “d” to the receiver circuit 2 as W0 a1, W1 a1, W2 a1,..., in the direction indicated by the arrow β in FIG. 34 as shown in FIG. 7. The bit data in the MSB sequentially outputted from B2 of registers 3042 (Re) are sequentially written in the order of W0a1, W1a1, W2a1, ..., W5a4, W6a4 and W7a4 to B7 of register 3042 (Rh). Withdrawn. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4 bits via D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bit data in the LSB sequentially output from the receiver circuit 2 via the output " e " as W0c1, W1c1, W2c1, ..., in the direction indicated by the arrow β in FIG. 34 as shown in FIG. W0c1, W1c1, W2c1, ..., W5c4, W6c4 and W7c4 are drawn out in the vertical order by B0 of register 3042 (Ra) to B7 of register 3042 (Rd). When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

In a portion within the range α indicated by α2, the output " d " is output to the receiver circuit 2 as W0a5, W0c5, W1a5, ... in the direction indicated by the arrow β in FIG. 34 as shown in FIG. The bit data in the MSB sequentially outputted from B2 of registers 3042 (Re) are sequentially written in the order of W0a5, W1a5, W2a5, ..., W5a8, W6a8 and W7a8 to B7 of register 3042 (Rh). Withdrawn. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4 bits via D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bit data in the LSB sequentially output from the receiver circuit 2 via the output " e " as W0c5, W1c5, W2c5, ..., in the direction indicated by the arrow β in FIG. 34 as shown in FIG. W0c5, W1c5, W2c5, ..., W5c8, W6c8 and W7c8 are drawn out in the vertical order by B0 of the registers 3042 (Ra). When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

Bit data for one block because 8-bit × 8 columns of data output from the data buffer circuit 304 received in one output operation, i.e., 8-bytes use the upper "a" and "c". 34 is modulated into 8-bit parallel data by performing the preceding operation up to eight times for each 64-bit data.

4. If the frame type is 6400 bps (4-level FM):

If the frame type is 6400 bps (4-level FM), both phase "a", phase "b" and phase "c" are multiplexed and drawn out. In addition, one bit each included in the upper "a" and the upper "b" is given to obtain two bits (one symbol). In addition, a bit of each hanan contained in the upper "c" and the upper "d" is given to obtain two bits (one symbol). Therefore, the supplied serial bit data includes one bit data in the upper "a" and one data in the upper "c" supplied through the outputs "d" and "e" of the receiver circuit 2 as MSB and LSB, respectively. Supplied in a manner.

therefore. Data in the LSB of one symbol data is stored in the front part Ra to Rd of the register 3042, while data in the MSB of the same symbol data is stored in the back part (Re to Rh).

In the part within the range α indicated by α1, the receiver circuit 2 is output via the output " d " as W0a1, W0c1, W1a1, ..., in the direction indicated by the arrow β shown in FIG. 35 as shown in FIG. The bit data in the MSB sequentially outputted from the NB is vertically represented as W0a1, W0c1, W1a1, ..., W6c2, W7a2 and W7c2 to B7 of the register 3042 (Rh) by B0 of the register 3042 (Re). It is drawn in the direction order. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4 bits via D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bits in the LSB that are sequentially output from the receiver circuit 2 via the output " e " as W0b1, W0d1, W1b1, ..., in the direction indicated by the arrow β shown in FIG. 35 as shown in FIG. Data is drawn out in the longitudinal order from B0 in register 3042 (Ra) to W7b1, W0d1, W1b1, ..., W6d2, W7b2 and W7d2 in B7 of register 3042 (Rd). When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

In a portion within the range α indicated by α2, as shown in FIG. 10, the receiver circuit (through the output " d " as W0a3, W0c3, W1a3, ..., in the direction indicated by the arrow β shown in FIG. Bit data in the MSB sequentially outputted from 2) is transferred to B0 of registers 3042 (Rh), W0a3, W0c3, W1a3, ..., W6c4, W7a4 and W7c4 by B0 of registers 3042 (Re). It is drawn out in the vertical order. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4-bits via D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bit data in the LSB sequentially output from the receiver circuit 2 via the output " e " as W0b3, W0d3, W1b3, ..., in the direction indicated by the arrow β shown in FIG. (Ra) is drawn out in the longitudinal order from W0b3, W0d3, W1b3, ..., W6d4, W7b4 and W7d4 to B7 of the registers 3042 (Rd). When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

In a portion within the range α indicated by α3, as shown in FIG. 11, through the output "d" as W0a5, W0c5, W1a5, ... in the direction indicated by the arrow β shown in FIG. Bit data in the MSB sequentially outputted from 2) is transferred to B0 of registers 3042 (Rh), W0a5, W0c5, W1a5, ..., W6c6, W7a6 and W7c6 by B0 of registers 3042 (Re). It is pulled out sequentially in the vertical direction. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4-bits via D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bit data in the LSB sequentially output from the receiver circuit 2 via the output " e " as W0b5, W0d5, W1b5, ... in the direction indicated by the arrow β shown in FIG. (Ra) is drawn out to B7 of registers 3042 (Rd) in the order of the longitudinal direction from W0b5, W0d5, W1b5, ..., W6d6, W7b6 and W7d6. When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

In a portion within the range α indicated by α4, as shown in FIG. 12, through the output " d " as W0a7, W0c7, W1a7, ... in the direction indicated by the arrow β shown in FIG. Bit data in the MSB sequentially outputted from 2) is transferred to B0 of registers 3042 (Rh), W0a5, W0c5, W1a5, ..., W6c6, W7a6 and W7c6 by B0 of registers 3042 (Re). It is pulled out sequentially in the vertical direction. When the data trigger "c" is supplied, 32 bits are output to the bus line "B" in units of 4-bits through D4 to D7 of the latches 3043 (La to Lh).

At the same time, the bit data in the LSB sequentially output from the receiver circuit 2 via the output " e " as W0b7, W0d7, W1b7, ..., in the direction indicated by the arrow β shown in FIG. (Ra) is drawn out in the longitudinal order from W0b7, W0d7, W1b7, ..., W6d8, W7b8 and W7d8 to B7 of the registers 3042 (Rd). When data trigger " c " is supplied, 32 bits are output to bus line " B " in units of 4 bits via D0 to D3 of latches 3043 (La to Lh).

Since 8-bit × 8 columns of data, that is, 8-bytes, output from the data buffer circuit 304 received in one output operation use the upper "a", "b", "c" and "d". The bit data for one block is converted to 8-bit parallel data by performing the previous operation up to 16 times for each 64-bit data as shown in FIG.

The deinterleaving circuit 5 will now be described. The deinterleaving circuits 5 are respectively provided from the decoder section 3 to reproduce the received interleaved block structure D2 according to the received frame type, so as to output the reproduction interleaved block structure D2 to the buffer memory 4014. And controlled by the CPU 401.

14 is a block diagram showing an example of the structure of the deinterleaving circuit 5. The deinterleaving circuit 5 shown in FIG. 14 includes shift registers 501A, 501B, 501C and 501D, rearrangement circuits 502, 503 and 504, and a selector circuit 505.

Each of the shift registers 501A, 501B, 501C, and 501D has a memory whose memory capacity is 8 bits, and receives data from the selector circuit 505 in units of 8 bits. Shift registers 501A and 501B have output terminals coupled to addresses 0 and 1 of rearrangement circuit 502. Shift registers 501c and 501d have output terminals connected to addresses 6 and 7 of rearrangement circuit 504.

The selector circuit 505 has an output terminal connected to the shift registers 501A, 501B, 501C and 501D and is arranged by selecting an address from which data is input to determine the rearrangement circuit, the selection being made by the CPU 401. Under control. The selector circuit 505 outputs data supplied from the RDA to each shift register corresponding to the output of the rearrangement circuit.

To fetch one-byte data from each shift register 501A, 501B to rearrange the two-byte data, the rearrangement circuit 502 handles data with a frame type of 3200 bps (2-level FM). do. Then, the rearrangement circuit 502 sequentially outputs the reproduction data on the bus line "B" in total of 2 bytes in units of 1-byte or 8-bit.

The reordering circuit 503 handles data with a frame type of 3200 bps (4-level FM) to fetch 1-byte data from each shift register 501C, 501D to rearrange the 2-byte data. do. The rearrangement circuit 503 then sequentially outputs two types of data on the bus line "B" in units of 1-byte or 8-bits.

The rearrangement circuit 504 has a frame type of 6400 bps (4-level FM) to fetch one-byte data from each shift register 501A, 501B, 501C, and 501D to rearrange the two-byte data. The data is urgent. The rearrangement circuit 503 then sequentially outputs two types of data on the bus line "B" in units of 1-byte or 8-bits.

The operation of the deinterleaving circuit 5 will now be described. 15 through 17 are diagrams showing the rearrangement operations of the rearrangement circuits 502, 503, 504, respectively, provided to match the frame type / rate. Referring to Figs. 15-17, a portion of 8-bit data RD stored in shift registers 501A-501D to be rearranged and output and corresponding to 4 bits including D0-D1 of input data WR. Is mentioned with respect to the LSB, while some corresponding to 4 bits including D4 through D7 are mentioned with respect to the MSB.

1. For 3200 bps (2-level FM):

As shown in Fig. 15, the rearrangement circuit 502 has two 8-bit data D0 to D7 stored in the shift register 501A and 8-bit data D0 to D7 stored in the shift register 501B. It is supplied by two feeding operations. Then, four odd-order bits (D0, D2, D4, and D6) of 8-bit data supplied to address (1) to be reproduced and output on bus line "B" are rewritten to LSB of address (1). A rearrangement operation is performed such that the array and the four even-order bits D1, D3, D5, and D7 are rearranged in the LSB of the address (0).

On the other hand, the four odd-order bits D0, D2, D4 and D6 of 8-bit data supplied to address 0 to be reproduced and output to bus line "B" are stored in the MSB of address 0. The four even-order bits (D1, D3, D5 and D7) are rearranged to the MSB of address (1).

As above, the rearrangement circuit 502 can reproduce 16-bit (8 bits x 2) data.

2. For 3200 bps (4-level FM):

As shown in FIG. 16, the rearrangement circuit 503 has two 8-bit data D0 to D7 stored in the shift register 501C and 8-bit data D0 to D7 stored in the shift register 501D. It is supplied by two feeding operations. Then, the MSBs (D4, D5, D6, and D7) of 8-bit data supplied to the address (2) to be reproduced and output on the bus line "B" are rearranged to the MSB of the address (2) and the LSB ( A reordering operation is performed such that D0, D1, D2, and D3) are rearranged to the MSB at address 3.

On the other hand, the four MSBs (D4, D5, D6 and D7) of 8-bit data supplied to address 3 to be reproduced and output on bus line "B" are rearranged to the LSB of address 2 and , LSBs (D0, D1, D2 and D3) are rearranged to the MSB at address (3).

3. For 6400 bps (4-level FM):

As shown in FIG. 17, the addresses 4, 5, 6, and 7 of the rearrangement circuit 504 are supplied with 8-bit data stored in the shift registers 501 to 501D, respectively, in four supply operations. When the rearrangement operation is performed, D5 to D7 in the MSB portion are fetched from the input 8-bit data of each address 4, 5, 6 and 7. Then, each 2-bit data is specified from the LSB portion of the address 4 which is output on the bus line "B" so that 8-bit data at the address 4 is formed.

Similarly, D4 and D6 in the MSB portion are fetched from the input 8-bit data in each address 4, 5, 6, 7. Then, each 2-bit data is specified from the LSB portion of the address 5 which is output on the bus line "B" in order to allow 8-bit data at the address 5 to be formed.

Similarly, D3 and D1 in the LSB portion are fetched from input 8-bit data in each address 4, 5, 6, 7. Then, each 2-bit data is specified from the LSB portion of the address 6 outputted on the bus line "B" in order to allow 8-bit data at the address 6 to be formed.

Similarly, D2 and D0 in the LSB portion are drawn from the input 8-bit data in each address 4, 5, 6, 7. Then, each 2-bit data is specified from the LSB portion of the address 7 which is output on the bus line "B" so that 8-bit data at the address 7 is formed.

As above, the rearrangement circuit 504 can reproduce 6400 bps (4-level FM) 32-bit (8 bits x 4) of 8-bit parallel data.

The address comparison circuit 6 will now be described. 18 is a circuit diagram showing an example of the internal structure of the address comparison circuit 6. The address comparison path 6 is, for example, an address register 601 for storing its own address data (21 bits) in advance, and received / reproduced address data with the address data stored in the address register 601. A comparison circuit 602 for comparison and a shift register 603 for outputting an 8-bit coincidence signal " f " that is the result of the comparison performed by the comparison circuit 602 to the bus line " B ".

The operation will now be described. The address field AF5 of the data reproduced by the deinterleaving circuit 5 has been compared with the address data previously stored in its own pager to format the address data that must be combined.

When the comparison circuit 602 has fetch data (data structure in the reproduced address field AF C5) supplied from the bus line "B" in 8-bit units and which is the subject of the comparison, the comparison circuit 602 The fetch data and the address data supplied from the address register 601 (for example, by using an EXOR circuit) are compared. The final result of the comparison is obtained by summarizing the comparison result of each bit (e.g., using a NOR circuit). The result of the comparison is output to the shift register 603. The shift register 603 sequentially retrieves the result of the comparison from the comparison circuit 602 so that an 8-bit coincidence signal " f " representing the result of the comparison of the 8-bit address is output.

The final operation of the circuit for receiving and reproducing data according to the first embodiment will now be described. 19-22 are flowcharts of the main operation of the pager. 23 is a flowchart of the operation of the deinterleaving circuit 5.

The main operation of the pager will now be described. 19 to 22 show the CPU 401 to be performed from the moment the power of the pager is turned on until the completion of the operation for receiving data for one frame in which the operations of the CPU 401 and the decoder unit 3 are connected to each other. This is a flowchart of decoder operation. The operation of the decoder section 3 is described by step R ... and the operation of the CPU 401 is described by step C ....

A predetermined number of bit data that can be reproduced by the deinterleaving circuit 5 is stored in the RDA of the RAM 403, and the CPU 401 senses the timing at which the deinterleaving circuit 5 can perform the regeneration process. In doing so, the CPU 401 always outputs data to the deinterleaving circuit 5 via the bus line "B". The CPU 401 fetches the data from the decoder section 3 to write this data to the RDA, and corrects an error of the data, which is one preceding block stored in the buffer memory 4014 to read the contents. Perform the action.

Therefore, if it is determined that the address data contained in the received address field AF5 does not match in terms of the match signal supplied from the address comparison circuit 6, the control is performed by the decoder section 3 and the receiver. The operation of the circuit 2 is performed to be interrupted.

19-22, data receiving and reproducing processes will now be described. If the CPU 401 determines that power has been supplied by an operation of a power supply switch (not shown) in step C1, the CPU 401 causes the power to be supplied to individual circuit parts connected to the CPU 401 and the parts Initialize At this time, the initialization operation is performed so that control data for controlling the received data buffer circuit 304 corresponding to each frame pattern is set in the frame rate determining circuit 302 and the level determining circuit 301. The operation of the section 3 is also started. The decoder section 3 then enters a standby state in the upper and frequency bands set by the ID-ROMs (steps R1 and R2). In this standby state, when the synchronization 1 (S1) C1 of the synchronization signal unit D1 is received, the CPU 401 will operate from 1.875 seconds (one frame) to 10 seconds at an interval of 30 seconds for 2 minutes until synchronization is detected. An internal timer (not shown) is started to perform intermittent reception within the period of (step C3). Then, synchronization detection is performed by receiving synchronization 1 (S1) C1 until a predetermined time has elapsed (steps C4 and C6).

If synchronization is detected, the dynamic proceeds to step C5 so that the timer is reset, and the frame pattern data set by synchronization 1 (S1) C1 is stored in the buffer memory 4011. If no synchronization is detected within two minutes and a predetermined time has elapsed, the pager is moving or staying outside the service area. Therefore, the operation proceeds to step C7 where the fact that the pager is out of the service area is displayed on the display unit 7. In addition, the area departure notification interrupt signal for interrupting the area departure notification output by the notification unit 8 when the pager is outside the area is output.

When the decoder unit 3 receives the synchronization 1 (S1) C1, the decoder unit 3 draws it out and the level determining circuit 301 is set by the synchronization 1 (S1) C1 and the frame pattern data related to the modulation method. To store the data contained in the data (step R3). The decoder section 3 also causes the frame rate determination circuit 302 to store data in the frame pattern data set by the synchronization 1 (S1) C1 and related to the frame rate (step R4). The received frame pattern data is also output to the CPU 401.

The decoder unit 3 continues the intermittent reception in steps R2, R3, and R6 until the area deviation notification interrupt signal is received by the CPU 401 in step C7. When the out of range notification interrupt signal is received, the operation proceeds to step R7 where the operation of the receiver circuit 2 is interrupted.

After step R4 is performed, in step R5 the decoder unit 3 receives the frame information F1 C2, and then receives the received cycle number and the received frame number to obtain its own frame from the frame information F1 C2. This timing information is output to the CPU 401. In step 8, since the frame itself occurs, the CPU 401 has its own frame in accordance with the timing information supplied to the timing from the decoder section 3 and the frame information 42B (F1) in order to interrupt the operation of the receiver circuit 2. Recognize the position of. Since the frames are preceded by their own frames one by one, the process in step C8 continues until the timing for the frame one preceding the own frame (step C9). Control to interrupt the operation of the receiver circuit 2 is performed by the decoder unit 3 under the control of the CPU 401 (step R8). The process in step R8 is repeatedly performed until the re-drive signal is input (step R9).

If the frame timing preceding one by one its own frame is detected in step C9, the CPU 401 restarts the decoder unit 3 in step C10. If the decoder section 3 is instructed from the CPU 401 (step R9), it re-drives the decoder section 3 (step R10) where the decoder section 3 re-drives for the receiver circuit 2. The CPU 401 waits for input of the control signal (step R11). When the re-drive control signal for the receiver circuit 2 is supplied from the CPU 401, the receiver circuit 2 is re-driven in step R12.

The CPU 401 re-drives the decoder unit 3 (step C10), and then sets the address data read from the ID-ROM of the ROM 402 in the step C11 to the hydrogen register of the address comparison circuit 6. In step C12, the CPU 401 determines the output time of the last block of the frame, which precedes one by one its own frame. When the timing of the last block is detected, the CPU 401 outputs an operation control signal to the receiver circuit 2 (step C13) (step C13).

When the receiver circuit 2 is re-driven, the decoder unit 3 achieves synchronization with synchronization 1 (S1) C1 of its own frame received in step R13. Further, the decoder section 3 causes the level determining circuit 301 to store data in the frame pattern data of its own frame related to the modulation method and related to the frame rate (step R16). At the same time, the received frame pattern data is also output to the CPU 401.

The decoder unit 3 then draws, decodes, and outputs the frame information F1 C2 in step R14. Since frame type data is also output to the CPU 401 in step R13, the CPU 401 causes the buffer memory 4011 to re-memorize the frame type data in step C14. In step C15, whether the frames match each other is determined according to the decoded frame information F1 C2. If a mismatch is determined, the operation returns to step C8 where the preceding frame timing is waited for one by one in its own frame. If a match is detected, the operation proceeds to step C16 where the own frame is confirmed, the continuous reception is controlled, and the address of the rearrangement circuit is determined by the deinterleaving circuit 5.

The decoder unit 3 outputs the frame information F1 C2 to the CPU 401 in step R14, and then waits for input of an interrupt signal generated when frame mismatch is detected in step R15. If an interrupt signal is supplied, the operation returns to step R8 where the operation of the receiver circuit 2 is interrupted. If no interrupt is supplied, the operation proceeds to step R16. In step R16, synchronization 2 (S2) C3 is received, and then the timing control circuit 303 confirms the synchronization of the reception of the interleaved block structure D2 and makes fine adjustments. In step R17, the received data is rearranged by the received data buffer circuit 304 such that the rearranged data is output as 8-bit parallel data. Next, the operation proceeds to step R18 in which the block information BI C4, the address field AF C5 and the vector field VF C6 set by the synchronization signal unit D1 are input and reception continues.

In step C16, the CPU 401 selects to select any one of the rearrangement circuits 502, 503, 504 to be connected to the selector circuit 505 of the deinterleaving circuit 5 according to the frame type of the subject frame by determining the address to be used. A process for supplying a control signal is also performed (the operation proceeds to step D1 shown in FIG. 23).

After the operation in step C16 is completed, the CPU 401 determines whether the frame type received in step C17 is 1600 bps (2-level FM). If the frame type is 1600 bps (2-level FM), the operation proceeds to step S38 in which the first start word of the address field AF C5 is read from the block information BI C4 and stored in the buffer memory 4013. Next, operation proceeds to step C39.

If a determination is made in step C17 that the data is output in a frame type other than 1600 bps (2-level FM), the operation proceeds to step C18, where the received data is subjected to a bit of data in order for the reproduction process to be performed. The numbers are stored sequentially and stored in the RDA of the RAM 403 until the timing of the reproducing process is reached (step C19). If the number of bits of data that allows the reproducing process to be performed is determined and whether the timing of the reproducing process is made, the operation proceeds to step C20 in which the data is read from the RDA and the data is supplied to the deinterleaving circuit 5. Therefore, the interleaving circuit 5 starts to perform a process for reproducing data (see step D4 shown in FIG. 23).

The operation of the deinterleaving circuit 5 shown in FIG. 23 will now be described. In step D1, the selector circuit 505 determines the address of the rearrangement circuit to store 8-bit data according to the selection control signal for the rearrangement circuit determined in step C16. Then, the operation waiting for input of 8-bit parallel data starts (step D2). If 8-bit history data is confirmed in step D3, the operation proceeds to step D4 in which the input 8-bit parallel data is sequentially stored in the shift registers 501 (A to D) sequentially. As described with reference to Figs. 15-17, the next 8-bit parallel data is output from the individual shift register in step D5 to the address of the rearrangement circuit. The data reproduced by each rearrangement circuit is output again to the bus line "B" in step D6. After the regeneration process in step D6 is completed, steps C21, C25 and C35 are performed.

After the reproducing process in step D6 is completed, the CPU 401 stores this data in the buffer memory 4014 for handing over the error correction process. In step C21, the start word of the address field is read in accordance with the block information BI C4 for storage in the buffer memory 4013. In step C22, the CPU 401 stores the data received in the RDA of the RAM 403. In step C23, the CPU 401 determines whether a predetermined number of bits of data for allowing the reproduction process to be performed and whether the timing of the reproduction process has come. If the storage and reproduction timing of the predetermined number of bits of data are confirmed in step C23, the calculated data are read sequentially from the RDA and output to the deinterleaving circuit 95 in step C24. When data is supplied to the deinterleaving circuit 5 via the bus line "B", the deinterleaving circuit 5 is a frame type except 1600 bps (2-level FM) and the shift register 501 (A in step D3). To D) are reproduced.

Then, when the reproduced data is drawn out from the deinterleaving circuit 5 via the bus line "B", the CPU 401 stores this data in the buffer memory 4014 for an error correction process. The CPU 401 then outputs the address data included in the address field AF C5 to the address comparison circuit 6 (step C25). At this time, the address comparison circuit 6 compares the received address data drawn out through the bus line "B" with the address data in the address register 601 at the timing of the data trigger "C". Then, the coincidence signal " f " indicating coincidence or mismatch is output to the CPU 401.

The CPU 401 instructs the decoder unit 3 to withdraw data. If the CPU 401 has detected a match of the address because it received the match signal "f" from the address comparison circuit 6 in step C26, the operation proceeds to step C28. If no match of the address is detected, the operation proceeds to step C27 in which the CPU 401 sends an interrupt signal to the decoder unit 3. When the interrupt signal is supplied from the CPU 401 to the decoder unit 3, the operation returns to step R8 where the operation of the receiver circuit 2 is interrupted. If the coincidence signal "f" is not supplied, the operation proceeds to step R20. In steps R20 and R21, reception continues until an interrupt signal is received from the CPU 401.

In step C28, the data VF C6 of the vector field is read from the RDA along the address field AF C5, so that the number of words and the initial word in the message field MF C7 are determined. In step C29, the process for interrupting the operation of the receiver circuit 2 is performed until the start word of its own message data appears. When interrupt control starts, only its own message data can be fetched according to the determined start word. Since the decoder section 3 receives the interrupt signal in step R21, the decoder section 3 interrupts the operation of the receiver circuit 2 in step R22, and the above-mentioned state is when the re-drive signal is received. Maintained until.

When the CPU 401 confirms the timing for receiving the start word of its own message data in step C30, the CPU 401 transmits the re-drive signal to the decoder unit in order to re-drive the receiver circuit 2 in step C31. Output to (3). Thus, the receiver circuit 2 receives the data. In step C32, the CPU 401 sequentially stores the data received in the RDA through the decoder unit 3. When the decoder section 3 receives the above-mentioned re-drive signal output in step C31 (step R23), the receiver circuit 2 is re-driven (step R24).

After the data storage in the RDA is started in step C32, the CPU 401 determines whether a predetermined number of bits of data for allowing the playback process to be performed in step C23 and when the timing of the playback process has come. If the timing of storing and reproducing a predetermined number of bits of data is confirmed in step C32, the received data (message data) is sequentially read from the RDA in step C35 and output to the deinterleaving circuit. When the deinterleaving circuit 5 performs a data reproducing process, the data in the next block is stored in the RDA. Then, operation proceeds to step C35.

When the data reproduced by the deinterleaving circuit 5 is output on the bus line "B", the idle block IB C8 is sensed in step C35. When the idle block (IB) C8 is detected, an interrupt signal is output to the decoder section 3 to interrupt the operation of the receiver circuit 2 in accordance with the timing for receiving its own frame. In order to control the reception notification in step C37, the CPU 401 causes the notification unit 8 to notify the reception and reproduces and displays the message according to the received own message data, and then the operation proceeds to step C9. Thus, the CPU 401 waits for the timing of the frame in step C9, which proceeds to its own frame one by one. When the receiver circuit 2 is re-driven in step R24, the decoder section 3 continues the receiving operation until the operation is interrupted in step C36 by the CPU 401 (steps R25 and R26). When the interrupt signal has been received in step R26, the operation proceeds to step R27 where the operation of the receiver circuit 2 is interrupted. The decoder unit 3 then completes the receiving operation.

Thus, the operations of the CPU 401 and the decoder unit 3 have been described to be connected to each other to receive data having a frame pattern other than 1600 bps (2-level FM) according to the result of the determination made in step C17. If the frame type of the received data is determined in step C17 at 1600 bps (2-level FM), the reception operation performed by the CPU 401 is moved to step C38 where an operation in which the reproduction operation is not performed is started.

In step C38, the block information BI C4 is fetched into the buffer memory 4014 and subjected to an error correction process. Then, the start word of the address field AF C5 is stored. In step C39, the CPU 401 outputs the address data stored in the address field AF C5 to the address comparison circuit 6. Thus, the address comparison circuit 6 compares the received address data retrieved via the bus line "B" with the address data in the address register 601 at the timing of the supplied data trigger "C". Then, the address comparison circuit 6 outputs the coincidence signal "f" to the CPU 401.

When the CPU 401 detects the coincidence signal " f " indicating the coincidence of the address supplied from the address comparison circuit 6 in step C40, the CPU 401 moves the operation to step C41. If the coincidence signal "f" is not detected, the CPU 401 moves the operation to step C27 where an interrupt signal is issued to the decoder section 3. When the decoder section 3 receives the interrupt signal from the CPU 401, the operation returns to step R8 where the operation of the receiver circuit 2 is interrupted. If the coincidence signal "f" is detected, the operation proceeds to steps R20 and R21 where reception continues until the interrupt signal is supplied from the CPU 401.

In step C41, the data of the vector field VF C6 is supplied from the receiver circuit 2 along the address field AF C5 to determine the start word of its own message data and the number of words in the message field MF C7. . In step C42, control is performed such that the operation of the receiver circuit 2 is interrupted until the start word of its own message data is detected. When interrupt control is started, only its own message can be fetched according to the determined start word. Since the decoder section 3 receives the interrupt signal in step R21, it interrupts the operation of the receiver call path 2 in step R22 and maintains this state until the re-drive signal is supplied.

When the CPU 401 confirms the timing for receiving the start word of its own message data in step C43, the CPU 401 sends the re-drive signal to the decoder section 3 to re-drive the receiver circuit 2. Output to step S44. Thus, the receiver circuit 2 receives the data, and the CPU 401 sequentially reads its message data in 8-bit units (step 45) and senses an idle block (IB) C8 (step C46). When the re-drive signal output in step C31 is supplied in step R23, the decoder section 3 re-drives the receiver circuit 2 (step R24).

If the idle block (IB) C8 is detected in step C45, an interrupt signal is output to the decoder section 3 to interrupt the operation of the receiver circuit 2 in accordance with the timing for receiving the next self frame. The CPU 401 causes the notification unit 8 to perform the notification process in step C37, and reproduces and displays the message in accordance with the received message data to control the reception notification. Then, the CPU 401 returns the operation to step C9. As above, the CPU 401 waits for the timing for the frame in step C9, which proceeds to its own frame one by one. After the receiver circuit 2 is re-driven in step R24, the decoder section 3 continues the receive operation until the operation is interrupted by the CPU 401 in step C36 (steps R25 and R26). When an interrupt signal is received in step R26, the operation proceeds to step R27 where the operation of the receiver circuit 2 is interrupted. Then, the decoder unit 3 completes the reception operation.

As described above, according to the first embodiment, when the information indicating the frame type (synchronization 1 (S1) C1 is received), the frame type of the data is determined. Therefore, the load distribution to hardware and software can be balanced, so that the size of the circuit and the load on the CPU can be reduced.

(Second embodiment)

The first embodiment has such a structure in which a data receiving operation is performed by the CPU 401 as follows. When the predetermined number of bits of data that can be reproduced is stored in the RDA in the RAM 403 and the timing for performing the reproducing process is reached, a suitable rearrangement circuit is arranged in plural in the deinterleaving circuit 5 according to the frame type of the received data. Is selected from the rearrangement circuit of. The address of the data reproduced by the selected rearrangement circuit is placed in the comparison process. If a match is detected, its own data in the message field is retrieved and the playback process is performed.

However, according to the first embodiment, the CPU 401 controls data transportation between the RAM 403, the deinterleaving circuit 5 and the address comparison circuit 6, and the complicated control of the data transportation causes data to be reproduced. In addition to the main operation is required. Therefore, a problem sometimes arises because of the slow data processing speed.

Thus, the pager according to the second embodiment is provided with a DMA (direct memory access) circuit 11. Thus, when the CPU 401 performs a data receiving operation, as shown in FIG. 30, the DMA circuit 11 performs the CPU 401, the RAM 404, and the deinterleaving furnace 5 to perform an error correction process. Then, data transfer is controlled between the BCH decoders 10. Therefore, the load carried by the CPU 401 to carry data is reduced.

Referring to Figures 24-32, the second embodiment will now be described. In the second embodiment, the data structure C and the block structure D shown in Fig. 32 are used.

24 is a block diagram showing the structure of a circuit in a pager as a second embodiment of a data receiving apparatus according to the present invention.

The same elements as in the pager according to the first embodiment and shown in FIG. 1 are designated with the same reference numerals, and the same elements are omitted.

The pager according to the present embodiment includes an antenna 1, a receiver circuit 2, a decoder section 3, a control section 4, a deinterleaving circuit 5, an address comparison circuit 6, a display unit 7 , A notification unit 8, a power supply circuit 9, a BCH decoder 10, a DMA circuit 11 and a key input unit 12.

The control unit 4 controls the overall operation of the pager according to the control program stored in the ROM 404 and includes a CPU 401, a ROM 402, and a RAM 404. The CPU 401 is, for example, a buffer memory 4011 for storing the frame pattern read from the synchronization 1 (S1) C1 for a while, and the data (cycle number, frame number and a plurality of data read from the frame information F1) C2. Buffer memory 4012 for storing the number of output operations) for a while, and buffer information 4013 (vector field VF) for storing data and block information BI C4 read from the vector field VF C5. And a clock generator 4015 for generating a clock for adjusting the timing of the reception process in the message field MF and the address field AF. Equipped. The CPU 401 controls a circuit unit connected to the CPU 401 by using the data and the clock contained in one frame.

As shown in Fig. 25, the RAM 404 is a work area for allowing the CPU 401 to operate, and one supplied from the decoder section 3 at the time of performing the receiving operation so as to be used to reproduce the received data. A memory area BDM (block data memory) in which an 11-block address of received data for a frame is allocated in units of blocks, and a memory area for storing received message data.

The BDM stores data for one frame that is received and played back by assigning an address.

As will be mentioned later, the data so stored is output to the deinterleaving circuit 5 under the control of the DMA circuit 11. The data reproduced by the deinterleaving circuit 5 is re-memorized at the same storage address, and then output to be subjected to an error correction process in the BCH decoder 10.

In the case where the block data includes an address field, the data placed in the error correction process in the address comparison circuit 6 is output again to be placed in the comparison of the address data, and then placed in the address comparison process. If a match is detected, the data is re-memorized in the same sculpture. If a mismatch is detected, the data is deleted without being stored in the DBM.

The BCH decoder 10 corrects an error in the data using an even parity bit and a 10-bit BCH code included in the data for one block reproduced by the deinterleaving circuit 5, and then the number of error bits is stored in the CPU. To 401.

The DMA (Direct Memory Access) circuit 11 stores data via a bus line "B" between the CPU 401, the RAM 404, the deinterleaving circuit 5, the address comparison circuit 6, and the DMA circuit 11. To control transport.

The key input unit 12 is composed of a main switch, a cursor key, and a memory key to output a signal indicating the operation of the key operation to the CPU 401.

The overall operation of the second embodiment will now be described.

26 to 29 are flowcharts of the main operation of the pager. 30 is a timing chart of the operation in the DMA circuit for reading and writing data between the BDA circuit 11 and other circuits.

When the CPU 401 has been powered by the operation of the power supply switch (not shown) in step C101, the CPU 401 allows the power to be supplied to the individual circuit portions connected to the CPU 401, Start working. At this time, when the operation start operation is performed, the operation of the decoder unit 3 is started so that control data for controlling the received data buffer circuit 304 according to each frame pattern is determined by the frame rate determination circuit 302 and the level determination. Is set in the circuit 301. Then, the decoder unit 3 is placed in a standby state above the frequency band set by the ID-ROMs (steps R101 and R102). In this standby state, when the synchronization 1 (S1) C1 of the synchronization signal unit D1 is received, the CPU 401 will operate from 1.875 seconds (one frame) to 10 seconds at an interval of 30 seconds for 2 minutes until synchronization is detected. An internal timer (not shown) is started to perform intermittent reception within the period of (step C103). Then, synchronization detection is performed by receiving synchronization 1 (S1) C1 until a predetermined time has elapsed (steps C104 and C106).

If synchronization is detected, the dynamic proceeds to step C105 so that the timer is reset, and the frame pattern data set by synchronization 1 (S1) C1 is stored in the buffer memory 4011. If no synchronization is detected within two minutes and a predetermined time has elapsed, the pager is moving or staying outside the service area. Therefore, the operation proceeds to step C107 in which the fact that the pager is out of the service area is displayed on the display unit 7. Further, an area departure notification interrupt signal for interrupting the area departure notification output by the notification unit 8 when the pager is outside the area is output.

When the decoder unit 3 receives the synchronization 1 (S1) C1, the decoder unit 3 draws it out and the level determining circuit 301 is set by the synchronization 1 (S1) C1 and the frame pattern data related to the modulation method. The data contained in the data is stored (step R103). The decoder section 3 also causes the frame rate determination circuit 302 to store data in the frame pattern data set by the synchronization 1 (S1) C1 and related to the frame rate (step R104). The received frame pattern data is also output to the CPU 401.

The decoder unit 3 continues the intermittent reception until the area-out notification interrupt signal is received by the CPU 401 in step C107 in steps R102, R103 and R106. When the out-of-area notification interrupt signal is received, the operation proceeds to step R107 where the operation of the receiver circuit 2 is interrupted.

After step R104 is performed, the decoder unit 3 receives the frame information F1 C2 in step R105, and then the number of cycles received by the CPU 401 to obtain its own frame from the frame information F1 C2. And the number of received frames and this timing information. In step C108, the CPU 401 own frame according to the frame information 42B (FI) and timing information supplied from the decoder section 3 until the timing for its own frame comes to interrupt the operation of the receiver circuit 2. Recognize the position of. The process in step C8 continues until the timing for the frame one preceding the own frame (step C109). Control to interrupt the operation of the receiver circuit 2 is performed by the decoder section 3 under the control of the CPU 401 (step R108). The process in step R108 is repeatedly performed until the re-drive signal is input (step R109).

If the frame timing preceding one own frame is detected in step C109, the CPU 401 re-drives the decoder unit 3 in step C110. If the decoder section 3 is instructed from the CPU 401 to re-drive (step R109), it re-drives the coder section 3 (step R110), where the decoder section 3 is the CPU 401. Waits for the input of the re-drive control signal for the receiver circuit 2 (step R111). When a re-drive control signal for the receiver circuit 2 is supplied from the CPU 401, the receiver circuit 2 is re-driven in step R112.

The CPU 401 re-drives the decoder section 3 (step C110), and then, in step C111, the address data read from the ID-ROM of the ROM 402 is set in the address register of the address comparison circuit 6; do. In step C112, the CPU 401 determines the output timing of the last block of the frame, which precedes its own frame by one. When the timing of the last block is detected, the CPU 401 outputs an operation control signal to the receiver circuit 2 (step C113).

When the receiver circuit 2 is re-driven, the decoder section 3 achieves synchronization by synchronization 1 (S1) C1 of its own frame received in step R113. Further, the decoder section 3 causes the level determining circuit 301 to store data between frame pattern data of its own frame related to the modulation method and related to the frame rate (step R116). At the same time, the received frame pattern data is also output to the CPU 401.

Then, the decoder unit 3 extracts, decodes, and outputs the frame information F1 C2 in step R114. Since the frame type data is also output to the CPU 401 in step R113, the CPU 401 causes the buffer memory 4011 to re-memorize the frame type data in step C114. In step C115, whether the frames coincide with each other is determined according to the decoded frame information F1 C2. If a mismatch is detected, the operation returns to step C108 where the frame timing preceding one's own frame is awaited. If a match is detected, the operation proceeds to step C116 where the own frame is identified and subsequent reception is controlled and the address of the rearrangement circuit is determined by the deinterleaving circuit 5.

The decoder unit 3 outputs the frame information F1 C2 to the CPU 401 in step R114, and then waits for input of an interrupt signal generated when frame mismatch is detected in step R115. If an interrupt signal has been supplied, the operation returns to step R108 where the operation of the receiver circuit 2 is interrupted. If no interrupt is supplied, the operation proceeds to step R116. In step R116, synchronization 2 (S2) C3 is received, and then the timing control circuit 303 confirms the synchronization of the reception of the interlocated block structure D2 and performs fine adjustment. In step R117, the received data is rearranged by the received data buffer circuit 304 so that the rearranged data is output as 8-bit parallel data. Then, the operation proceeds to step R118 where the block information BI C4, the address field AF C5 and the vector field VF C6 set by the synchronization signal section D1 are input, and the reception continues.

In step C116, the CPU 401 selects to select any one of the rearrangement circuits 502, 503, 504 to be connected to the selector circuit 505 of the deinterleaving circuit 5 according to the frame type of the subject frame by determining the address to be used. A process for supplying control signals is also performed.

After the operation in step C116 is completed, the CPU 401 determines whether the frame type received in step C117 is 1600 bps (2-level FM). If the frame type is 1600 bps (2-level FM), the operation proceeds to step C127 in which the first start word of the address field AF C5 is read from the block information BI C4 and stored in the buffer memory 4013. Next, operation proceeds to step C128.

If a determination is made in step C17 that the data is output in frame type excluding 1600 bps (2-level FM), the operation proceeds to step c118, where the 8-bit parallel data is allocated to the RAM 404 with the assigned address. Is remembered in the BDA.

When it is determined that the number of bits of data for causing the reproducing process to be stored is determined, the DMA circuit 11 sequentially reads data from the BDM and supplies the data to the deinterleaving circuit 5. Thus, the deinterleaving circuit 5 performs a data reproducing process and re-memorizes the data reproduced at the read address. When one block of data is reproduced, one block of data is read from the BDM and supplied to the BCH decoder 10. The error corrected data of one block is re-memorized at the address read.

Then, the CPU 401 reads the start word of each address field AF5 and vector field VFC6 of the data placed in the error correction process based on the block information BIC4 in step C119.

Next, the CPU 401 instructs to accept the comparison of the address data stored in the BCM of the RAM 404. The DMA circuit 11 reads the address data contained in the reproduced address field AF C5 stored in the BDM and outputs it to the address comparison circuit 6. The address comparison circuit 6 compares the address data received via the bus line "B" with the address data in the address register 601 at the timing of the data trigger "c". Next, the address comparison circuit 6 outputs a matching signal "f" indicating whether or not the address data items coincide with each other to the CPU 401. The CPU 401 instructs the decoder unit 3 to withdraw data. Further, when the CPU 401 receives the match signal " f " from the address comparison circuit 6 in step C120 and detects a match of the address, the operation moves on to step C121. If no address match is detected, the operation proceeds to step C123 where an interrupt signal is output to the decoder unit 3. When the decoder section 3 is supplied with the interrupt signal from the CPU 401, the operation returns to step R108 where the operation of the receiver circuit 2 is interrupted. If the coincidence signal "f" is not supplied, the operation proceeds to step R120 where the receiving operation continues.

In step C121, the start word and the number of words of the own message data in the message field MF C7 are determined according to the vector data in the vector field VF C6. In step C122, data for one frame is retrieved sequentially, and then a storage address is allocated. Next, the data is stored sequentially in the BDM of the RAM 404.

Simultaneously with the reception operation performed by the CPU 401, data sequentially stored in the BDM is repeatedly recorded and read in both the deinterleaving circuit 5 and the BCH decoder 10.

In step C124, an idle block (IB) C8 is detected. When an idle block (IB) C8 is detected, an interrupt signal is output at the timing for receiving the next self frame in order to interrupt the operation of the receiver circuit 2. In step C126, the CPU 401 performs the control of the reception notification by performing a process for reproducing and displaying the message according to the received message data placed in the notification process in the notification unit 8. Then, the operation returns to step C109. As above, the CPU 401 waits for frame timing, which precedes its own frame by one. It should be noted that the receiving operation of the decoder unit 3 continues until the interrupt of the operation is instructed from the CPU 401 in step C125 (step R121). If the interrupt signal is supplied from the CPU 401 in step R121, the operation proceeds to step R121 where the operation of the receiver circuit 2 is interrupted. The decoder unit 3 then completes the receiving operation.

The operations of the CPU 401 and the decoder unit 3 have been described, where they are connected to each other to receive data having a frame pattern other than 1600 bps in accordance with the result of the determination performed in step C117. If the frame type of the received data is detected at step C117 at 1600 bps (2-level FM), the reception operation performed by the CPU 401 is moved to step C127, where the regeneration operation is not performed. It begins.

In step C127, the block information BI C4 is output to the BCH decoder 10 to be subjected to an error correction process, and then stored in the BDM of the RAM 404. Then, the start word of each address field AF C5 and vector field VF C6 is stored in the buffer memory 4013.

In step C128, the CPU 401 outputs the address data included in the address field AF C5 to the address comparison circuit 6. The address comparison circuit 6 compares the address data supplied via the bus line "B" with the address data in the address register 601 at the timing of the data trigger "c". Then, the address comparison circuit 6 outputs the matching signal "f" to the CPU 401. In step C129, the CPU 401 detects the coincidence signal "f" supplied from the address comparison circuit 6. If the addresses match with each other, the operation proceeds to step C130. If no match is detected, the operation proceeds to step C123 in which an interrupt signal is output to the decoder section 3. When the decoder section 3 receives an interrupt signal from the CPU 401, the operation returns to step R108 where the operation of the receiver circuit 2 is interrupted. If the coincidence signal "f" is not detected, the operation proceeds to step R131 where the receiving operation continues.

In step C130, the start word of the own message data and the number of words in the message field MF C7 are determined according to the data of the vector field VF C6.

The CPU 401 causes the receiver circuit 2 to continue the data receiving process in which data is sequentially stored in the BDM in units of one block. In addition, the CPU 401 causes the DMA circuit 11 to continue the data carrying process (step C131). The self message data is then read sequentially, and then an idle block (IB) C8 is detected (step C132).

If an idle block (IB) C8 is detected in step C1312, the CPU 401 outputs an interrupt signal to the decoder section 3 to interrupt the operation of the receiver circuit 2 with respect to the timing for receiving the next self frame. (Step C125). In order to control the reception notification in step C125, the notification process is performed by the notification unit 8, and the message is reproduced and displayed according to the received own message data. Then, the operation returns to step C109. As above, the CPU 401 waits for frame timing in step C109, which precedes its own frame by one. When the interrupt signal is supplied to the decoder unit 3 in step R121, the operation proceeds to step R122 where the operation of the receiver circuit 2 is interrupted. Next, the decoder unit 3 completes the reception operation.

The operation performed by the DMA circuit 11 will now be described with reference to the timing chart shown in FIG. The timing chart shown in FIG. 30 shows the operation of the DMA circuit 11 to carry data for one block (block # 0) when data of frame type, for example 6400 bps (4-level FM) is received. Shows. The frame type is 6400 bps (4-level FM) and the data received by the receiver circuit 2 is decoded into parallel data by the decoding section 3 by 8 bits each. When parallel data is output on the bus line "B", the address is assigned to the BDM formed in the RAM 404 under the control of the CPU 401 and stored sequentially.

The DMA circuit 11 operates simultaneously with the reproduction process and sequentially accesses data between 8-bit parallel data stored in the BDM. Data of block # 0 having a predetermined number of bits that can be reproduced is read sequentially and supplied to the deinterleaving circuit 5. After the data reproducing process is completed by the deinterleaving circuit 5, the reproduced data is output to the BDM again and recorded at the same address.

As described above, when data having a frame type of 6400 bps (4-level FM) is received, the DMA circuit 11 performs the BDM and deinterleaving circuit 5 until the regeneration process for one block is performed four times. It repeatedly outputs and receives block data.

In order for the BCH decoder 10 to BCH-decode the data written after the BDM by the DMA circuit 11 (correct the error), the CPU 401 causes the DMA circuit 11 to read the data from the BDM again. The same is output to the BCH decoder 10. After the BCH decoder 10 completes the error correction process, the corrected data is again output to the BDM and written to the same address. During the error correction process performed by the BCH decoder 10, the DMA circuit 11 is then stored in the BDM to follow the instructions from the CPU 401 to output the same to the deinterleaving circuit 5 for reproduction. Accesses data in block (block # 1). In the case shown in Fig. 30, a process is performed in which data is output to the deinterleaving circuit 5 relating to a process for reproducing (twice and three times) data in the next block.

If the corrected block is data in the address field AF C5 (block # 1 or blocks # 1 and block # 2), the CPU 401 reads the address data in the data written after the BDM by the DMA circuit 11. The same is output to the address comparison circuit 5 so as to be compared with the address data of the ID information. If the coincidence signal "f" is detected from the address comparison circuit 6, the address data is written after the BDM.

Simultaneously with the address comparison process performed by the address comparison circuit 6, the next process is repeatedly performed in the DMA circuit 11. The reproduced data (data of block # 3) is repeatedly carried from the BDM to the BCH decoder 10, and the next data (data of block # 4) output from the decoder unit 3 and stored in the BDM is deinterleaved circuit ( Approach to supply 5).

As described above, according to the second embodiment, controlling data transfer between the CPU 401, the BDM of the RAM 404, the deinterleaving circuit 5, the address comparison circuit 6, and the BCH decoder. A DMA circuit 11 for is additionally provided in the structure of the first embodiment, so that the load carried by the CPU 401 for data transportation is reduced.

31 is a circuit diagram showing a variation of the second embodiment. As shown in FIG. 31, the structure according to this variant has a PC module with an interface 15, a receiver module 14 formed of a circuit board for a personal computer, an interface 16 for a PC card slot, or the like. One portable data terminal 17 is included.

Referring to FIG. 31, the receiver module 14 includes an antenna 1, a receiver circuit 2, a decoder unit 3, a buffer memory 4011 to 4014, a clock generator 4015, a ROM 402, RAM 404, deinterleaving circuit 5, address comparison circuit 6, BCH decoder 10, DMA circuit 11, and interface 15 capable of outputting and receiving data in bus line "B". do. The portable data terminal 17 is a CPU 401 for controlling data reception and reproduction processes, a display unit 7, a notification unit 8, and a CPU for controlling a circuit in the portable data terminal 17. (13) is provided.

Although both the first and second embodiments of the present invention are applied to the only pager that is adapted to the paging system STD-43, the present invention is not limited to this system. The present invention will be applied to both an information communication terminal and a data communication device connected to a personal computer.

For example, the present invention can be applied to any pager adapted to the data communication method in which information on the definition or modulation method of the data frame rate can be output. In this case, even if a paging service company uses a plurality of paging systems mixed, the pager related to the present invention will be applied.

.

Claims (27)

Receiving means for receiving interleaved data in any of a plurality of interleave times; First deinterleaving means for changing the arrangement of data received by said receiving means; Second deinterleaving means for changing the arrangement of data changed by the first deinterleaving means again; And And control means for controlling the operation of the second deinterleaving means based on the interleaved type of data received by the receiving means. The method of claim 1, And said control means controls whether or not to operate said second deinterleave means based on an interleaved type of data received by said receiving means. The method of claim 1, The second interleave means has a plurality of data rearrangement furnaces for changing the arrangement of data, And said control means selects one of said plurality of data rearrangement circuits based on an interleaved type of data received by said receiving means. The method of claim 3, Data storage means for dividing the data output from the first deinterleave means into data items of a predetermined unit amount, and storing the divided data items in sequence; Reading means for reading the divided data items in the order stored from the storing means, and supplying the read data items to one of the plurality of data rearranging circuits selected by the selecting means; And a storing control means for storing the data output from the selected data rearrangement circuit in the address of the divided data items read by the reading means of the data storing means. The method of claim 3, Data storage means for storing data to be processed once by one of the plurality of data rearrangement circuits selected by the selection means; Detection means for detecting a timing of causing data rearrangement to be performed on one of the plurality of data rearrangement circuits selected by the selection means, and And storing control means for sequentially transferring data from said data storing means to said data reordering circuit, and storing data output from said first deinterleave means in said data storing means in turn. Receiver. The method according to any one of claims 1 to 5, And the interleaved data is data interleaved by multiplexing data of independent phases. The method according to any one of claims 1 to 5, The interleaved data has information indicating an interleaved type of the data. And said control means comprises means for extracting information representing said interleaved type from data received by said receiving means. The method of claim 7, wherein And a buffer memory in the interleaved type information storage means for storing and holding the information indicating the interleaved type extracted by the extraction means until the information indicating the new interleaved type is extracted by the extraction means. Device. The method of claim 7, wherein And the information indicating the interleave type includes information indicating a transmission speed of data. The method of claim 7, wherein And the information indicating the interleave type includes information indicating a data modulation method. The method of claim 7, wherein And the information indicating the interleave type includes first information indicating a data transmission rate and second information indicating a data modulation mode. The method according to any one of claims 1 to 5, The first deinterleave means includes a shift register circuit for sequentially storing data output from the receiving means, and a latch circuit for outputting the data stored in the shift register circuit in a changed arrangement order. Device. In claim 12, The shift register circuit is composed of shift registers N (where N is an integer) having M bits (where M is an integer). The latch circuit is composed of M latches having a configuration number of N, The data receiving apparatus is characterized in that the data at the same bit position of the N shift registers is supplied to the same latch circuit. The method according to any one of claims 1 to 5, And said first deinterleaving means has switching means for switching the arrangement of the arrangement of the received data on the basis of the interleaved type of the received data. The method of claim 14, The first deinterleave means includes L shift receiver groups for storing received data, where L is an integer; A latch circuit for changing and outputting data stored in the L shift register groups in the arrangement order; The switching means is a means for switching the L shift register groups as independent shift registers or as one register connected in series based on an interleaved type of received data. Device. The method of claim 15, The L shift register group is composed of registers N (N is an integer) each having M bits (M is an integer), And said latch circuit is constituted by M latches having L x N bits, and wherein data at the same bit position of the register is supplied to the same latch. The method of claim 14, The first deinterleaving means has interleaved type detecting means for detecting an interleaved type of received data; And said switching means switches the mode of data arrangement change received on the basis of the interleaved type detected by said interleaved type detecting means. The method of claim 17, The interleaved data has information indicating an interleaved type of the data. And said interleave type detecting means detects information indicating said interleave type among data received by said receiving means (2). The method of claim 18, The information indicating the interleaved type includes information indicating a data modulation method. And said switching means switches the mode of arrangement of received data on the basis of information indicating a data modulation method detected by said interleaved type detecting means. The method of claim 17, And said interleaved type detecting means stores and stores the detected type information until it detects new interleaved type information. The method according to any one of claims 1 to 5, ID code storing means for storing an ID code for specifying a call of the data receiving apparatus; Detection means for detecting an ID code from the reproduction data while the data array change processing by the second deinterleave circuit is continued; And an interrupt means for stopping the rearrangement process of the rearrangement circuit if a match is not detected by comparing the detected ID code with the ID code stored in the ID code storage means. . The method according to any one of claims 1 to 5, It further comprises an interface for establishing a connection with an external device, And the reception processing of the data reception device is executed based on a control signal supplied from the external device through the interface. Receiving interleaved information data according to one of a plurality of interleaved types; A first array changing step of changing the arrangement of the received data; A second arrangement changing step of changing again the arrangement of the received data which has been changed in the first arrangement changing step; And controlling the execution of the second array change step based on the interleaved type of the received data. The method of claim 23, wherein And said controlling step is a step of controlling whether or not to execute a second array changing step. The method of claim 23, wherein And wherein said controlling step executes a second array changing step only if the interleaved type is a predetermined type. The method of claim 25, There are a plurality of the predetermined types, And said second array changing step selects one of the rearrangement circuits provided corresponding to each type based on the interleaved type. The method of claim 23, wherein And a step of switching the format of data array change by the first array change step based on the interleaved type.

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