KR100253795B1 - An 8-way smp system and a method for minimizing traffic in order to maintain coherency of the system - Google Patents

Abstract

PURPOSE: The system for eight-way symmetrical multi-processor and the method for minimizing the coherency traffic of the system is provided to secure the performance and scalability of the system, to minimizing the unnecessary bus bandwidth and memory access time. CONSTITUTION: The system comprises eight pentium processors(29-36), the multi-port memory control block(20), three pentium pro-buses(24,25,26), four I/O bridges(37-40), the coherency filters(21,22,23), and the shared memory(27,28). Eight pentium processors are mounted on two pentium pro-buses(24,25) for removing the restraint of the electronic loaded number. Four I/O bridges are connected to the third pentium pro-buses(26) for connecting with large capacity I/O unit. The multi-port memory control block processes the memory request cycles occurred by eight pentium processors and four I/O bridges, and deliveries the bus cycle to the other remote buses by using the coherency filters. The coherency filters has the same structure like the tag of a cache memory, and are implemented by the SRAM which the access time is under 10ns.

Description

8-Way Symmetric Multiprocessor System and How to Minimize Its Maintaining Traffic

The present invention provides a high performance symmetric multi-processor system using an MPU having a cache memory using snooping as a method of maintaining data coherency with shared memory. The present invention relates to a computer system structure that can secure performance and scalability of a system by using multiple buses for implementation and minimizing the number of cache memory data homogeneity bus cycles occurring between the multiple buses. In particular, due to bus protocol and electrical limitations, Intel's Pentium Pro processor and its buses are designed to configure only multiprocessor systems with four or fewer processors. Pentium Pro processor to scale to processor system Maintain cache memory data homogeneity to ensure system performance and scalability by minimizing the number of bus cycles multiplexing and maintaining cache memory data homogeneity between eight Pentium Pro processors spread across multiple buses. A computer system using a coherency filter, and a method of minimizing traffic to maintain the homogeneity of the system.

1 is a block diagram of a symmetric multiprocessor system that can be implemented using an Intel Pentium Pro processor and a chipset supporting chips. Up to four Pentium Pro processors (3) with cache memory (2), a memory controller (4) for connecting shared memory (5), and an I / O bus bridge (6) for connecting with the I / O bus. Share the pro bus (1).

However, the Arbitration Bus of the Pentium Probus 1, which the four processors 3 use to determine the license of the bus 1, allows only up to four Bus Agents, It is not possible to implement high-performance multiprocessor systems that support more than four processors. Therefore, Intel's Pentium Pro processor (3) and its bus (1) initially had enough bus bandwidth (533 Mbyte / Sec) that could be used by four processors and up to two I / O bus bridges (6). It is designed to provide.

2 is a configuration diagram of a multiprocessor system supporting up to eight processors using a memory controller 9 capable of connecting two Pentium Proverses 7 and 8. The memory controller 9 is limited to the arbitration bus of the Pentium Probus 1 of FIG. 1 so that four Pentium Pro processors 3 can be mounted on two identical Pentium Probuses 7 and 8 respectively. It serves as a bus bridge to overcome. Thus, although the system structure of FIG. 2 may implement a multiprocessor system supporting up to eight Pentium Pro processors, performance is not as good as that of a multiprocessor system having four processors.

Pentium Pro processor 3 uses MESI (Mofified / Exclusive / Shared / Invalid) protocol to maintain homogeneity of cache memory 2 connected to bus 1. This protocol guarantees that all cache memories have only the most recent copy of the data. This protocol is provided by hardware and is possible by all processors sharing the bus cycle type, address and cache status bus of the Pentium Probus 1. However, most 8-Way Pentium Pro processor systems are multiple cache structures connected to multiple buses, requiring proper mechanisms for maintaining cache homogeneity between these buses.

Data present in the cache 2 of the processor connected to the Pentium Proverse 7 of FIG. 2 may also exist in the cache 2 of the processor connected to the Pentium Probus 8, but in any case all caches are the most recent. It should have only data from. That is, when a processor connected to the Pentium Proverse 7 wishes to change the contents of data present in its cache, it must inform the other processor of this fact. The way to advertise is to snoop the homogeneity cycle for changing the contents of the cache and change the state of the cache itself. In other words, it invalidates the cache state that it has, or if it has changed data, it invalidates the changed data by putting it on the bus. By doing this, cache homogeneity can be maintained in multiple cache systems, and the mechanism for maintaining such cache homogeneity should be applied to multiple buses. However, in the case of a multi-bus system, since the buses are physically different from each other, the bus cycles occurring on one bus cannot be snooped on the other bus, and thus the memory controller 9 responsible for the bus switch or the bus bridge 9 Must transfer all bus cycles occurring on one bus to the other bus. However, because the Pentium Probus only provides bus bandwidth enough for four processors to use a single bus, the buses will saturate in cycles to keep the processors homogeneous. In other words, rather than an increase in performance due to an increase in the processor, a decrease in performance occurs.

The present invention was devised to solve the above problems, using Pentium Probus that supports only up to 4 Pentium Pro processors, while guaranteeing processor scalability corresponding to the increase of the processor. It is a first object to provide a new multibus symmetric multiprocessor architecture capable of implementing a multiprocessor system with up to Pentium Pro processors, and a method of minimizing traffic to maintain the homogeneity of the system. To provide a second object.

1 is a block diagram of a conventional symmetric multiprocessor system.

2 is a block diagram of another conventional symmetric multiprocessor system.

3 is a block diagram of a symmetric multiprocessor system according to the present invention;

4 is a waveform diagram

The present invention for achieving the above first object, the multi-port memory control block; A central processing unit including a cache connected in parallel to the multi-port memory control block; A shared memory connected in parallel to the multiport memory control block; A homogeneous retention filter connected in parallel to the multiport memory control block; And an input / output bus bridge connected in parallel to the multi-port memory control block.

In addition, the present invention for achieving the second object, in the method for minimizing the traffic in order to maintain the homogeneity of the symmetric multiprocessor system, homogeneous retention filter that can represent caches of multiple processors connected to one processor bus By employing, by selectively transmitting the memory request generated in the three buses to the remote bus, it characterized in that to minimize the traffic.

Hereinafter, the operation principle of the present invention will be described in detail with reference to the accompanying drawings. In the present invention, in order to overcome the limitations of the arbitration bus in the bus protocol of the Pentium Probus, four processors are distributed on two buses. This allows only four processors to be connected to each bus, and the bus bridge responsible for the connection of two buses (actually three) can be used to arbitrate bus requests from two buses.

In addition, because the 100 MHz Pentium Probus only allows up to five bus agents on one bus due to the limited number of electrical loads, four processors and I / O bridges on one Pentium Probus, as shown in the prior art of FIG. Connecting the two together could not work at the maximum 100 MHz clock supported by the Pentium Proverse. In the present invention, to solve this problem, a third Pentium Proverse is required, and up to four input / output bridges can be connected using this.

Therefore, the problem solved by the present invention is for a multiprocessor system structure using three Pentium Probuses and having eight Pentium Pro processors, and eight Pentium Pro processors and four I / O buses distributed over three Pentium Probuses. In this connection, it is designed to operate on a bus clock of up to 100Mhz, and cache data homogeneity cycles occurring between cache memory and shared memory of processors and input / output bridges connected to three buses to all three buses. The "homogeneous filter" circuit was created to prevent performance degradation due to increased processor throughput.

3 is a system block diagram constructed in accordance with the present invention. Eight Pentium Pro processors (29-36) with cache memory to implement an 8-Way SMP feature two Pentium Probuses to address the Pentium Proverse specification and the limitations of the number of electrical loads to operate at 100 MHz clocks. 24-25) are respectively mounted, and four input / output bridges 37-40 are connected to the third Pentium Proverse 26 to connect a large capacity input / output device. These three Pentium Probuses are interconnected by a multiport memory control block 20 connected to two shared memory systems for handling the memory processing requests generated by the three Pentium Probuses. That is, the multi-port memory control block 20 handles memory request cycles generated by processors and input / output bridges connected to three Pentium Probuses. It serves to transfer to two remote buses. For example, if the Pentium Pro processor 29 issues a memory request cycle to the Pentium Proverse 24 at T2 shown in the waveform diagram of FIG. 4, the multi-port memory control block decodes this memory request cycle to process this. Decide if you want to. This decision is made before the T6's Pentium Pro processor bus is placed in the "Snoop Phase." If only the memory data can be read or written, it may need to be transferred to another bus (25) or (26). At this time, the multi-port memory control block 20 generates the same memory request to the Pentium Probus 25-26 as is generated in the Pentium Probus 24 as if it were a Pentium Pro processor.

In order to determine whether the multiport memory control block 20 will have memory request cycles occurring at T2 on the Pentium Pro bus 24 going to the memory 27, 28 or forwarded to another Pentium bus 25, 26? Homogeneous retention filters 21-23 are used. The homogeneity maintenance filter has a structure similar to that of a cache memory tag and can represent caches of a Pentium Pro processor, and is implemented as an SRAM having a memory access time of less than 10 ns. The amount of SRAM depends on the cache memory capacity of the Pentium Pro processor and how many processors are connected. For example, assuming that the Pentium Pro processor has an address of 36 bits, a cache memory of 1MB, and a cache line size of 32 bytes, the required SRAM capacity is calculated as in Equations 1 and 2 below.

Number of cachelines a homogeneous filter has ≥ (1 MB / 32-Byte) * 8 (CPU) = 256K lines

Number of data bits required for homogeneous filter = 36 (64GB address)-5 (32-byte cacheline size)-18 (cache entries with total PPros = 256K lines) + 2 (status bits) + 1 (parity bits) = 16

The 2-bit status bit indicates Invalid / Shared / Owned so that the status of the Pentium Pro processor cache can be seen from the outside. The processor's cache is marked as Exclusive or modified. If it is marked as Modified, the cache indicates that it owns an homogeneous retention filter. That is, if the caches of the Pentium Pro processors connected to Pentium Probus 25 and 26 have the data needed by the memory request that occurred at Pentium Probus 24 at T2 time, and what state (shared) Or modified ownership or exclusive ownership) by reading the homogeneous retention filters 21, 22, 23 at time 4 T4. That is, if the state of the homogeneity filter 22, 23 on the remote bus is owned or shared, the memory request from 24 is passed to the bus 25 or 26 to update the state of the remote processor cache by snooping. Do it. However, if they are invalid, they can read or write memory data without interfering with the remote bus.

The status bit of the homogeneity maintenance filter serving as a representative of the multiple caches connected to the multiple buses may be represented by a status bit of 2 bits for one cache line.

Invalid: A copy of the memory data is not in the cache of any processor.

Share: Memory data copy exists in one or more processor caches.

-Owned: A copy of the memory data exists in a single cache, either modifiably or exclusively.

Now, an example of how the state of the homogeneous retention filter changes will be described to explain how to implement a multi-bus multiprocessor system with eight processors.

-The status bit of the homogeneous filter is reset to invalid when the system is reset.

When a processor connected to the Pentium Proverse 24 requests a memory access request (BRIL) for the exclusive use of one cacheline,

The multiport memory control block 20 reads the cacheline from the memory 27 or 28 and passes the BRIL to the requesting processor, and the state of the cache connected to the processor will change from invalid to exclusive.

This processing is possible without interference with other Pentium Proverses because it is marked invalid in the remote homogeneous filters 22 and 23 read in T4 of FIG.

The memory control block 20 also changes the entry of the local homogeneity filter 21 to possession.

Afterwards, the processor retains the state of the homogeneous filter because the processor's cache changes from monopoly to modified without any cycles on the Pentium Proverse 24. That means you can.

A processor connected to another Pentium Probus 25 presents BRIL on the bus 25 for exclusive use of the same cacheline and first checks the remote homogeneous filter 21 marked as proprietary, as in T4 of FIG. do. In this case, the multiport memory control block makes a "deferred response" to this BRIL, passes the BRIL to the Pentium Proverse 24, and changes the ownership state of the homogeneous filter 21 back to an invalid state.

At this time, the cache exclusively or modified by the processor connected to the bus 24 is also invalidated by BRIL transmitted from the remote bus. If the state of the cache was modified, the data changed with HITM # is output to the bus. Implicit writeback occurs.

The data changed by the absolute reply is sent to the shared cache and processor cache requesting BRIL, which received the delayed response on the bus 25. Thus, any cache can have a copy of the most recently changed data.

However, if the cache connected to bus 24 was in a monopoly state, the state of this cache line would simply be invalid and BRIL of bus 25 would receive data from memory.

Whatever the case, the homogeneous filter 22 of the bus taking the cacheline is changed from void to proprietary.

By maintaining the data homogeneity between the cache and the memory of the multiple processors distributed in the multiple buses by the above-described homogeneous filter, it has been proved that it is not necessary to transfer all the bus transactions to the remote bus as in the case of FIG. Accordingly, it can be expected that the performance and scalability of the 8-way Symmetric Multiple Processor System (SMP) according to the present invention are superior to those of FIG. 2.

As described above, the present invention has eight Pentium Pro processors, overcoming the limitations of each Pentium Probus arbitration bus by interconnecting three Pentium Probuses and two memory ports by a multiport memory control block. Symmetric multiprocessors can be implemented. In addition, each Pentium Probus takes up to five electrical loads to solve timing problems that occur when operating at a clock of 100 MHz.

In order to ensure performance and scalability as an 8-Way Pentium Pro processor system, homogeneous retention filters have been devised to minimize unnecessary bus bandwidth and memory access time. This makes it very economical to scale from a single Pentium Pro processor system to a multiprocessor system with up to eight Pentium Pro processors, depending on your needs. That is, the performance is linearly increased by adding only processors to the system according to the user's performance requirements.

Claims (11)

A multiport memory control block; A central processing unit including a cache connected in parallel to the multi-port memory control block; A shared memory connected in parallel to the multiport memory control block; A homogeneous retention filter connected in parallel to the multiport memory control block; And And an input / output bus bridge connected in parallel to the multiport memory control block. 8-Way symmetric multiprocessor system. The 8-Way symmetric multiprocessor system of claim 1, wherein the system is based on an Intel Pentium Pro processor. 8. The 8-Way symmetric multiprocessor system of claim 1, wherein multiple buses are used to implement the system. 4. The 8-Way symmetric multiprocessor system of claim 3, wherein one or more of the multiple buses are used as input / output buses. The 8-Way symmetric multiprocessor system according to claim 4, wherein the input / output bus cycles are selectively transferred to the processor buses according to the content maintaining filter of the homogeneity maintaining filter to maximize the bandwidth of each bus. . 3. The 8-Way symmetric multiprocessor system of claim 2, wherein the system can operate at a clock of 100 MHz by using three Pentium processors and connecting only up to five bus agents to each bus. 3. The 8-Way symmetric multiprocessor system of claim 2, wherein the Pentium Pro processor bus is multiplexed to extend the system to a multiprocessor system having up to eight processors. 8. The system of claim 7, wherein the performance and scalability of the system can be guaranteed by minimizing the number of cache memory data homogeneity bus cycles occurring between the eight Pentium Pro processors distributed over the multiple buses. 8-way symmetric multiprocessor system. 9. The 8-Way symmetric multiprocessor system of claim 8, wherein a coherency filter is used as a means for maintaining homogeneity of the cache memory data. A method of minimizing traffic to maintain homogeneity in a symmetric multiprocessor system, employing a homogeneous retention filter that can represent caches of multiple processors connected to one processor bus, thereby screening for memory demands on three buses. And minimizing the traffic by transmitting to a remote bus. 11. The method of claim 10, wherein the multiprocessor system is four or more symmetric multiprocessor systems.

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