KR100252509B1 - Fault Management Using M-bus in Switch Module of Mass Communication System - Google Patents

Abstract

PURPOSE: A method for managing a failure using an M bus in an HSSF(High Speed Switching Fabric) of an AICPS(Advanced Information Communication Processing System) is provided to check states of state registers of each board by reading the states at regular time intervals in the HSSF, so as to smoothly perform a failure management relating to the HSSF. CONSTITUTION: An HSSA(High-Speed Switching Unit)(210) and each of HSCAs(High-Speed Channel Units)(220-1-220-16) have command registers(CMD)(242), state registers(STAT)(241), and channel ID registers(CHID)(244), to identify each board by channel IDs. The HSSA(210) reads the state registers(STAT) of each board at predetermined time intervals. If present state data read from the state register registers(STAT) are different from prestored state data of the same board, the HSSA(210) analyzes the present state data according to bits, by a predetermined regulations, and decides whether a failure is generated.

Description

Method of managing faults using M bus in HSSF of AICPS

The present invention relates to a high speed switch module (HSSF) in a large capacity communication processing system (AICPS), and more particularly, to a method of managing a failure by using an M bus of the high speed switch module.

In general, a public telephone network is a communication network for transmitting voice signals to other subscribers in a network by performing circuit switching according to call requests of telephone subscribers, and a packet switching network is a communication network for transmitting digital data between computers through packet switching. Although these networks tend to be integrated with each other as the B-ISDN is promoted, they are still composed of individual networks, so the procedures for exchanging services between networks have been very complicated.

Almost all households and companies are subscribed to the public telephone network and are used most widely, but the service is mainly voice-based telephone service. However, as the information society progresses, data transmission between computers is widely required, and various information providers are on the rise and the demand for access to packet networks is rapidly increasing. Therefore, the type of service connected to the packet switching network has been increased by using the telephone line used in general homes, and for this purpose, an information communication processing system has been introduced into the connection between the public telephone network and the packet network.

In the conventional communication processing system, as the network evolves, a wide variety of networks, such as an ISDN network, a frame relay network, an ATM network, and the Internet, have been newly established. In order to connect them integrally and to further increase processing capacity, FIG. As shown, it has been improved with a large capacity communication processing system.

1 is a block diagram illustrating a general mass communication processing system, wherein the mass communication processing system 100 includes a telephone network matching device (TNAS) 110 for connecting to a public telephone network 101, an ISDN network 102, and the like. ISDN matching device (INAS: 130) for connection, packet network matching device (PNAS: 120) for connection with packet communication network 103, ATM network matching device (ANAS :) for connection with high speed (ATM) communication network 104 140), a frame network matching device (FNAS: 150) for connection with the frame relay network 105, an Internet matching device (WNAS: 160) for connection with the Internet 106, and a high speed switch for connecting the matching devices with each other. Module (HSSF: 170), unit system management device (LOMS: 180) for network management, ONAS (182) for accessing unit system management device, etc., connected to public telephone network or ISDN (PC or Hitel terminal) Connect to the information provider (IP or CP) connected to the other network.

In such a high-capacity communication system, the high-speed switch module (HSSF) needs to switch packets input and output through the TAXI bus at high speed, and is provided with an H bus for packet switching and an M bus for OAM. In addition, fault management in the high speed switch module (HSSF) is so severe as to cause service interruption of the entire system. Therefore, fault management is required in the high speed switch module.

Accordingly, the present invention has been proposed to meet the above necessity, and an object thereof is to provide a fault management method using an M bus in a high speed switch module (HSSF) of a large capacity communication processing system.

In order to achieve the above object, in the method of the present invention, an arbitration exchange board and a subscriber I / O board are connected to an M bus including an address bus, a data bus, and a control signal line, so that a packet frame can be exchanged through an H bus. In the high speed switch module of the communication processing system, the arbitration switching board and the subscriber I / O board are provided with command registers, status registers, and channel ID registers, and the boards are identified by unique channel IDs. If the current state data of each board is read at a predetermined time interval and the current state data read from the state register is different from the previously stored state data of the same board, the current state data is analyzed according to a predefined rule for each bit to determine whether there is a failure. Characterized by judging.

1 is a configuration example of a general mass communication processing system,

2 is a block diagram of a high speed switch module to which the present invention is applied;

3 is an address format of an M bus according to the present invention;

4 is a flowchart of managing a fault using an M bus according to the present invention.

* Explanation of symbols for main parts of the drawings

101: public telephone network 102: ISDN

103: packet network 104: high speed communication network

105: frame network 106: Internet

110: telephone network matching device 120: packet network matching device

130: ISDN matching device 140: ATM network matching device

150: frame matching device 160: internet matching device

170: high speed switch module 180: unit system management device

201,202,203: M-bus 210: HSSA

220-1 to 220-16: subscriber input / output unit (HSCA)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

High Speed Switching Fabric (HSSF: High Speed Switching Fabric) is a device that exchanges data in packet units with 32 x 32 capacity through a high-speed parallel common bus. -High speed channel unit (HSCA) for data input / output by frame through serial communication with various network matching devices, H bus for packet frame exchange and M bus for OAM It consists of a backplane that accommodates it.

Here, the H bus is a parallel common bus having a transmission capacity of about 640 Mbps, a 64-bit data bus that is a transmission path of packet frames, a control signal for transmitting an address bus and frame data used to select a channel of each subscriber input / output unit. It consists of With the mediation and exchange function of HSSA, it checks the state of each packet input / output unit (HSCA) packet frame buffer and analyzes the header of frame so that it can be exchanged to the destination automatically. ), It is implemented as a self-routing structure that supports broadcasting and multicasting.

2 is a block diagram illustrating a high speed switch module to which the present invention is applied. FIG. 3 is a data format used on an M bus.

As shown in FIG. 2, the fast switch module to which the present invention is applied includes an arbitration exchange unit (HSSA) 210 and a plurality of subscriber input / output units (HSCA: 220-1 to 220-16) that are commonly connected to an M bus. The M bus is divided into a data bus (HPD [7: 0], 201), an address bus (HPA [7: 0], 202), and a control signal line (HPC [], 203). Although not shown in the drawing, the arbitration switching unit (HSSA) 210 and the plurality of subscriber input / output units (HSCA: 220-1 to 220-16) are connected through an H bus to provide a packet switching function. HSCA) is connected to the matching board (HSNA) of network matching devices through the TAXI bus to transmit and receive subscriber packets.

Referring to FIG. 2, the M-bus is composed of HPD [] for transmitting necessary data for management, HPA [] corresponding to an address for selecting each channel and type of operation, and a control signal. On the HPA bus, it is divided into HPAS \, which indicates that the address is valid, HWR \, which controls reading and writing, and HPDTACK \, which indicates the response of the data transfer.

The HPA [] bus is composed of the HSSA, which is responsible for selecting each subscriber I / O channel for the management of the high-speed switch module (HSSF), collecting the necessary management information, and recovering or initializing itself in the event of a failure or if necessary. Use commands to distinguish delivery. It is also used for channel selection to set MGID (Multicasting Group IDentifier) for each channel for exchange operation. As described above, the format of the address generated by the HSSA is a 32-bit address b31 to b0, and b31 to b8 are " 2F5000 " It is an address on the local bus, and b7 to b0 are driven on the M bus as HPA [].

At this time, among addresses driven on the M bus, b7 is an undefined bit as '0', and b6 to b1 are channel IDs (CH ID) from) to 63. B0 indicates a read or write to the MID, and a '0' indicates a command write or a status read.

Therefore, when assigning MID for the designated channel through M bus, designate the channel as b6 ~ b1 of HPA [6: 0], set b0 to '0', and then transfer the MID data to HPD [7: 0]. After driving, the control signal HWR \ is written to light. When reading status from the designated channel, specify the channel by b6 ~ b1 of HPA [6: 0], set b0 to '1', and read the control signal HWR \. The state data is driven.

Referring back to FIG. 2, an arbitration exchange (HSSA) 210 includes an M-bus control function 230 and an HSCA emulation portion 240, and the M-bus control function 230 includes an arbiter 231. Buffers 232, 233, and 234. Each subscriber input / output unit (HSCA: 220-1 to 220-16) and the HSCA emulation portion 240 have the same configuration, and are composed of buffers 246, 247, 248, decoder 245, and registers 241, 242, 243, 244. That is, the buffer for transmitting data is a bidirectional buffer, the buffer for delivering an address is a unidirectional buffer, and the buffer for transmitting control signals is a bidirectional buffer. In the channel ID register (CHID: 244), a channel ID uniquely assigned to each board is stored, and the decoder DEC 245 decodes an address driven through an address bus so that an address on the address bus is a channel. If it matches the ID, it enables its registers so that data can be read or written over the data bus. The multicasting register (MGID: 243) is for storing the multicasting group ID, the command register (CMD: 242) is for storing instructions, and the status register (STAT: 241) is for storing state. .

As such, the control through the M bus is mapped to the memory area of the local processor in the HSA, and when the address of the processor is interpreted to have a default value of $ 2F500000, the subscriber I / O unit of each channel through the M bus ( The type of operation for the channel related to the management function of HSCA) is identified. Mainly, LSB 7bit distinguishes each subscriber's input / output channel designation and operation type for the corresponding channel. The operation type can be set / verified by MID register and commands such as reporting or initializing board status.

For example, to set the multicasting group and confirm the set contents, the address of the channel of the corresponding HSCA and HSSA is designated and the contents can be written or read through the data bus D [7: 0]. As shown in Fig. 3, the address has a default value of 2F500000, assigns the corresponding board and channel IDs to the areas b6 to b1, and assigns a value of 0 to b0 corresponding to MGID write and read. Once you have assembled the address for, you can verify it by storing or reading the value of the desired content in the MGID register.

And for the status check and initialization command of the board, the address is set as the above MGID setting by selecting the board and channel and assigning the last b0 to 1 to read the data bus D [7: 0]. You can check commands and execute commands such as initialization for each board or channel with a write operation.

At this time, the status register (STAT) of the HSSA is defined for each bit as shown in Table 1, and the command register (CMD) of the HSSA is defined as shown in Table 2 below. have.

division Display Contents b0 SULIVE \ Active state of H-Bus mediated exchange function b1 WDOG Status of Watch Dog Timer b2 WRFEF Byte data empty status of receiving buffer (FIFO) b3 RDFHF \ Half full state of transmission buffer b4 WRFFEF Empty state of frame unit in receiving buffer b5 - - b6 - - b7 BDINST \ State that board is inserted and power is supplied to

division Display Contents b0 SU_RST \ Initialize polling / moving sequence of Hbus b1 WRFRST \ HSCA emulation function-write buffer initialization b2 RDFRST \ HSCA Emulation Function-Initialization of Lead Buffer b3-b7 - -

In addition, the status register STAT of the subscriber input / output unit HSCA indicates a specific state for each bit as shown in Table 3 below.

division Display Contents b0 SULIV \ HSSA live status on HSCA board via H bus b1 CULIV \ Channel Live Status on HSCA Board b2 RXFEF Empty status in the receiving buffer b3 TXFEF Send buffer half full b4 RXFFEF Empty data in frame unit at receiving buffer b5 - - b6 - - b7 BDINST \ Status of board inserted

4 is a flowchart illustrating a failure management using an M bus according to the present invention. Referring to FIG. 4, in the exemplary embodiment of the present invention, status registers are sequentially monitored for 32 ports at intervals of about 2 seconds to monitor the states of the boards.

In step 401, the following file loop is repeatedly performed to monitor the status of each board connected to the M bus. After a delay of 2 seconds in step 402, the port variable is initialized to 0 in step 403.

In step 404, the state register of the designated port is read to store the state of the current port, and then in step 405, it is determined whether it is the same as the previous state. If the result of the determination is the same (i.e., there is no change of state), the next port is checked, and if it is not the same, a corresponding routine for checking and processing each bit of the status register is performed in step 406, and in step 407 To increase the port number. In step 408, it is determined whether the inspection of all ports is completed, and if so, the process returns to step 401, and the process is repeated after a delay of about 2 seconds.

As described above, the present invention can smoothly perform fault management for the high speed switch module by checking the state by reading the state registers of the boards at a predetermined time interval in the high speed switch module of the mass communication processing system.

Claims (2)

It is connected to the high speed switch module of the high-capacity communication processing system in which MHS consisting of address bus, data bus, and control signal line is connected to HSSA and subscriber input / output board (HSCA) to exchange packet frames through H bus. In Each board is identified by a unique channel ID by including a command register (CMD), a status register (STAT), and a channel ID register (CHID) in the HSA and the subscriber input / output board (HSCA). If the HSA reads the status registers of the boards at predetermined time intervals and the current status data read from the status register is different from the previously stored status data of the same board, the current status data is previewed for each bit. A failure management method using an M-bus in a switch module of a large capacity communication processing system, characterized in that it is analyzed according to a defined rule. The status data of claim 1, wherein b0 indicates a live state of an arbitration exchange board, b1 indicates a live state of a channel of a subscriber I / O board, and b2 indicates a data empty state of a byte unit in a receiving butter. B3 indicates the half full state of the transmission butter, b4 indicates the data empty state in the frame unit of the reception buffer, and B7 indicates whether the board is inserted. Fault management method using M-bus in switch module of system.

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