KR100247075B1 - High speed serial errata situation polyno mial caiculation circuit in reed-soldmon - Google Patents

Abstract

The present invention relates to error correction system using Reed solomon code, particularly in calculating error polynomial position polynomial, error polynomial, erasure position polynomial, number of erasers, erasure overflow signal An error correction system and method in a Reed Solomon decoder for calculating a position polynomial and outputting this and the input syndrome again to calculate an error position.

Description

Error correction circuit in Reed Solomon decoder {HIGH SPEED SERIAL ERRATA SITUATION POLYNO MIAL CAICULATION CIRCUIT IN REED-SOLDMON}

The present invention relates to an error correction system using a Reed solomon code. In particular, in calculating an error position position polynomial, a syndrome polynomial, an eraser position polynomial, an eraser number, and an eraser overflow signal are inputted. The present invention relates to an error correction circuit in a Reed Solomon decoder that calculates an error rudder position polynomial and re-outputs this and a pre-populated syndrome to calculate the error rudder position.

In general, Reed-Solomon (hereinafter referred to as RS) code is widely used for error control in digital communication and storage systems, and RS code for error control is generated during data transmission or reproduction of encoded data. It is used to detect and correct an error, which is a symbol for controlling an error of a symbol unit that finds the position and value of an error through a series of processes using only the received data. The error and erasure are together called an error, and the position of the error is generally represented by one bit because the position of the error can indicate the reliability of the transmitted symbol according to the input timing. The error correcting process including the erasure flag includes an error rudder position having the position of the error rudder as a root. Calculations for polynomials are required, in this regard RE Blahut "Theory and Practice of Error Control Code", Addison-Wesley, 1983 and JLMassey, "Shift Register Synthesis and BCH Decoding", IEEE Transation Information Theory, Vol. 15, PP122-127, Jan, 1969. The circuit using the Berlekamp-Massey algorithm (hereinafter referred to as "BMA") as the circuit for calculating the error position is LERS (Leaner) published by Massey in 1965. There is a circuit using Feednack Shift Register, which calculates the discrepancy from the syndrome and the error location polynomial to be calculated, and if the match is zero, the error location polynomial is left as it is, and the zero is zero. Otherwise, the error position polynomial is newly calculated, and the modified polynomial is placed to calculate the new error position polynomial, and when the value of the degree of conformance is not zero, the new value is calculated. The ever calculating the polynomial. However, the circuit of the above method has a disadvantage in that the multiplier for calculating the error position polynomial is large because the circuit of the above method becomes large, thereby increasing the size of the circuit. This method can be used in digital communication systems that seek high speed due to the large delay time of calculating error position polynomials, or in storage systems that require high-speed access with high capacity storage. There is a difficult problem, and there is a problem that can not be used in the error position polynomial calculation circuit including an eraser.

Accordingly, an object of the present invention is to provide an error rudder position polynomial calculation circuit including an eraser that can be used for high-speed calculation because the circuit size is small and the calculation delay time is small.

Another object of the present invention is to use a Berlekamp-Massey iterative algorithm as an error position position polynomial calculation circuit, and the structure is a serial calculation structure to provide a circuit capable of operating at a fast clock.

According to the present invention for performing the above object, in order to calculate the error polynomial position polynomial in the error correction system using the RS code, the error polynomial, the erasure position polynomial, the number of erasers and the error overflow signal are inputted. Compute the positional polynomial and output it again and the input syndrome.

1 is an error correction system diagram according to an embodiment of the present invention

2 is an internal block diagram of the error rudder position polynomial calculator 105 of FIG.

3 is a detailed circuit diagram of the error rudder position polynomial calculation circuit 201 of FIG. 2.

4A and 4B are control and state flow diagrams of FIG. 3 in accordance with an embodiment of the present invention.

5 is a detailed flowchart of process (4r) of FIG. 4 according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings. In the following, reference numerals are given to components of each drawing, even though the same components are shown in different drawings. Note that they have the same sign. In describing the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or a chip designer, and the definitions should be made based on the contents throughout the present specification.

1 is an error correction system diagram using an RS code used in an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram clarifying the peripheral coupling relationship of the error rudder position polynomial calculating unit 105 in FIG. 1. Referring to FIGS. 1 and 2, the function and configuration of each block will be described.

A syndrome polynomial calculation unit 103 for inputting a code to correct the received word IDATA to calculate a syndrome to output a syndrome polynomial output SYNDPOLYO;

Eraser generating the eraser position polynomial (ERTLPOLY), the number of erasers (NUM-ERA) and the eraser overflow flag (OFL-ERA) calculated by entering the eraser flag (ERAFLG). A position polynomial calculation circuit 101,

An error rudder position polynomial calculator 105 that receives the output of the syndrome polynomial calculator 103 and the erasure position polynomial calculation circuit 101 and calculates an error rudder position polynomial;

An error rudder position retrieval and error rudder value calculator 107 for retrieving the error rudder position from the output of the error rudder position polynomial calculator 105 and calculating an error rudder size value for the retrieved rudder position;

The error rudder position search and error rudder value calculation unit 107 includes an error rudder correction unit 109 for correcting the error rudder by adding an error rudder size to the retrieved error rudder position symbol.

The relationship between the syndrome polynomial calculation unit 103, the erasure position polynomial calculation circuit 101, and the error rudder position polynomial calculation unit 105 is an error of the syndrome polynomial calculation unit 103 as illustrated in FIGS. The signal of the number of erasers (NUM-ERA) and eraser overflow flag (OFL-ERA) of the other polynomial calculation start signal (INIT-ELC), the syndrome polynomial output (SYNDPOLYO), and the eraser position polynomial calculation circuit 101 Input processing to thereby initialize the load control signal (LOAD-B, C), update calculation control signal (UPD-BPOLY), conformance latch signal (UPD-DISCREP), and next conformance calculation part of the error-terminator polynomial (ERTLPOLOY). A calculation control circuit 110 for generating a signal INI-NXTDISC,

An error of calculating the syndrome polynomial output SYNDPOLYO and the eraser position polynomial ERTLPOLY by the output of the calculation control circuit 110 and outputting the recalculated syndrome polynomial output SYNDPOLYO and the eraser position polynomial ERTLPOLY. Another position polynomial calculation circuit 105 is configured.

3 is a detailed circuit diagram of the error rudder position polynomial calculation unit 105 of FIG. 2.

A first shift register 301 for storing an error position position polynomial (ERALPOLY) and a modified polynomial [B (x)],

A second shift register 302 for storing an error position polynomial (ERALPOLY) and an error position polynomial [V (x)],

A third shift register 303 for storing the syndrome polynomial [S (x)],

A delay circuit 310 for delaying a symbol byte of the output-modified polynomial or the error position position polynomial of the first shift register 301 for a predetermined time;

The output symbol of the error position polynomial or the error position position polynomial of the second shift register 203 and the syndrome polynomial output symbol of the third shift register 303 are multiplied, and the next correspondence is added to the galois field [GF (2m)]. A first operation cell 311 for calculating

A second multiplexer 305 for selecting the output of the first operation cell 311 and the output of the third shift register 303 according to a signal of the selection terminal 316 for storing intermediate values;

A next match storage unit 308 for storing the median value for calculating a match to be used for the next calculation from the output of the second multiplexer 305,

A third multiplexer 306 that selects the output of the first operation cell 311 and the signal of the current sum input stage 317 among the signals of the sindorom coefficient stage S0;

A current match storage unit 309 for storing a current match at the output of the third multiplexer 306,

A coefficient signal storage unit 307 for storing a count signal among data of an error position polynomial (ERALPOLY) and an error position polynomial [V (x)] stored in the second shift register 203,

A multiplier for calculating a gallois field GF (2m) by multiplying the output of the first shift register 301 by the output of the current match degree storage unit 309 and the output of the second shift register 302. 2 operation cell 312,

Inverting the output of the current match degree storage unit 309 and multiplying by the output of the coefficient signal storage unit 307, the third operation cell 313 for operation in the gallois field [GF (2m)] by the division operation. )and,

A first multiplexer 304 which selects an output of the third operation cell 313 and an output of the delay circuit 310 according to a signal of the condition selection terminal 315 and applies it to the first shift register 301. It consists of.

4 is a control and operation flowchart for an error rudder position polynomial referred to an embodiment of the present invention;

FIG. 5 is a detailed flowchart of the polynomial calculation in the inner loop of the process (4r) of FIG.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

의 관계에 있다.RS (N, K, d) refers to a Reed Solomon code having a codeword length of N, an information word length of K, and a minimum hamming distance of d. One of the characteristics of the RS code is that d is d = N-K + 1, and NK is the number of parities, and R is R = d-1. If the number of symbols that can be corrected by the RS code is t

Is in a relationship.

A codeword including e erasures is represented by Equation 1 below.

d ≥ 2t + e +1

T errors and e erasures satisfying the above expression can be corrected. The RS decoder for correcting the error is configured as shown in FIG. 1 and is corrected by the following procedure.

The erasure position polynomial calculation unit 101 calculates the erasure position polynomial from the received erasure flag, and the syndrome polynomial calculation unit 103 calculates the syndrome from the received word. The erasure position polynomial calculation unit 101 The error locator polynomial calculation unit 105 calculates the error rudder position polynomial using the eraser position polynomial calculated by the syndrome polynomial calculation unit 103 and the symbols output from the syndrome polynomial. The error rudder position search and error rudder value calculator 107 retrieves the error rudder position from the calculated error rudder position polynomial and calculates an error rudder size (value) for the retrieved error rudder position. The error rudder correction unit 109 corrects the error rudder by adding the error rudder size to the retrieved error rudder position symbol. For the error correction, if the syndrome polynomial is S (X), the error locator polynomial is ∧ (X), and the erasure position polynomial is Γ (X), it can be represented by the following equations (2), (3) and (4).

+

+ ... +

+

+ ... +

(1-

χ)=

+

+ ... +

+

(One-

χ) =

+

+ ... +

+

(1-

χ)=

+

+ ... +

+

(One-

χ) =

+

+ ... +

+

Can be written as

The Berlekamp-Massey algorithm (hereinafter referred to as "BMA") for calculating the error point position polynomial is as follows.

[BMA; Berlekamp-Massey algorithm]

num_era: number of erasers

ofl_era: Flag indicating that the number of erasers is overflowing

deg_b: order of B (x), deg_c: order of ∧ (x)

(χ)=1,

(χ)=1,0)

(χ) = 1,

(χ) = 1,

deg_c = 0, deg_b = 0,

zload_eral = 1, r = 0,

1) if num_era ≠ 0 and r = num_era-1 and ofl_era = then

(χ) =Γ(χ),

(χ)= Γ(χ)).zload_eral = 0 (

(χ) = Γ (χ),

(χ) = Γ (χ)).

else

zload_eral = 1,

2) if r≥2t then stop else

=

.

=

.

(χ) =

(χ)+

χ

(χ).3)

(χ) =

(χ) +

χ

(χ).

≠0and deg_b≥deg_c then4) if

≠ 0and deg_b≥deg_c then

(χ)=

(χ),

(χ) =

(χ),

deg_b = deg_c,

deg_c = deg_b + 1,

goto 6).

=0 or deg_b＜deg_c then5) if

= 0 or deg_b <deg_c then

(χ)= χ

(χ),

(χ) = χ

(χ),

deg_b = deg_b + 1,

6) r = r + 1, goto 1)

이 된다.In the present invention, as shown in FIG. 3, the 2 (d-1) iterations are repeated as in FIG. 4, but the calculation of the degree of conformance (dr) and the steps 3 and 4 of the steps 2 to 6 of the BMA is performed. In order to calculate the coefficients of the polynomials in, 5 sequentially, the circuit size is greatly reduced by reducing the addition and multiplier required for the calculation. In addition, the error rudder position polynomial calculation circuit 201 inputs the syndrome polynomial SYNDPOLY of the syndrome polynomial polynomial calculation unit 103 and the erasure polynomial ERALPOLY of the erasure position polynomial calculation unit 101 as shown in FIG. 2. Calculate the error locator polynomial. The error position calculation circuit 201 shown in FIG. 2 corresponds to the circuit shown in FIG. In the operation of the circuit of the present invention of Figure 3 and the control flowchart of Figures 4 and 5, Figure 4 shows a flow chart of the 2 (d-1) iteration calculation algorithm of the BMA, Figure 5 shows the inner loop in Figure 4 The procedure of sequentially calculating the coefficients of conformance and polynomials is repeated (d-1) times. After all, the number of clocks needed for the total calculation

Becomes

Referring to the BMA and Figures 1 to 5 illustrating the present invention,

)에서의 연산을 위한 셀로서 제1,2연산셀(311,312)은 같은 내부구성의 셀이며, 이는 두 수를 곱하고 그 결과를 제 삼의 값과 더하도록 구성되어있다. 제3연상 셀(313)은 나눗셈을(예를 들면, 곱셈에 대한 역원을 다른 수에 곱하여 나눗셈을 행할수 있음)행하는 셀이다. 신호 S(X)는 입력되는 신드롬 다항식이며, ∧(X)는 출력되는 에러타 위치 다항식으로서 제2쉬프트 레지스터에 연결되어 있다. 제3연산셀(313)의 출력단(321)의 신호는 계수 신호 저장부(307)의 계수신호(331)를 부합도 저장부(309)의 출력으로 나눈 신호이며, 제2연산셀(312)의 출력신호(336)는 현재 부합도 저장부(309)의 출력과 제1쉬프트 레지스터(301)의 출력 계수신호를 곱하여 제2쉬프트 레지스터(302)의 계수신호에 더한 신호이다.제1멀티 플렉셔(304)는 선택단(315)는 상기 BMA의 3항 조건에 맞을 경우에 신호 321의 값을 선택하고 그렇지 않을 경우 제1쉬프트 레지스터(301)의 계수로서 지연회로(310)에서 지연된 신호을 선택하는 신호이다.제2멀티플렉셔(305)의 선택단(316)은 다음 계산에 사용될 부합도를 계산하기 위해 그 중간값을 저장하기 위한 다음 부합도 저장부(333)의 입력을 선택하기 위한 신호로서 부 반복 주기의 처음에는 제3쉬프트 레지수터(303)의 출력 신호를, 그렇지 않을 경우에는 제1연산셀(311)의 출력을 선택한다. 제3멀티플렉셔(306)의 선택단(317)은 현재 사용되는 부합도의 입력을 선택하기 위한 신호로서 반복 주기의 처음에는 입력되는 신드롬의 계수 S(0)를 선택하고 이후에는 항상 제1연산셀(311)의 출력신호를 선택한다.상기 제2멀티 플렉셔(305)의 선택단(316)은 다음 부합도 계산을 위해 매 부 반복 주기마다 처음에는 제3쉬프트레지스터(303)의 출력을 선택하고, 두 번째 이후에는 제1연산셀(311)의 출력를 선택하도록 되어있다.In FIG. 3, the 1-3 shift registers 301-303 are (d-1) byte shift registers for storing the modified polynomial B (X), the error position polynomial X (X), and the syndrome polynomial S (X), respectively. . Delay circuit 310, next, current match storage 308, 309 is a flip-flop that can store symbols (usually bytes) in the delay of the first shift register 301, next, current match storage 308, 309 The next matching degree, the current matching degree, is stored.

The first and second operation cells 311 and 312 as the cell for the operation in λ) are cells of the same internal configuration, which are configured to multiply two numbers and add the result to a third value. The third associative cell 313 is a cell that performs division (for example, multiplication may be performed by multiplying an inverse for multiplication by another number). The signal S (X) is an input syndrome polynomial, and ∧ (X) is an error position position polynomial output and is connected to the second shift register. The signal of the output terminal 321 of the third operation cell 313 is a signal obtained by dividing the coefficient signal 331 of the coefficient signal storage unit 307 by the output of the matching degree storage unit 309, and the second operation cell 312. The output signal 336 is a signal multiplied by the output of the current match storage unit 309 and the output count signal of the first shift register 301 and added to the count signal of the second shift register 302. The selector 315 selects the value of the signal 321 when the selection stage 315 satisfies the term 3 of the BMA, and otherwise selects the delayed signal in the delay circuit 310 as a coefficient of the first shift register 301. The selection stage 316 of the second multiplexer 305 is a signal for selecting an input of a next conformance storage unit 333 for storing the intermediate value to calculate a correspondence to be used in the next calculation. As an output signal of the third shift register 303 at the beginning of the negative repetition period, 1 selects the output of the operation cell 311. The selection stage 317 of the third multiplexer 306 selects the coefficient S (0) of the input syndrome at the beginning of the repetition period as a signal for selecting an input of the currently used conformity, and always after the first operation. The output terminal of the cell 311 is selected. The selection stage 316 of the second multi-flexurer 305 initially outputs the output of the third shift register 303 for every subsequent repetition period for the next matching calculation. After the second selection, the output of the first operation cell 311 is selected.

On the other hand, the operation of the error rudder position polynomial calculation circuit 201 of the present invention, as shown in the example flow chart of Figure 4 (4a) in the initial process, the calculation control circuit 203 is the error rudder polynomial calculation start signal (INIT-XLC) The output of the delay circuit 310 is set to "0" in response to the number of NUM-ERA signals and the eraser overflow flag (OFL-ERA) signal, and the output terminal Bo of the first shift register 301 is "0". 1 ", and the input terminal Bd-1 is " 0 ", and the syndrome coefficient index [s (i)] of the third shift register 303 is the syndrome coefficient index [s () of the syndrome parity number PN. i)] minus [S (i) = SYND (PN-i)], the symbol [SYDN (0)] is set to "0" for the syndrome polynomial [s (0)] and [s (0) = SYDN (0)] and the output of the count signal C0 storage unit 307 of the second shift register 302 are set to "1". The first condition (COND = 1) when the number of erasures is one, the other is 0 (else 0), the number of erasures (NUM-ERA) is "1", and the eraser overflow flag (OFL). ERA) is set from 1 to d-1 [c (d-1: 1)] of the second shift register 302 to erasure position polynomial 1 to d-1 when " 1 " [c (d-1: 1)] = [ERALPOLY (d-1: 1)], COND = 1, otherwise the selection of the third multiplexer 306 when the syndrome symbol [synd (0)] is performed. "0" is recorded in the current match degree storage unit 309 by doing so. On the other hand, when the first condition (COND = 1) and the other [[else 0)] "0", the second shift register 302 is loaded with "1". The total index r and the coefficient index i are set to " 0 ", and the order of the first and second shift registers 301 and 302 and the error polynomial deg-b and c are set to " 0 ". In step 4b), it is compared whether the total index r is greater than a value indicating the last byte d-1 of the second shift register 302. If the total index r value is large in step (4b), the process ends, and if it is small, it is checked whether "1" is loaded in the second shift register 302 in step (4c). If "1" is not loaded in the second shift register 302, "1" is loaded in the first shift register 301, but if it is loaded, "0" is loaded in the first shift register 301. The calculation control circuit 203 receives the error polynomial calculation start signal INIT-XLC, the number of erasers NUM-ERA, and the eraser overflow flag OFL-ERA, and the eraser overflow flag OFL-. ERA) is not "1", the number of erasers NUM-ERA is not "0", the number of erasers NUM-ERA is not "1", and the number of erasers [(NUM-ERA) -2] checks whether the corresponding second condition (COND2) corresponds to the corresponding second condition (COND2) in step (4g). If the second condition does not correspond to the second condition in step (4g), In the second shift register 302, "0" is loaded, and "1" is loaded if the second condition is met. Next, an output DISCRIP of the current match storage unit 309 is "0". Checks whether the degree (DEG-B) of the polynomial of the first shift register 301 and the order (DEG-C) of the polynomial of the second shift register 302 are the same. The current discrepancy is "0". Not or mutual When the numbers are not equal, the output of the delay circuit 310 is selected by the first multiplexer 304 to update the polynomial of the first shift register 301, and when the numbers are equal, the output of the third operation cell 313 is selected. To update it. In the next step (4m), it is checked whether "1" is loaded in the first shift register 301 and if it is not loaded, it is checked whether the output of the third operation cell 313 is selected in step (4n). When "1" is loaded in step (4m), the degree (DEG-B, C) of the first and second shift registers 301 and 302 is the eraser polynomial order (ERA-CNT), and in step (4n) When the value of the first shift register 301 is "1", the order (DEG-B, C) of the first and second shift registers 301 and 302 is matched in step 40, and the first shift register 301 is matched. When the update is not "1", the order of the first shift register 301 is increased in step (4q) (DEG-B = DEG + 1). In step (4r), the internal looping is performed for the polynomial calculation. In the next step (4s), the total index (r) is increased. 5 is a detailed flowchart of the process (4r) of FIG. 4, the process is terminated if the coefficient index (i) reaches the final stage (d-1) in step (5a), and before that the coefficient index ( Check if i) is zero. When 0 in step 5b, the output of the third shift register 303 is selected by the second multiplexer 305 by the signal of the selection stage 316 to load the next match in step 5d. If it is not 0 in step 5b, the output of the second shift register 302 in the first operation cell 311 in step 5c is calculated to calculate the next match. Multiplying the output of the third shift register 303 by the multiplier M2 and adding the output of the multiplier M2 and the output of the next matching storage unit 308 in the adder A2 to the second multiplexer 305. The next match is also recorded in the storage unit 308. Then, in step 5e, it is checked whether the coefficient index i has reached the final value d-2. 303) [s (d-2) = s (0), s (k-1) = s (k) FOR 1 <= K <= d-2] The second shift register in the process (5g). Error polynomial of 302 In order to calculate the equation, the output Bo of the first shift register 301 and the output of the current match storage unit 309 are multiplied by the multiplier M3 of the second operation cell 312 so as to multiply the second shift register 302. Add at output and adder (A1). When the update is not "1" in the first shifter register 301 in step 5h, the output of the first shifter register 301 is delayed to the delay circuit 310 in step 5i, and is "1". In step (5j), the output of the current correspondence storage unit 309 of the third operation cell 313 is inverted by the inverter N1, and a value multiplied by the output of the coefficient signal storage unit 307 is selected. The first shift register 301 is inputted. In step 5k, the first and second shift registers 301 and 302 are shifted from 1 to d-2, and in step 5l, the coefficient index is increased (i = i + 1). However, when the coefficient index is d-2 in step (5e), the output of the first operation cell 311 is selected by the third multiplexer 306 in step (5m) to the current match storage unit 309. In step 5n, the delay circuit 310 is set to "0", the coefficient signal storage unit 307 is set to "1", and the second shift register 302 is loaded with "1" ( Check in step 5o). If it is not loaded in step (5o), the process of (5g) is executed, and if the loading is performed, the output of the current conformance storage unit 309 for loading of the second shift register 302 in step (5p) is It is set to "0", the output of the coefficient signal storage unit 307 is set to "1", and the eraser position polynomial is stored. In step 5q, the first shift register 301 checks whether "1" is loaded, and if the loading is not "1", executes step (5g), and if "1" is loaded, step (5r) B0 is set to "1" for loading into the first shift register 301 at, and stores the eraser position polynomial and increases the coefficient index in step 5l. Based on the above description, if you calculate the error coder position polynomial of RS code that can correct up to four error codes, there are four syndromes, respectively S (3), S (2), S (1), and S (0). Assuming that one erasure flag and one error occur, when the error polynomial calculation start signal INIT_ELC is generated in the syndrome polynomial calculation unit 103, the second shift register 302 has an erasure position. The polynomial, the current correspondence storage unit 309 is 0 symbols, and the third shift register 303 has a syndrome polynomial s_poly (3: 0) = (S (1), S (2), S (3), Loaded into S (0)) to start the first main iteration. In the repetition period, the degree of conformity for determining whether the relationship between the calculated Eraser polynomial and the syndrome is appropriate is sequentially calculated. When the second main repetition period is reached, the calculated match is stored in the current match storing unit 309, the erasure position polynomial is loaded in the first shift register 301, and zero symbols are loaded in the delay circuit 310. If the matching degree is not "0", the first shift register 301 has a value obtained by dividing the second shift register 302 by the matching degree, and the second shift register 302 may determine the matching degree by the first shift register ( Multiply by 301 and have its value added to it (see the effect of multiplying x by allowing c_poly (1) to be entered into the computation). The subsequent calculation process differs only in the process of calculating the degree of conformance, and according to the signal of the selection stage 315 according to the 3rd term or 4th term of the BMA, the input of the first shift register 301 is first received. The multiple shifter 304 is selected, the calculation process of the first shift register 301 is determined as described above, and the second shift register 302 is always calculated in the same manner. In the second main period, the signal syndrome symbol si of the third shift register 303 is multiplied by the coefficient of the second shift register 302, where S (2) is selected and newly calculated, and the next match storage unit 308 In addition to calculating the correspondence to be used next, at the beginning of this period the current conformance store 309 calculates the correspondence calculated from the first main period C (0) S (1) + C (1) S. It is used to calculate a new error position polynomial by latching (0).

The next degree of sum calculated in the main period is C (0) S (2) + C (1) S (1) + C (2) S (0). The next fit calculated at the third main cycle is C (0) S (3) + C (1) S (2) + C (2) S (1), and the current fit is calculated at the second main cycle. Since the fourth main cycle is the last iteration process, the next fit is not of interest, and the current fit computes the errorta position polynomial with the calculated one in the third main cycle. After a total of 4 * 4 = 16 clocks (4 week repetition period, 4 part repetition period), the error position polynomial is calculated, and the error position polynomial circuit can be used for the next step. The shifting operation of the third shift register 303 is controlled to be inhibited only at the end of every subcycle and always performed. Initially, since the third shift register 303, S_POLY = (S (1), S (2), S (3), S (0)), when the first subcycle operation is completed, (S (2), S ( 3), S (0), S (1)), (S (2), S (3), S (0), S (1)) in the second, and (S (3), S ( 2), S (1), S (0)), the fourth is (S (1), S (2), S (3), S (0)) and the syndrome polynomial output (SYNDPOLYO) (S_POLY ( 1), S_POLY (2), S_POLY (3), S_POLY (0)) = (S (3), S (2), S (1), S (0)) If the eraser does not occur, only the error is corrected, and the operation is performed as described below, so that the error position polynomial calculation circuit can be used. It is initialized to B_POLY = 1, C_POLY = 1, S_POLY = SYNDPOLY, CNT_D = S (0). Since the initial match is always S (0) when calculating the match, the current match storage unit 309 is S (0). ) Does not cause any problem in continuous operation Is to discover and apply the features. The first main iteration now calculates the conformance to be used next, as described above (with or without an eraser, once the initialization or loading operation has been performed and then performs the same computational operation), Accordingly, the error rudder polynomial and the modified polynomial are repeated as shown in FIGS. 4 and 5. However, the number of steps required to calculate the error position polynomial at this time is only twice as long as using a circuit capable of calculating only the error position polynomial. In order to compensate for this disadvantage, it is possible to add and control the multiplexer so that the shift operation of the first and second shift registers 301 and 302 becomes (d-1) / 2. And, the codes of Reed Solomon (RS) are mostly used in the form of product codes. In this case, it is common to correct only an error in one code group and to perform error correction for another code group. The present invention is particularly useful because it is configured to correct only errors and error errors.

In another embodiment of the present invention in Figure 3, the syndrome polynomial is initially loaded in parallel and the error position polynomial is output in parallel, and the circuits for controlling the load and output in serial are all easily modified for applications that do not lack timing. It can be used and belongs to the scope of the present invention.

클럭소요)이점이 있다.As described above, the present invention eliminates the shortcomings of a large circuit and a long calculation time in a circuit that calculates a degree of conformance and calculates an error position polynomial using the same, and can operate with a small and fast clock. (

Clock is required).

Claims (2)

In the error correction system of the Reed Solomon decoder, A syndrome polynomial calculation unit 103 for calculating a syndrome by inputting a code to be corrected of the received word IDATA, and outputting the syndrome polynomial (SYNDPOLYO); Eraser Position Polynomial which generates Eraser Position Polynomial (ERTLPOLY), Number of Erasers (NUM-ERA) and Erasure Overflow Flag (OFL-ERA) by inputting Eraser Flag (ERAFLG) The calculation circuit 101, Error of the syndrome polynomial calculation unit 103 and the error polynomial calculation unit 105 and the syndrome polynomial calculation unit 103 for calculating the error polynomial position polynomial by receiving the output of the erasure position polynomial calculation circuit 101. The signal of the number of erasers (NUM-ERA) and eraser overflow flag (OFL-ERA) of the other polynomial calculation start signal (INIT-ELC), the syndrome polynomial output (SYNDPOLYO), and the eraser position polynomial calculation circuit 101 Input processing to thereby initialize the load control signal (LOAD-B, C), update calculation control signal (UPD-BPOLY), conformance latch signal (UPD-DISCREP), and next conformance calculation part of the error-terminator polynomial (ERTLPOLOY). A calculation control circuit 110 for generating a signal INI-NXTDISC, An error rudder position retrieval and error rudder value calculator 107 for retrieving an error rudder position from the output of the error rudder position polynomial calculator 105 and calculating an error rudder size value for the retrieved rudder position; In the Reed Solomon decoder characterized in that it comprises an error rudder correction unit 109 for correcting the error rudder by adding the error rudder size to the retrieved error rudder position symbol of the error rudder position search and error rudder value calculator 107. Error correction system. The method of claim 1, The error rudder position polynomial calculation unit 105 includes a first shift register 301 for storing the error rudder position polynomial ERALPOLY and the modified polynomial B (x); A second shift register 302 which stores the error position polynomial ERALPOLY and the error position polynomial V (x); A third shift register 303 for storing the syndrome polynomial [S (x)], A delay circuit 310 for storing and delaying a symbol byte of an output-corrected polynomial or an error-position polynomial of the first shift register 301 for a predetermined time; The output symbol of the error position polynomial or the error position position polynomial of the second shift register 203 and the syndrome polynomial output symbol of the third shift register 303 are multiplied, and the next correspondence is added to the galois field [GF (2m)]. A first operation cell 311 for calculating A second multiplexer for selecting the output of the first operation cell 311 and the output of the third shift register 303 according to a signal of the selection terminal 316 for storing the intermediate value of the calculation control circuit 110 ( 305), A next match storage unit 308 for storing the median value for calculating a match to be used for the next calculation from the output of the second multiplexer 305, A third multiplexer 306 that selects the output of the first operation cell 311 and the signal of the sindorom coefficient stage S0 according to the signal of the current match input selection stage 317 of the calculation control circuit 110; Wow, A current match storage unit 309 for storing a current match at the output of the third multiplexer 306, A coefficient signal storage unit 307 for storing a count signal among data of an error position polynomial (ERALPOLY) and an error position polynomial [V (x)] stored in the second shift register 203, The output of the first shift register 301 and the output of the current correspondence storage unit 309 are multiplied, and the output of the second shift register 302 is added to calculate the galois field GF (2m). 2 operation cell 312, Inverting the output of the current match degree storage unit 309 and multiplying by the output of the coefficient signal storage unit 307, the third operation cell 313 for operation in the gallois field [GF (2m)] by the division operation. )and, The output of the third operation cell 313 and the output of the delay circuit 310 are selected according to the signal of the condition selection terminal 315 of the calculation control circuit 110 and applied to the first shift register 301. And a first multiplexer (304).

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