KR100246534B1 - Atm cell converter for exchange system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange system, and more particularly to converting time-division multiplexed data of a time division multipexing (TDM) trunk line into an ATM cell, thereby enabling an existing exchange network and an Asynchronous Transfer Mode (ATM) exchange network to interoperate. An ATM cell converter.

It is very expensive to replace all existing telecommunications networks with ATM networks. Therefore, high-speed information networks can be economically established only when the existing telecommunication networks and ATM networks are operated in parallel.

Despite the above situation, since the technology for connecting the existing TDM network and ATM network has not been developed, it is acting as an obstacle in constructing a high-speed information network.

The present invention converts the data applied through the TDM trunk line into an ATM cell and applies it to the ATM switch, so that the TDM network can be connected to the ATM network, thereby efficiently constructing a high-speed information network.

Description

ATMS converter of exchange system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange system, and more particularly to converting time-division multiplexed data of a time division multipexing (TDM) trunk line into an ATM cell, thereby enabling an existing exchange network and an Asynchronous Transfer Mode (ATM) exchange network to interoperate. An ATM cell converter.

In general, since the ATM exchanger exchanges and transfers a variety of information in an asynchronous manner, there is an advantage that the information transfer speed is very fast compared to the conventional synchronous exchange, so efforts have recently been made to apply to a high-speed information network.

However, it is very expensive to replace all the existing communication network with an ATM network, so it is possible to economically construct a high-speed information network only by operating the existing communication network and the ATM network in parallel.

Despite the above situation, since the technology for connecting the existing TDM network and ATM network has not been developed, it is acting as an obstacle in constructing a high-speed information network.

An object of the present invention is to provide an ATM cell conversion apparatus that can connect a TDM network to an ATM network by converting data applied through a TDM trunk line to an ATM cell. There is this.

Another object of the present invention is to provide an ATM cell conversion device capable of smoothly converting input / output ATM cells even when the number of trunk lines is increased four times or more while maintaining the data processing speed.

A feature of the present invention according to the first embodiment is that in an exchange system, operating under the control of a CPU and receiving a clock, a sync pulse signal, and a condition signal, the sync signal, clock, status signal, trunk line number, and timeslot number. A state / timing signal generator for generating and outputting the signal; A serial / parallel converter for converting serially applied data from a trunk line of a TDM type trunk in parallel according to a synchronization signal from the state / timing signal generator; A line data multiplexing unit for time-division multiplexing the data applied in parallel from the serial / parallel conversion unit in each time slot section according to a synchronization signal from the state / timing signal generator; A memory section including a link table, a cell buffer control table, a cell header table, a cell buffer, and a queue of a complete cell buffer; A memory interface unit for matching the memory unit and mediating signals inputted to and outputted from the memory unit by being operated according to a clock from the state / timing signal generator; Perform a state transition operation according to a state signal from the state / timing signal generator, and access the memory unit via the memory interface unit based on a trunk line number and a time slot number from the state / timing signal generator; A data conversion unit for converting data of a trunk line into an ATM cell by writing data received from the line data multiplexer into an ATM cell format, and outputting a write pointer read from the memory unit; A cell transfer control unit which operates according to a synchronization signal from the state / timing signal generator and reads and outputs an ATM cell by accessing the memory unit through the memory interface unit based on a write pointer from the data converter; A FIFO for transmitting an ATM cell applied from the cell transmission control unit to an ATM switching system; And a processor interface unit for matching the CPU to interface and mediate signals inputted and outputted between the CPU and the memory interface unit.

A feature of the present invention according to the second embodiment is that in an exchange system, operating under the control of a CPU and receiving a clock, a sync pulse signal, and a condition signal, the sync signal, clock, status signal, trunk line number, time slot number. A state / timing signal generator for generating and outputting the signal; A serial / parallel converter for converting serially applied data from a trunk line of a TDM type trunk in parallel according to a synchronization signal from the state / timing signal generator; A line data multiplexing unit for time-division multiplexing the data applied in parallel from the serial / parallel conversion unit in each time slot section according to a synchronization signal from the state / timing signal generator; A memory section including a link table, a cell buffer control table, a cell header table, a cell buffer, and a queue of a complete cell buffer; A memory interface unit for matching the memory unit and mediating signals inputted to and outputted from the memory unit by being operated according to a clock from the state / timing signal generator; Perform a state transition operation according to a state signal from the state / timing signal generator, and access the memory unit via the memory interface unit based on a trunk line number and a time slot number from the state / timing signal generator; A data conversion unit for converting data of a trunk line into an ATM cell by writing data received from the line data multiplexer into an ATM cell format, and outputting a write pointer read from the memory unit; A cell transfer control unit which operates according to a synchronization signal from the state / timing signal generator and reads and outputs an ATM cell by accessing the memory unit through the memory interface unit based on a write pointer from the data converter; A FIFO for transmitting an ATM cell applied from the cell transmission control unit to an ATM switching system; A processor interface unit matching the CPU to interface and mediate signals inputted and outputted between the CPU and the memory interface unit; It includes a line data storage unit for temporarily storing the data input and output between the line data multiplexer and the data conversion unit in a predetermined byte unit.

1 is a block diagram of an ATM cell converter of an exchange system according to a first embodiment of the present invention.

2 illustrates a data frame of a trunk line.

3 illustrates a time division multiplexed data frame.

4 shows a link table.

5 illustrates a cell buffer control table.

6 illustrates a cell header table.

7 illustrates a cell buffer.

8 illustrates a queue of completed cell buffers.

FIG. 9 is a view showing the memory map shown in FIG.

10 is an operational state diagram of the data conversion unit shown in FIG.

Fig. 11 is a block diagram of an ATM cell converter of an exchange system according to a second embodiment of the present invention.

FIG. 12 is a diagram showing frame comparison between a line data multiplexer and a data converter in FIG.

Explanation of symbols on the main parts of the drawings

10: serial / parallel conversion unit 11: line data multiplexer

12: data converter 13: status / 'timing signal generator

14: cell transmission control unit 15: FIFO (First In First Out)

16: memory interface 17: memory

18: processor interface unit 19: line data storage unit

The ATM cell converter of the switching system according to the first embodiment of the present invention includes a serial / parallel converter 10, a line data multiplexer 11, a data converter 12, a state / The timing signal generator 13, the cell transmission controller 14, the FIFO 15 (First In First Out), the memory interface 16, the memory 17 and the processor interface 18. . The status / timing signal generator 13 operates under the control of the CPU to receive the clock CLK, the sync pulse signal SYP, and the condition signal to obtain the sync signal, the clock, the status signal, the trunk line number, and the time slot number. To generate a synchronization signal to the serial / parallel conversion unit 10 side, to supply a synchronization signal to the line data multiplexer 11 side, and to provide a status signal, trunk line number and time to the data conversion unit 12 side. The slot number is supplied, the synchronization signal is supplied to the cell transfer control unit 14 side, and the clock is supplied to the memory interface unit 16 side. The serial / parallel conversion unit 10 converts data applied serially from the trunk line of the TDM type trunk in parallel according to the synchronization signal from the state / timing signal generator 13 to the line data multiplexer 11 side. Output to. The line data multiplexer 11 converts the data applied in parallel from the serial / parallel converter 10 in time-division multiplexed within each time slot section according to the synchronization signal from the state / timing signal generator 13. Output to the part 12 side. Then, the data converter 12 performs a state transition operation in accordance with the state signal from the state / timing signal generator 13, so that the trunk line number and time from the state / timing signal generator 13 are performed. Based on the slot number, the memory unit 17 is accessed via the memory interface unit 16 to write the data received from the line data multiplexer 11 into the memory unit 17 in the ATM cell format, thereby providing data on the trunk line. Is converted into an ATM cell, and a write pointer read from the memory unit 17 is outputted to the cell transfer control unit 14 side. The cell transfer control unit 14 operates in accordance with the synchronization signal from the state / timing signal generation unit 13 to operate the memory unit through the memory interface unit 16 based on the write pointer from the data conversion unit 12. 17), the ATM cell is read and transmitted to the FIFO 15 side. The FIFO 15 transfers the ATM cell applied from the cell transfer control unit 14 to the ATM switching system side. In addition, the memory interface unit 16 matches the data converter 12, the cell transfer control unit 14, and the processor interface unit 18 with the memory unit 17, from the state / timing signal generator 13; It operates according to the clock of the controller and mediates the signals input and output to the memory unit 17, and notifies the data conversion unit 12, the cell transfer control unit 14, and the processor interface unit 18 of the arbitration result. The memory unit 17 includes a link table, a cell buffer control table, a cell header table, a cell buffer, and a queue of completed cell buffers. In addition, the processor interface unit 18 matches the CPU to interface signals input and output to the CPU.

Meanwhile, the queues of the link table, the cell buffer control table, the cell header table, the cell buffer, and the completed cell buffer included in the memory unit 17 will be described in detail as follows. The link table is configured as shown in FIG. 4 to connect the time buffer data and the cell buffer of an arbitrary trunk line. The address of each item of the link table is a trunk line number and a time slot number (channel). Number), and the content of each item indicates the number of the cell buffer. The cell buffer control table is configured as shown in FIG. 5 and is used as an area for storing information necessary for operating each cell buffer. Further, the cell header table is configured as shown in Fig. 6 and used as an area for storing header information of each ATM cell. The cell buffer is configured as shown in Fig. 7, and is used as an area for storing one time slot data on a trunk line in order of one byte. The queue of the completed cell buffer is configured as shown in Fig. 8, and a 48-byte cell payload is used as an area for storing the number of the completed cell buffer. Tables, cell buffers, and queues as described above are provided in the memory unit 17. These are arranged in the memory unit 17 in the form as shown in FIG. Is placed.

The ATM cell converter of the switching system according to the first embodiment of the present invention configured as described above operates as follows.

When serial data is applied from each trunk line connected to a trunk of a TDM scheme, the data is applied in the form of a frame in synchronization with a frame sync pulse as shown in FIG. 2, assuming that each K trunk line is provided. Data of each trunk line applied at a specific time may be assigned the same timeslot number. When the serial / parallel converter 10 receives serially applied data from the trunk line, the serial / parallel converter 10 operates according to the synchronization signal from the status / timing signal generator 13 to output the data of the K trunk lines in each time slot. Each time, the data is converted into 8-bit parallel data and output to the line data multiplexer 11 side. Then, the line data multiplexer 11 transmits K 8-bit parallel data applied from the serial / parallel converter 10 in one time slot interval according to the synchronization signal from the state / timing signal generator 13. As shown in FIG. 3, time division multiplexing is performed to output to the data conversion unit 12 side. Thereafter, the data converter 12 writes the 1-byte data applied from the line data multiplexer 11 to the cell buffer, in accordance with the status signal applied from the state / timing signal generator 13. It works. At this time, the data converter 12 performs the same operation by one time slot interval by ending the process at a time obtained by performing one continuous state transition for a time equal to K timeslot intervals. The state transitions are performed in the order as shown in FIG.

A state transition process of the data converter 12 will be described with reference to FIG. 10 as follows. The data converter 12 unconditionally transitions to the reset state ST1 when the reset signal is applied, and transitions to the initial state ST2 when the reset signal is cleared. In the initial state ST2, the data conversion unit 12 is prohibited from accessing the memory unit 17. In this state, the CPU sets various tables in the memory unit 17 and sets initial values. Then, all call setting bits (V) on the link table are made "0" so that no call is set. When this initial process is completed, the CPU sends a control signal to the state / timing signal generator 13 and transitions the state machine managing the data converter 12 in the state / timing signal generator 13 to an idle state. The data converter 12 makes the transition to the idle state ST3. The above process is a process performed only once after the reset signal is applied, and is repeatedly performed after the idle state ST3.

After the idle state ST3, the data conversion unit 12 transitions to the link table access state ST4 at the rising edge of the clock which equals one time slot by K, and the state / link in the link table access state ST4. The call setting bit V and the cell buffer number are read by accessing the link table of the memory unit 17 based on the trunk line number and the timeslot number received from the timing signal generator 13. At this time, if the call setup bit (V) is set to "1", it means that the call is set for the data allocated to the corresponding timeslot of the trunk line, so that the cell buffer number is used for subsequent processing. The memory unit 17 transitions to the cell buffer control table access state ST5, and if the call setting bit V is set to " 0 ", it means that the call is not set. On the other hand, in the cell buffer control table access state ST5, the data converter 12 reads the write segment bit WSEG, the write pointer WPTR, and the effective payload length PAL from the cell buffer control table. The selection of a specific item in the cell buffer control table, that is, the cell buffer number read in the link table access state ST4 is used as the access address. Thereafter, the data conversion unit 12 transitions to the comparison state ST6. In the comparison state ST6, the data conversion unit 12 compares the write pointer WPTR with the effective payload length PAL and transitions to the next state according to the comparison result. .

That is, the data converter 12 compares the write pointer WPTR and the effective payload length PAL in the comparison state ST6, and when the write pointer WPTR is equal to the effective payload length PAL, the cell buffer is the same. After transitioning to the access state ST7, the data received from the line data multiplexing unit 11 is written to the cell buffer, and then transitioned to the cell buffer control table access state ST8. The cell buffer is transferred to the cell buffer control table access state ST8. Prepare a new cell buffer by setting the write pointer (WPTR) of the control table to "0", and transition to the queue access state (ST9) of the complete cell buffer, and the cell in which data has been recorded in the queue access state (ST9) of the complete cell buffer. The number of the buffer is written to the queue, and the state is shifted to the idle state ST3 to perform the repeating operation. The data converter 12 compares the write pointer WPTR and the effective payload length PAL in the comparison state ST6, and when the write pointer WPTR differs from the effective payload length PAL, the cell buffer is different. After transitioning to the access state ST10, the data received from the line data multiplexing unit 11 is written to the cell buffer, and then transitioned to the cell buffer control table access state ST11, and the cell buffer is accessed from the cell buffer control table access state ST11. The write pointer WPTR of the control table is increased by " 1 " to prepare data for recording in the remaining recording area of the cell buffer, and the state is shifted to the idle state ST3 to perform a repeating operation.

On the other hand, when the data converter 12 converts the data applied from the line data multiplexer 11 into a raw ATM cell, the data converter 12 transitions the states ST7 to ST9 in order and transitions the states ST10 and ST11. In the case of converting data into an AAL1 type ATM cell, the operation is performed by transitioning states ST12 to ST15 in order, and then transitioning states ST10 and ST11. When converting data into an AAL1 type ATM cell, the data converter 12 compares the write pointer WPTR and the effective payload length PAL in the comparison state ST6 to compare the write pointer WPTR and the effective payload. If the length PAL is the same, the data transition from the cell buffer access state ST12 to the cell buffer control table access state ST13 is performed after writing the data received from the line data multiplexer 11 into the cell buffer. In the control table access state ST13, a new cell buffer is prepared by setting the write pointer WPTR of the cell buffer control table to " 0 ", and the state transitions to the SN (Sequence Number) recording state ST14, and the SN recording state ST13 In the first buffer of the cell buffer designated by the write segment bit (WSEG), and transitions to the queue access state (ST15) of the complete cell buffer, and the data has been recorded in the queue access state (ST15) of the cell buffer. Buffer number It records and transitions to the idle state ST3 to perform a repeating operation.

As described above, the data conversion unit 12 accesses the queues of the link table, the cell buffer control table, the cell header table, the cell buffer, and the completed cell buffer of the memory unit 17, and the data from the line data multiplexer 11 are stored. The cell transfer control unit 14 accesses the queue of the completed cell buffer provided in the memory unit 17 on the basis of the write pointer WPTR from the data conversion unit 12, and then records the data in the ATM cell format. Read the cell buffer number and read the ATM cell of the cell buffer. First, read 5 byte of the cell header and read the 48-byte cell payload (ATM cell) from the cell buffer by referring to the read segment bit (RSEG). Send it to the ATM switching network side via 15). Meanwhile, the memory interface unit 16 arbitrates signals input and output to the memory unit 17 by the data conversion unit 12, the cell transfer control unit 14, and the processor interface unit 18.

The ATM cell conversion apparatus of the switching system according to the first embodiment of the present invention described above can convert the data applied through the TDM trunk line into an ATM cell and apply it to the ATM switch, so that the TDM network can be connected to the ATM network. Therefore, the high speed information network can be efficiently constructed.

Also, the ATM cell converter of the switching system according to the second embodiment of the present invention provides a line data storage unit 19 between the line data multiplexer 11 and the data converter 12 as shown in FIG. It is further provided. The line data storage unit 19 acts as a buffer between the line data multiplexer 11 and the data converter 12 so that any trunk line data is processed by the line data multiplexer 11 and data conversion is performed. This allows for inconsistencies between the times handled in part 12. When the second embodiment is compared with the above-described first embodiment, there is a difference in the state / timing signal. In the first embodiment, there is one channel number difference between the line data multiplexer 11 and the data converter 12. (In practice, the channel number of the line data multiplexer precedes the channel number of the data conversion section), but in this second embodiment, the state / timing signals shared with each other can access the line data storage 19. There is nothing other than an arbitration signal for avoiding a collision between the line data multiplexer 11 and the data converter 12 at the time. Another difference between the second embodiment and the first embodiment is the size of the trunk line data processed by the data conversion unit 12. In the first embodiment, one-byte data is processed in one cycle. Processes 4-byte data.

The ATM cell converter of the switching system according to the second embodiment of the present invention configured as described above operates as follows.

When serial data is applied from each trunk line, the serial / parallel converter 10 converts the serial data in parallel and is applied to the line data multiplexer 11, and the line data multiplexer 11 time-divisions the parallel data. Multiplex. The time-division multiplexed data is stored in the corresponding area of the line data storage unit 19 according to the trunk line number, channel number, and frame number at the time of application, where the frame number is four frames (hereinafter, referred to as "reference frame"). Is repeated).

The line data storage unit 19 is largely divided into two groups, and each group is alternately used by the line data multiplexer 11 and the data converter 12. The reason is that alignment of trunk line data according to the frame order is made by allowing the data converter 12 to access the remaining group area while the data output from the line data multiplexer 11 is written to one group area during the reference frame period. To maintain. That is, 4 bytes of trunk line data arranged in an arbitrary group area in each frame order during the reference frame period are read by the data converter 12 during the next reference frame period.

The data converter 12 operates with the reference frame as one cycle, but the state machine belonging to the data converter 12 operates with one time slot as in the first embodiment. However, there is a slight difference in the method of determining the amount of data processed by state drinker during one time slot period. The difference is as follows. If the amount handled by the state drinker during one timeslot period is consistent with the number of trunk lines in the manner of the first embodiment, the maximum " trunk lines / 4 " is sufficient in this second embodiment, because The amount of trunk line data input during the reference frame period is "number of trunk lines x number of timeslots in 1 frame x 4 (frames in reference frames)", and the number of timeslots in reference frames is "timeslot in one frame." Is the number of frames × 4 (the number of frames in the reference frame), and in the second embodiment, four bytes are processed as one unit during one timeslot period, so that the amount of data to be processed during one timeslot period is trunked. This is because when considering the number of lines, one can conclude that the number of trunk lines / 4. This means that even if the number of trunk lines is increased four times, the speed of state drinking in the data converter 12 does not need to be increased.

In addition, when the data conversion unit 12 processes only the data of the trunk line in which the call is set, the number of trunk lines can be increased by four times or more, in which case a certain number of call blocking rates are involved.

On the other hand, when the cell is input via the cell transmission control unit via the FIFO, the input cells are stored in the cell buffer and then read by 4 bytes by the data conversion unit according to the trunk line number and channel number of the receiver side in the line data storage unit. The line data demultiplexer reads one-byte data from the line data storage unit according to the trunk line number, channel number, and frame number and sends the data by time division demultiplexing to the serial / parallel conversion unit and serial / parallel conversion. Reverse processing may be performed by converting the additional parallel data into serial data and outputting it to the trunk line.

That is, the ATM cell conversion apparatus of the switching system according to the second embodiment of the present invention described above can input and output cells even when the processing speed of the data conversion unit 12 is maintained as it is when the number of trunk lines is increased by four times or more. I can handle it smoothly.

As described above, the present invention can convert the data applied through the TDM system trunk line into an ATM cell and apply the data to the ATM exchanger so that the TDM network can be connected to the ATM network, thereby efficiently constructing a high-speed information network. Increasing the number of lines by more than four times enables the I / O cells to be processed smoothly while maintaining the data processing speed.

Claims (11)

A status / timing signal generator for generating a frame synchronization signal, a status signal, a trunk signal, and a timeslot number under control of the CPU; A serial / parallel conversion unit for performing a conversion operation between trunk data and parallel data based on the frame synchronization signal; A data multiplexer / demultiplexer for time division multiplexing the converted parallel data and demultiplexing the time division multiplexed data into parallel data; A memory unit; A data converter which writes the time division multiplexed data into the memory unit in a cell form, reads the storage cells of the memory unit, and outputs the data to the data multiplexer / demultiplexer; And a cell transfer control unit for outputting an ATM cell formed by accessing the memory unit to an ATM cell exchanger, and writing the ATM cell transferred from the ATM cell exchanger to the memory unit. The memory device of claim 1, wherein the memory unit comprises: a link table storing a cell buffer number; A cell buffer control table which stores a write segment bit, a read segment bit, a record pointer and an effective payload length of each cell buffer number; A cell header table storing header information of the ATM cell; A cell buffer in which time division multiplexed trunk data is stored; Atm cell conversion device of the switching system, characterized in that the cell payload comprises a queue for storing the number of the cell buffer is completed. The apparatus of claim 1, wherein the data conversion unit further comprises a state machine operated in one time slot period according to the state signal output from the state / timing signal generation unit. A status / timing signal generation unit for outputting a frame synchronization signal, a trunk number, a time slot number, and a conversion synchronization signal under control of the CPU; A serial / parallel conversion unit for performing a conversion operation between trunk data and parallel data according to the frame synchronization signal; A data storage unit; A data multiplexer / demultiplexer for time division multiplexing the parallel data, storing the data in the data storage unit, and demultiplexing the time division multiplexed data read from the data storage unit and outputting the demultiplexed data to the serial / parallel conversion unit; A memory unit; A data converter which reads the stored data of the data storage unit and writes them to the memory unit in a cell form, and reads the storage cells of the memory unit and outputs them to the data storage unit; And an ATM cell accessing the memory unit to form an ATM cell, and comprising a cell transfer control unit for controlling ATM cell transfer between the memory unit and the ATM exchanger. The data storage unit of claim 4, wherein the data storage unit comprises first and second groups, and each group is alternated by the data multiplexing / demultiplexing unit and the data converting unit based on the trunk number, time slot number, and frame number. The AT cell conversion device of the exchange system, characterized in that the access. 5. The AT cell of claim 4, wherein the period of the conversion synchronization signal is N times the frame synchronization signal, and the data conversion unit processes N bytes of data for one period of the conversion synchronization signal. Inverter. It is connected between multiple trunks of TDM method and ATM switch which relays / exchanges ATM cell according to asynchronous transmission method, and converts trunk data into ATM cell and ATM cell transmitted from ATM switch into trunk data. TEM cell inverter. 2. The exchange according to claim 1, further comprising a memory interface for interfacing a signal between the data conversion unit, a cell transfer control unit and a memory unit, and a CPU interface for interfacing a signal between the memory interface and the CPU. AT cell transformation of the system. The memory device of claim 4, wherein the memory unit comprises: a link table storing cell buffer numbers; A cell buffer control table which stores a write segment bit, a read segment bit, a record pointer and an effective payload length of each cell buffer number; A cell header table storing header information of the ATM cell; A cell buffer in which time division multiplexed trunk data is stored; Atm cell conversion device of the switching system, characterized in that the cell payload comprises a queue for storing the number of the cell buffer is completed. An ATM cell converter of an exchange system, comprising: an initialization process of setting a link table, a cell buffer control table, and a cell header table provided in a memory unit; Reading a cell buffer number by accessing a link table of a memory unit according to a trunk number and a timeslot number inputted from a state / timing signal generator; Using the read cell buffer number as an access address, reading a write segment bit, a record pointer, and an effective payload length from a cell buffer control table; Completing the cell payload by recording the multiplexed trunk data in a cell buffer until the read record pointer and the effective payload length are the same; Writing the cell buffer number to a queue when the cell payload is completed; Reading a cell buffer number in which a cell payload is completed from the queue, and reading a corresponding cell header from a cell header table based on the read cell buffer number; And forming an ATM cell from the read cell header and the cell payload and transmitting the ATM cell to the ATM switching system. 11. The method of claim 10, further comprising increasing the recording pointer of the cell buffer control table to record multiplexed data again in the remaining recording area of the cell buffer when the recording pointer and the effective payload length are different. ATM cell conversion method of an exchange system characterized in that.

Images