KR100242289B1 - Mpeg data receiving apparatus using dual port ram - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a device for receiving serial MPEG data using dual port RAM.

2. The technical problem to be solved by the invention

Improving system performance by implementing a central processing unit that can read received MPEG data without having a DM function and an interrupt port.

3. Summary of Solution to Invention

An MPEG data receiving apparatus according to the present invention comprises: serial / parallel conversion means for converting serial MPEG data received from a network into MPEG data in parallel; A dual port RAM having a sample port for data input, a RAM buffer having a predetermined area for temporary storage of data, a RAM array including a plurality of memory cells, and a RAM port for data output; Counting a preset value and outputting a count clock according to the present invention, so that the parallel-type MPEG data inputted to the sample port is temporarily stored in the ram buffer in synchronization with the count clock, and the ram buffer is a data pool. Buffer control means for generating a write address indicating a predetermined memory cell of said ram array so that all data temporarily stored in said ram buffer is written to said ram array; A central processing unit is configured to generate a read address indicating a predetermined memory cell of the ram array by performing a plurality of functions and to read data written in the ram array through the ram port.

4. Important uses of the invention

Set-top box of video on demand.

Description

MPEG data receiver using dual port RAM

1 is a block diagram of an MPEG data receiving apparatus according to the prior art.

2 is a block diagram of an MPEG data receiving apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

100: T1 interface 200: serial / parallel converter

300: central processing unit (CPU) 600: dual port RAM

700: buffer controller 800: multiplexer

The present invention relates to an apparatus for receiving MPEG data, and more particularly, to an apparatus for receiving serial MPEG data using a dual port RAM.

With the recent expansion of digital communication technology and the integration of high-density semiconductor (VLSI) and signal processing (DSP) technologies, video data, audio data, and other data, which have been generated and processed heterogeneously and independently in the past, are used as information sources or media. It can be processed and used in a wide variety of forms without distinction.

In such an environment, there is a need for standardization of international data transmission standards for digital data transmission and sharing between different devices, and according to this need, the Joint Picture Experts Group (hereinafter referred to as "JPEG") And Moving Picture Experts Group (hereinafter referred to as "MPEG") for the transmission of moving images have been standardized.

JPEG was developed with the main purpose of still image processing such as computer graphics. MPEG, on the other hand, stores video on compact disks, digital audio tapes, hard disk drives, optical disks, or other types of telephone lines, integrated services digital networks. It was developed in response to the necessity to transmit via Asynchronous Transfer Mode, communication satellite or satellite broadcasting line. The MPEG can be classified into MPEG1 and MPEG2 according to which compression algorithms are used for video and audio. MPEG1 is a compression standard applied to actual communication systems, and MPEG2 is a compression standard to be applied to future communication systems. The MPEG1 is suitable for applications having a limited number of horizontal pixels of 768, vertical pixels of 576, frames of 30 Hz, and transmission of 1,856,000 bits, for example, CD-ROM, CD-I, video CD, etc. Mainly used video compression standard, it is transmitted at data rate of 1.5Mbps. Data according to the MPEG1 standard (hereinafter referred to as "MPEG data") is transmitted to the communication system through the network at the data rate, and an apparatus for receiving MPEG data is essentially provided on the receiving side of the communication system. A typical communication system using MPEG data is Video On Demand (hereinafter referred to as "VOD").

Referring to FIG. 1, serial MPEG data input to the T1 interface 100 is converted into parallel data through serial / parallel 200 and then written to the FIFO memory 400. When data written to the FIFO memory 400 is filled up to a predetermined area (2 KByte in the case of Set-Top-Box), an interrupt is generated to the CPU 300 to execute DMA. Data stored in the FIFO memory 400 using the DMA function is block transferred to the main memory 500.

In this method, the CPU 300 must support the DMA and Interrupt function, and also periodically transmit data from the FIFO memory 400 to the main memory 500 (when the FIFO memory 400 is in the full state). Since the CPU 300 load is increased. On the other hand, since the other master cannot access the main memory 500 during the DMA operation, when a part of the main memory 500 is used as a frame buffer for graphic data processing, the system performance is reduced because the DMA operation must be waited. Is reduced.

In order to solve this problem, the present invention converts serial MPEG data inputted into the T1 interface 100 into a parallel form through a serial / parallel converter 200 and then directly into the SAM port 610 of the memory 600. Light it. The data written through the SAM port 610 is sequentially stored in the RAM buffer 620 in synchronization with the serial clock SCLK generated by the buffer controller 700. When the data pool is generated in the RAM buffer 620, the buffer is buffered. All data stored in the RAM buffer 620 are write-transmitted to the RAM array 630 at a time by the control signal BCNT generated by the controller 700.

Since the RAM buffer 620-RAM array 630 data write transfer is executed only when the RAM buffer 620 full occurs, the data stored in the RAM array 630 through the RAM port 640 at other times. You can lead at any time. Since the data transfer from the T1 interface 100 to the RAM array 630 of the memory 600 is executed independently of the CPU 300, the present invention can reduce the load of the CPU 300 as compared to the conventional case. In addition to improving performance, the utilization of the CPU 300 may be greatly improved. In addition, the DMA channel and interrupt port are not used, so they can be used for other purposes. In addition, the dual port (SAM port, RAM port) can be used to read and write data simultaneously, improving overall system performance.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 2, the MPEG data input to the T1 interface 100 is sent to the serial / parallel converter 200, and the serial / parallel converter 200 converts the serial data into parallel data. The converted parallel data is sequentially accumulated in the RAM buffer 620 through the SAM port 610 in synchronization with the serial clock SCLK generated by the buffer controller 700. When the amount of data stored is equal to the size of the RAM buffer 620, the RAM buffer 620 is generated, and at this time, the counter value inside the buffer controller 700 is equal to the size of the RAM buffer 620. When the counter value is equal to the size of the RAM buffer 620, the buffer controller 700 is The address is generated along with the signal to write-transmit all data stored in the RAM buffer 620 in the memory 600 to the RAM array 630 at one time.

This series of operations is repeated continuously and at any time while the RAM buffer 620-RAM array 630 write transfer operation is not executed, the CPU 300 transfers all data stored in the RAM array 630 through the RAM port 640. You can lead or write. The multiplexer (MUX) 800 is generated from the buffer controller 700 when the RAM buffer 620-RAM array 630 write transfer operation is executed. Signal and the corresponding address to the memory 600, and in other cases generated by the CPU 300 signal, A signal and an address are supplied to the memory 600 to read or write data from the RAM array 630.

The CPU 300 can execute other kinds of tasks irrelevant to this series of operations since there is no load as well as a DMA or interrupt function while data is being transferred from the T1 interface 100 to the RAM array 630. have. Therefore, the utilization of the CPU 300 can be improved and system performance can be improved. Limited support for DMA channels and interrupt ports can be useful for other purposes, and data transfer rates per unit time can also be improved, as they are data paths that do not pass through FIFO memory.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (3)

An MPEG data receiving apparatus, comprising: serial / parallel conversion means for converting serial MPEG data received from a network into parallel MPEG data; A dual port RAM having a sample port for data input, a RAM buffer having a predetermined area for temporary storage of data, a RAM array including a plurality of memory cells, and a RAM port for data output; Counting a preset value and outputting a count clock according to the present invention, so that the parallel-type MPEG data inputted to the sample port is temporarily stored in the ram buffer in synchronization with the count clock, and the ram buffer is a data pool. Buffer control means for generating a write address indicating a predetermined memory cell of said ram array so that all data temporarily stored in said ram buffer is written to said ram array; And a central processing unit which performs a plurality of functions and generates a read address indicating a predetermined memory cell of the ram array to read data written to the ram array through the ram port. 2. The memory device of claim 1, wherein the buffer control means includes at least counting means for counting a value corresponding to a storage area of the buffer RAM, and outputs the count clock. Device for checking whether or not. 3. The apparatus according to claim 1 or 2, further comprising a multiplexer for multiplexing the write address generated from said buffer control means and the read address generated from said central processing unit.