KR100238687B1 - Digital apparatus for controlling buffer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder of a video signal processing apparatus such as a high-definition television, and more particularly, to a digital buffer control apparatus for maintaining a transmission rate of coded digital video data at a constant level.

A digital buffer control device comprising a discrete cosine transformer for discrete cosine transforming image data and a quantizer for quantizing the image data converted through the discrete cosine transformer, the coded image data being stored and stored in a memory area. A buffer for output and an image data storage state of the buffer are inspected, and when the storage state corresponds to the first section, the threshold mode is determined; when the storage state corresponds to the second section, a forced newization mode is determined; Judging means for determining the normal mode in the case of the third section, and determining the stop mode in the case of the fourth section, and inputting a mode determined by the judging means, and a threshold previously assigned to the determined mode. A threshold value determination unit for determining a hold value and outputting the hold value to the discrete cosine converter; By determining the quantization size of the system is assigned is composed of a determined quantization step size value and outputting the quantized groups.

Description

Digital buffer controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder of a video signal processing apparatus such as a high definition television (HDTV) and the like, and more particularly, to a digital buffer control apparatus for maintaining a transmission rate of coded digital video data at a constant level.

Typically, a digital buffer of a video signal processing apparatus is used to transmit data through a limited channel such as VHF / UHF of terrestrial broadcasting, satellite broadcasting, CATV, recording media of digital VTR, and the like.

The technique for constantly adjusting the bits generated in such a digital buffer is a prerequisite for maintaining optimal quality.

An example of an encoder for a general compensating encoder has a configuration as shown in FIG. 1, which is disclosed in a Motion Picture Expert Group (MPEG) or Motion Comprensated Prediction and Interpolation Coding (MCPIC) standard.

1 is a block diagram of a conventional compensating encoder.

The configuration as shown in FIG. 1 has been mainly used in the field of TV-phone or videocote, and its application to the field of digital HDTV is insufficient. In particular, no specific circuit or control method for controlling the VLC 8 or the quantizer Q 6 in the buffer 10 is disclosed.

Therefore, in the related art, the transmission bit of the coded image data output from the buffer 10 is caused to overflow or underflow according to the output of the variable length coder VLC 8. Not only did the buffer 10 not be utilized efficiently, but there was a problem that affected the restored picture quality at the receiving side.

Accordingly, it is an object of the present invention to provide a digital buffer control apparatus that can solve the above-mentioned problems.

Another object of the present invention is to provide a digital buffer control apparatus capable of improving image quality by maintaining a transmission bit of coded image data at a constant level.

According to an aspect of the present invention, there is provided a digital buffer control device including a discrete cosine transform for discrete cosine transform and a quantizer for quantizing the video data converted through the discrete cosine transform. A buffer for storing and outputting data on the memory area, and an image data storage state of the buffer are examined, and when the storage state corresponds to the first section, it is determined to be a threshold mode, and when it corresponds to the second section. Judging means for judging to a forced newizing mode, judging to a normal mode in the case of the third section, and determining to stop mode in the case of the fourth section, and inputting the judging mode determined by the judging means. A threshold value determination unit for determining a threshold value pre-assigned to a mode and outputting the threshold value to the discrete cosine converter, and a mode determined by the determination means. And a quantization step size value determination unit which determines a quantization stem size previously allocated to the determined mode and outputs the quantization stem size to the quantizer.

1 is a block diagram of a conventional compensating encoder.

2 is an example of parameters and mode resistance applied to the present invention.

3 is a digital buffer control flowchart of the present invention.

4 is a block diagram of a digital buffer control apparatus according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is an example of the parameters and mode resistance applied to the present invention.

(2a) of FIG. 2 shows that the threshold value and the quantization step size value of each mode are allocated according to the storage state of the image data stored in the buffer, and (2b) shows that the buffer size is 512 Kbit. This is an example for explaining that the transmission data range for each mode is set by dividing it into four modes, and accordingly, T and N values are divided and controlled.

3 shows a control flow chart for controlling the buffer according to each mode, and shows steps 1 to 16 according to the four modes.

4 is a hardware block diagram of a digital buffer control apparatus according to the present invention, and shows a buffer control block 100 capable of performing the control flow of FIG.

In FIG. 4, the blocks shown outside the buffer control block 100 are the same means as in FIG.

The S / P 101 and the P / S 102 in the buffer control block 100 represent a serial and a parallel converter, respectively, and the write address counter 104 inputs a sampling clock f _s . The write address is applied to the buffer 10 and the ALU 108, and the read address counter 106 inputs the transmission clock to apply the read address to the buffer 10 and the ALU 108.

The ALU (Arithmatic Logic Unit) 108 subtracts the counted write and read addresses from each other and outputs the counted output to the buffer mode determiner 110.

The buffer mode determination unit 110 determines the mode of the buffer 10 in a preset table area in response to the subtraction output of the ALU 108.

Here, the counters 104 and 106, the ALU 108, and the buffer mode determining unit 110 correspond to the mode determining means.

According to the mode determination of the buffer mode determining unit 110, the threshold value determining unit 112 and the quantization step size value determining unit 114 respectively set threshold values and quantization step size values to be pre-assigned. Output to DCT 4 and quantizer Q 6, respectively.

The present invention will be described in detail with reference to FIGS. 2 to 4 described above.

First, in order to transmit HDTV video information having a bandwidth of about 30 MHz to a 6 MHz transmission channel through band compression or DCT conversion, a 16QAM modulation method can be used. Generally, it is about 15Mbps.

At this time, the amount of data generated by the encoder is irregular depending on the characteristics of the input image of the encoder.

As described above, a buffer is required to transmit irregularly generated data through a channel having a constant transmission rate. When using a buffer in this case, the size of the buffer should be considered.

If the size of the buffer is too small and overflow occurs, data loss occurs, which seriously affects the playback image quality. On the contrary, if the size of the buffer is too large, the delay of the transmitted data is too large for the audio and audio. The images will not match each other.

Therefore, the buffer size is determined as in Equation 1 below.

If you apply a digital HDTV case, In this embodiment, the buffer size is approximately 500 Kbit. The currently input image sequence S (m, n), the previously input image sequence S (m, n-1), the buffer's write address W, and the read address corresponding to the transfer bit rate ( If Read Address) is R, Equation 2 below is established.

Once the size of the buffer is determined, it is necessary to determine how to adjust the amount of data generated by the encoder according to the buffer state. Parameters for adjusting the amount of data generation can control the threshold value T, the quantization step N, and passbands of the three-dimensional prefilter, frame or field skipping, and adjust the amount of fine information. When masking the quantized coefficients, the transmission bit rate can be reduced and repeated if necessary by replacing the coefficient closest to the zero matrix with 0 to increase the zero run length. Can be reduced.

Although there are various parameters for controlling the transmission rate as described above, the most basic and effective threshold hold T and quantization step N are used here as parameters.

As shown in (2a), the buffer size is set to 512 Kbit which can sufficiently accommodate 500 Kbit of image information, and the amount of information generated as shown in (2b) according to the input image information is set in the threshold hold mode (0 to 0). 256 Kbit section: 1st section, Forced Updating Mode mode (257 ~ 448Kbit section: 2nd section), Normal mode (449K-496Kbit section: 3rd section), Stop mode (497K ~ 512Kbit section: 1st section) 4 sections), and the size of T and N values were determined according to the respective modes, and the codes were assigned to four cases as feed control codes.

Of course, it can be increased to 8 modes and 16 modes for more precise control, but there is no expectation effect as the complexity increases, and only 4 modes are selected for simplicity of hardware.

Referring to FIG. 3, first, when data is input to the buffer, the read address is subtracted from the write address of the buffer in step 2 by the ALU. The subtracted result is truncated to an appropriate bit (for example, 4 bits) in the bit allocation step of step 3 and discarded into the normal mode search step of step 4.

The searcher of step 4 is composed of a ROM, and the ALU operation result of step 3 is within the normal mode range 448K to 496Kbit as shown in (2b), and the threshold hold value is fixed in step 5, and the quantization step size of step 6 Fix and export the result to the buffer output in step 7.

If it is determined that the normal mode of step 4 is not the normal mode, i.e., the normal mode, in step 8, it is checked in the threshold hold mode search step of step 9 if it is less than the normal mode. The threshold value T decreases as shown in (2a) at the threshold hold value drop, and then returns to the threshold hold search step of step 9.

At this time, if the bit is increased, it is naturally shifted to the forced newization mode of step 11, and in the forced updating mode, the transmission bit rate is increased as a result of the quantization step size down of step 12. Guide in the direction of

On the other hand, if the transition to the non-normal mode of step 9, i.e., the stop mode of step 13 in which the overflow occurs than the normal state, the T value is first increased in the threshold hold rising step of step 14 to reduce the bit rate.

Therefore, when the beet rake starts to decrease, the normal mode search step of step 15 determines whether it is in a normal state, and if it is correct, it is output through the steps 5, 6, and 7, or secondly, the quantization step size expansion of step 16 is performed. The step again attempts to lower the bit rate and feeds the result back to the normal mode input of step 4 to induce normal mode.

Referring to FIG. 4 implemented according to FIG. 3, since the data coming from the VLC 8 is a one-byte stream, the S / R 101 converts the data into parallel 8 bits and inputs the same to the buffer 10. The parallel serial converter (P / S) 102 converts the parallel 8 bits back into serial and outputs them.

The write address counter 104 is required to input data into the buffer 10, and the read address counter 106 is required to output the data.

The write address corresponds to an input bit rate and the read address corresponds to a channel transfer rate (500 Kbit).

The ALU 108 obtains the difference between the addresses and then applies the buffer mode determination unit 110. The buffer mode determiner 110 determines four mode states in accordance with the control content of FIG. 3, and accordingly, the threshold hold value determiner 112 and the quantization step size value determiner 114 perform a threshold hold. By outputting the values and the quantization step values as shown in the table of FIG. 2A, the transmission bit can be adjusted to a constant level.

As described above, the present invention has an advantage in that the buffer output on the encoder side can be constantly controlled, thereby improving image quality.

Claims (3)

A digital buffer control device having an ideal cosine transform for discrete cosine transform and a quantizer for quantizing the video data converted through the discrete cosine transform, for storing and outputting coded image data in a memory area. Examine the buffer and the image data storage state of the buffer, and if the storage state corresponds to the first section, determine the threshold mode; if the second section corresponds to the forced newization mode, the third section Is determined to be the normal mode, and the stop means is determined to be the stop mode, the mode determined by the determination means is input, and the threshold hold value previously assigned to the determined mode is input. A threshold value determination unit for determining and outputting to the discrete cosine converter and a mode determined by the determination means, and is preassigned to the determined mode. And a quantization step size value determiner for determining a predetermined quantization step size and outputting the quantization step size to the quantizer. The digital buffer control apparatus according to claim 1, wherein the image data storage state of the buffer is detected by subtracting a read address from a write address of the buffer. 3. The method according to claim 2, wherein when the mode determined by the determination means is a threshold hold mode, the threshold hold value is previously assigned to 0 and the quantization step value is 1, and the mode determined by the determination means is forcibly updated. In the case of the mode, the threshold hold value is pre-assigned to 1, and the quantization step value is preassigned to 1. When the mode determined by the determination means is the normal mode, the threshold hold value is 2 and the quantization step value is preassigned to 2. And the threshold hold value is 3 and the quantization step value is pre-assigned when the mode determined by the determination means is the stop mode.