KR100236331B1 - Counter - Google Patents

Abstract

A first logic gate for logic operation by inputting a clock signal and a feedback signal, a second logic gate for logic operation by inputting a feedback signal and a reset signal, and a logic operation for inputting logic outputs of a reset signal and a first logic gate A fourth logic gate that inputs and logically operates the third logic gate, an output of the second and third logic gates, an inverter that inverts the output of the third logic gate, and a fourth logic gate according to an input value set by the user. First and second transfer gates for selectively outputting output values and fixed signals that always maintain high levels, and outputting set signals, and selectively outputting and resetting output values and fixed signals of the inverter according to input values set by a user. A set-input stage composed of third and fourth transformer gates for outputting a signal, and a set signal or reset outputted from the set-input stage; Is activated by a signal and the clock signal, the set-is configured to include a flip-flop for outputting a feedback signal to the input stage.

Description

counter

TECHNICAL FIELD The present invention relates to a counter, and more particularly, to a counter in which the size of a counter is minimized and an input of a counter (the time point at which counting starts) starts according to an input setting.

Hereinafter, a conventional counter will be described with reference to the accompanying drawings.

Figure 1 shows the internal structure of a conventional 4bits counter in digital logic.

As shown in Fig. 1, the conventional counter is composed of a plurality of logic gates and flip-flops.

The flip-flop here uses a J-K flip-flop.

In the conventional counter, the first, second, third, and fourth flip-flops 11, 13, 15, and 17 and an input value applied to four flip-flops by a logical operation between the input value and the load signal are 1 A second logic for determining an input value of the first flip-flop 11 by performing a logical operation on the first logic unit 19 to be sequentially determined and the output value and the count value of the most significant bit of the outputs of the first logic unit 19. A second operation of determining the input value of the second flip-flop 13 by performing a logical operation on the output value of the first flip-flop 11 and the output value of the next higher bit among the outputs of the first logic unit 19 and the count value. The input value of the third flip-flop 15 is obtained by performing a logical operation on the output value of the third logic unit 23 and the second flip-flop 13 and the output value of the next next higher order bit and the count value among the outputs of the first logic unit 19. Logic operation of the output value of the fourth logic unit 25 and the third flip-flop 15 to determine the output value of the least significant bit and the count value of the output of the first logic unit 19 W 4 is composed of a fifth logic unit 27, which determines the input to the flip-flop 17.

Here, a clear signal and a clock signal are applied to each flip-flop, and the count signal and the outputs of the first, second, third, and fourth flip-flops 11, 13, 15, and 17 are output. The end gate 29 which carries out the carry out is further comprised.

In addition, a load signal is applied to the first logic unit 19 to perform a logical operation with the corresponding input bit.

The third, fourth, and fifth logic units 23, 25, and 27 are NAND gates 23a, 25a, and 27a for logically calculating the output value of the front flip-flop and the count value, and the output values of the corresponding NAND gates. And two OR gates 23b, 25b, and 27b for performing a logical operation by inputting a value of a corresponding input bit output from the first logic unit 19.

The operation description of the conventional counter configured as described above is as follows.

As shown in FIG. 1, the input bits I ₁ , I ₂ , I ₃ , and I ₄ set a specific input value by the user, and the first, second, The outputs A ₁ , A ₂ , A ₃ , A _{4 of} the third and fourth flip-flops 11, 13, 15, 17 are determined.

In general, the counter should change the logic of the counter depending on the application.

In other words, the fields used vary depending on how the logic of the counter is changed.

It is a counter according to the prior art that is conceived to solve this trouble.

The counter according to the prior art is possible by setting the input value of the counter without changing the logic of the counter even if the application field is different.

Here, the input value set by the user means a value indicating a time point at which the counter counts.

This operation is described as a simple table as follows.

The symbol X represents don't care and the symbol ↑ represents no change in value.

As shown in the table, when the clear signal is "1", the clock signal is unchanged, and the load signal is "0" and the count signal is "1", the counter starts counting.

When the clear signal is "1", the clock signal is "don't care", the load signal is "0", and the count signal is "0", the counter does not count. That is, it does nothing.

Of course, as a condition for implementing such a table, the user must set an input bit, that is, an input value indicating the start point of the counter.

Therefore, when the counter starts counting, it means that the counting operation starts according to the input value set by the user as described above.

In this way, the user does not need to change the logic of the old counter since the user only needs to set the initial value of the counter regardless of the application of the counter.

However, in the conventional counter as described above, since the number of bits is proportional to the number of input terminals of the third, fourth, and fifth logic units, when the number of bits increases, the number of bits increases accordingly, increasing the area and consequently increasing the size of the device. There was a problem.

The present invention has been made to solve the above problems, and an object thereof is to provide a counter suitable for minimizing an area by adding only a simple logic gate regardless of an increase in the number of bits.

1 is an internal configuration of a counter according to the prior art.

2 is a schematic configuration diagram of a counter according to the present invention;

Figure 3 is a partial detailed view according to the counter of the present invention.

4 is a block diagram of a counter according to an embodiment of the present invention.

5 is a waveform diagram according to one embodiment of FIG. 4;

* Explanation of symbols for main parts of the drawings

31: set input 33: flip-flop

31a: first logic gate 31b: second logic gate

31c: third logic gate 31d: fourth logic gate

31e: 1st inverter 31f, 31g: 1st, 2nd transfer gate

31h, 31i: third and fourth transfer gates

The counter of the present invention for achieving the above object is a first logic gate for logic operation by inputting the clock signal and the feedback signal, the second logic gate for logic operation by inputting the feedback signal and the reset signal, the reset signal and the first A third logic gate for inputting and logically operating the output of the logic gate, a fourth logic gate for inputting and logically operating the outputs of the second and third logic gates, an inverter for inverting the output of the third logic gate, and a user. The first and second transfer gates outputting a set signal by selectively outputting the output value of the fourth logic gate and a fixed signal that always maintains a high level according to the input value set by the user, and the input value set by the user. A set-input stage consisting of third and fourth transfer gates for selectively outputting an output value and a fixed signal to output a reset signal; And a flip-flop which is operated by a set signal or a reset signal and a clock signal output from the set-input stage and outputs a feedback signal to the set-input stage.

Hereinafter, the counter of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a counter according to the present invention.

As shown in Fig. 2, the counter of the present invention includes a set-input terminal 31 for setting a value indicating a counting time of the counter, and a flip-flop 33 connected to a set or reset terminal of the set-input terminal. It is composed.

Herein, the output value of the flip-flop 33 is fed back to the set-input terminal 31.

The set-input terminal 31 is always supplied with a fixed signal UP and a reset or set signal fixed at a "high" level.

The flip-flop 33 is operated by inputting one of a reset or set signal selectively output from the set-input terminal 31.

The set-input stage according to the counter of the present invention configured as described above will be described in more detail.

3 is a detailed block diagram of the set-input stage according to the counter of the present invention.

As shown in Fig. 3, the set-input stage 31 of the present invention is composed of four transfer gates, two OR gates, one NAND and an AND gate, and one inverter.

That is, a clock signal, a signal fed back from the flip-flop, a first logic gate 31a for inputting a logic operation by inputting a recess or set signal, a signal fed back from the flip-flop 33, and the re A second logic gate 31b for inputting a set or set signal and performing logical operation, a third logic gate 31c for inputting a logic operation by inputting a reset or set signal and an output of the first logic gate 31a, A fourth logic gate 31d for inputting and logically operating the output of the second logic gate 31b and the output of the third logic gate 31c, and a first for inverting the output of the third logic gate 31c. Four transmission gates 31f for selectively outputting the output of the fourth logic gate 31d and the output of the first inverter 31e according to the inverter 31e and the input value set by the user and the fixed signal UP. , 31g, 31h, 31i) .

Here, the first transfer gate 31f into which the input value set by the user is input to the non-inverting terminal and the inverted value of the input value set by the user is inputted, and the input value set by the user are non-inverting terminals. Similarly to the second transfer gate 31g and the second and second transfer gates 31f and 31g, which are input to the inverting terminal and the inverted value of the input value set by the user is input to the inverting terminal. One input value is input to the non-inverting terminal, and the inverted value of the input value set by the user is composed of third and fourth transfer gates 31h and 31i.

The inverting of the input value set by the user is performed by the second inverter 31j as shown in FIG.

Referring to the operation of the counter according to the present invention configured as described above are as follows.

First, according to FIG. 2, the set-input terminal 31 driving the flip-flop 33 sets the start point of the counter by the set input values, that is, S ₁ , S ₂ , and S ₃ .

The fixed signal of the set-input stage 31 always maintains the "high" level, and the flip-flop 33 feeds back the signal of the "high" level to the set-input stage 31 only when its output is a high signal.

This feedback signal serves as a load signal.

With this general description in mind, this will be described in more detail.

As shown in Fig. 3, the clock and feedback signals output a high signal equal to half the period of the clock signal through the first logic gate 31a.

The signal output from the first logic gate 31a is input to the third logic gate 31c together with the reset signal or the set signal to make an actual load signal.

Subsequently, the actual load signal, that is, the output signal of the third logic gate 31c is inverted by the first inverter 31e and used as a set signal.

In addition, the feedback signal and the reset or set signal input from the flip-flop 33 are output as a high signal for one cycle of the clock signal through the second logic gate 31b.

Therefore, the signal output from the second logic gate 31b and the signal output from the third logic gate 31c are input to the fourth logic gate 31d.

At this time, the fourth logic gate 31d outputs a low signal corresponding to half a period of the clock signal.

The signal passing through the fourth logic gate 31d is used as a reset signal.

Here, among the input values set by the user, S ₁ determines whether to use the set signal or the reset signal.

Ten thousand and one, S ₁ In this case, a high signal, in the case where the output value of the first inverter (31e) transmitted to the set value of the flip-flop 33 and the S ₁ is Righteous foil, the fourth flip-flop output of the logic gate (31d) (33 It is passed as a reset value of).

Here, as S ₁ is a high signal, when the output signal of the first interleaver 31e is transmitted to the set of the flip-flop 33, the fixed signal is always transmitted to the reset.

Thus, the reset does not actually work, only the set.

In this way, the user can set S ₂ and S ₃ .

Here, the process of transferring the output signal of the first inverter 31e and the output signal of the fourth logic gate 31d to the set or reset of the flip-flop 33 is performed by four transfer gates 31f, 31g, 31h, and 31i. To be explained.

As described above, when S ₁ is a high signal, the fourth transfer gate 31d is turned on and the output value of the first inverter 31e is transferred to the set through the fourth transfer gate 31d.

When S ₁ is a low signal, the first transfer gate 31a is turned on and the output value of the fourth logic gate 31d is transferred to the reset through the first transfer gate 31a.

In this way, you can set S ₂ and S ₃ to your desired values.

On the other hand, Figure 4 is a block diagram according to an embodiment using a counter of the present invention.

As shown in Fig. 4, according to the embodiment of the present invention, the number of set-input terminals is connected in accordance with the number of bits.

In the embodiment of the present invention, a 3-bit synchronous counter is taken as an example, and a clock signal, a signal fed back from the flip-flop, a first logic gate 31a for inputting a logical operation by a recess or set signal, and A second logic gate 31b for inputting a logic feedback signal from the flip-flop and the reset or set signal, and a logic operation for inputting an output and a reset or set signal of the first logic gate 31a A fourth logic gate 31d for inputting and logically operating a third logic gate 31c, an output of the second logic gate 31b, and an output of the third logic gate 31c, and the third logic gate ( The output of the fourth logic gate 31e and the output of the first inverter 31e according to an input value set by the user and the fixed signal UP. First set-in to selectively output Parallel to the stage 41, the first flip-flop 41a operated by the set signal or reset signal and the clock signal output from the first set-input stage 41, and the first set-input stage 41; A second set-input stage 43 for selectively outputting the output of the first inverter 31e and the output of the fourth logic gate 31d, and a set signal outputted from the second set-input stage 43; Or a second flip-flop 43a operated by a reset signal and a clock signal output from the first flip-flop 41a and the second set-input terminal in parallel to output the first inverter 31e. And a third set-input terminal 45 for selectively outputting the output of the fourth logic gate 31d, and a set signal or reset signal and a second flip-flop 43a thrust from the third set-input terminal 45. And a third flip-flop 45a operated by the clock signal output from the.

In this case, input values S ₁ , S ₂ , and S ₃ are set to the first, second, and third set-input terminals 41, 43, and 45 by the user.

And a fifth logic gate 47 for logically operating a signal output from the non-inverting output terminal of each of the first, second, and third flip-flops 41a, 43a, and 45a.

Further, an output Out 1 of the most significant bit of the 3-bit output is obtained from the first flip-flop 41a, and Out 2 and Out 3 are similarly obtained from the second and third flip-flops 41a, 45a.

FIG. 5 is a waveform diagram illustrating a three-bit sync counter of FIG. 4.

As shown in Fig. 5, the reset signal changes from high to low level, and the fixed signal is always a high signal.

If the value of the input value S ₁ is set to "1", the value of S ₂ is set to "0", and the value of S ₃ is set to "0", the values of the output terminals Out 1, Out 2 and Out 3 are obtained. Lose.

In other words, if the values of S ₁ , S ₂ , and S ₃ are set to "100", the output value is changed as shown in FIG.

Changed here means counting.

As described above, the counter of the present invention has the following effects.

While the logic gate is increased according to the conventional number of bits, the present invention only needs to add four transfer gates per bit by using the set-input stage, thereby minimizing the size.

That is, since only four transfer gates are added per bit without increasing the number of input terminals or increasing the number of logic gates according to the increase in the number of bits, the area can be minimized.

Claims (4)

An AND gate for inputting a logic operation by inputting a clock signal and a feedback signal, a first OR gate for inputting a logic operation by inputting a feedback signal and a reset signal, a second OR gate for inputting a logic operation of an output of a reset signal and an AND gate, A NAND gate that inputs and logically operates an output of the first or second OR gate, an inverter that inverts the output of the second OR gate, and an output value of the NAND gate according to an input value set by a user at all times A first and second transfer gates for selectively outputting a fixed signal maintaining a level and outputting a set signal, and selectively outputting the output value and the fixed signal of the inverter according to an input value set by a user and outputting a reset signal. A set-input stage consisting of third and fourth transfer gates, And a flip-flop operated by a reset signal and a clock signal output from the set-input stage and outputting a feedback signal to the set-input stage. The method of claim 1, wherein the first transfer gate is applied to the non-inverting terminal by the input value set by the user, the input value is applied to the non-inverting terminal through the inverter and the second transfer gate is the non-inverting terminal. The counter, characterized in that the input value is passed through the inverter is applied to the inverting terminal. The method of claim 1, wherein the third transfer gate is applied to the non-inverting terminal by the input value set by the user, the input value is applied to the non-inverting terminal through the inverter, and the fourth transfer gate is the non-inverting terminal. And the input value is applied to the inverting terminal through the inverter. The counter of claim 1, wherein the flip-flop is an R-S flip-flop.

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