KR100230186B1 - The host digital terminal using dual cell bus - Google Patents

Abstract

The present invention relates to a host digital terminal using two cell buses. In particular, a qubit chip mounted on an ATRU board is staggered so as to be connected to a first cell bus and a second cell bus, respectively, and two ONUs are connected to an OTRU board. Since it is in charge of processing, it is equipped with four qubit chips, which are twice as large as two cell buses, connected to each cell bus, and two qubit chips are mounted on the DS1E part to be connected to two cell buses, respectively. According to the present invention, when the HDT system is designed with two cell buses, a bandwidth of about 1.8G byte / sec can be secured to sufficiently handle 1.5G byte / sec required by the FLC-C standard. Three qubit chips are available, allowing the HDT to be configured to allow cell transmission from any ATRU to any ONU, while reducing the number of qubits to reduce production costs and costs. Not only can be reduced, there is an effect that the processing speed becomes fast in the data.

Description

Host Digital Terminal Using Two Cell Buses

The present invention relates to an automatic teller machine (ATM) optical transmission device in a demand-dense optical subscriber transmission system. In particular, after receiving image data input through an ATM exchanger and converting the signal for predetermined image processing, the conversion is performed. The number of cell buses in the HDT, the heart of the overall FLC (Fiber Loop Carrier) -C system connecting the ONU (Optical Network Unit), is used to distribute the video data transmission signals back to the home. It relates to a host digital terminal using two cell buses, which are limited to two and can connect devices.

FLC-C system is a device that supports star-type Fiber To The Curb (FTTC) network structure. It is Digital Signal Level 1 (DS) O (64kbps) voice and data service, DS1E (Digital Service 1 Europe) (2.048). Mbps), DS1 (1.544Mbps), ISDN (Integrated Serve Digital Network), and broadband video services are used for synchronous optical transmission in STM (Synchronous Transfer Mode) -4 class (622Mbps). The FLC-C system consists of HDT and ONU, and the HDT is installed on the demand-intensive subscriber side in the country where the main body of the control and management side is located. The HDT unit integrates the Public Switched Telephone Network (PSTN) service and the Video On Demand (VOD) service provided by the ATM switching network to perform synchronous optical transmission to the ONU, and vice versa. By demultiplexing signal and VOD signal, each subscriber's home provides high speed asymmetric transmission channel with 1.5 ~ 6Mbps (or 2 ~ 8Mbps for E1) downlink and 16 ~ 24kbps uplink and single twisted pair (TP). It performs the function of transmitting the data of such transmission rate through ADSL (Asymmetrical Digital Subscription Line) method which can transmit the data of such transmission rate up to 5.4km without a repeater through the strong particle line pair.

1 is a block diagram showing the structure of a conventional FLC-C system, comprising: a PSTN unit 1 used by an unspecified number of users through a public line; Divides the information sent from the sending terminal to the receiving terminal by 48 bytes, adds 5 bytes of headers to the destination label header, and has a fixed length of 53 bytes. An ATM switch unit (2) capable of freely allocating a band required for a communication channel by sending information in units of " " and changing the number of transmission information freely by changing the number of transmission cells per unit time during communication; Eight STM-s which are DS1E which is a predetermined service signal of 2,048 megabits / sec output from the PSTN unit 1 and a synchronous transmission mode level 1 signal which is output from the ATM switch unit 2. An HDT unit 3 for integrating and outputting the VOD service provided from 1 to a rear end; It is composed of a plurality of ONU units 4 which are installed on the side of demand dense subscribers and demultiplex the PSTN signals and VOD signals among the optical signals received from the HDT unit 3 and transmit them to the homes of each subscriber in an ADSL manner. .

That is, in the above-described configuration, the HDT unit is transmitted through the PSTN unit 1 and the ATM switch unit 2 when information of a unit of a 53-byte fixed length cell including a destination label header and a 5-byte header is transmitted. (3) integrates and outputs the VOD service provided from eight STM-1s and DS1E, which is a service signal of 2.048M bit / sec, and the ONU unit 4 outputs the optical signal output from the HDT unit 3. The PSTN signal and the VOD signal are demultiplexed again, and then transmitted to the home of each subscriber by the ADSL method.

However, in designing an HDT that satisfies the FLC-C specification using Transwitch's Cubit, a typical commercial chip supporting the existing cell bus, the ATM cell bus in the HDT can be selected using only one cell bus. In the design, the HDT is connected to the ATM switch with eight STM-1 links, and the PSTN switch is also connected to 108 2 Mbps E1 links, concentrating the ATM cells within the HDT, so that approximately 1.5 Gbits (Bit) / Sec (Sec) bandwidth is required, but when using a single cell bus as in the past, due to the characteristics of a typical commercial chip qubit chip, only a maximum of three qubits distributed to 16 STM-4 class lines The connection allows only about 900M bits / sec of performance to be handled, thus not meeting the performance requirements of the FLC-C specification.

The present invention is to solve the above-mentioned conventional problems, apart from the way to implement the HDT system with only one cell bus, by using each of the two cell buses to connect each board in the HDT evenly to the two cell bus, ATM cells over the STM-1 link from the ATM switch can be sent to any ONU and vice versa by configuring two ATM cell buses connecting each board in the HDT, Two bandwidths of approximately 1G bytes / sec are configured per ATM cell bus, resulting in a total bandwidth of 2G bytes / sec. Up to three qubit chips can be connected per ATM cell bus, resulting in up to 64 qubit chips. Therefore, the purpose is to design an HDT using two cell buses that can solve the existing problems in the HDT.

In order to achieve the above object, the host digital terminal using the two cell buses of the present invention alternates the qubit chips mounted on the ATRU boards to be connected to the first cell bus and the second cell bus, respectively. As it handles two ONUs, it is equipped with four qubit chips, which are twice as large as two cell buses, connected to each cell bus, and two qubit chips are mounted on the DS1E to connect two cell buses respectively. It is done.

1 is a block diagram showing the configuration of a conventional FLC-C system;

2 is a block diagram showing the configuration of a host digital terminal using two cell buses according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: PSTN unit 2: ATM switch unit

3: HDT unit 4: ONU unit

5: 1st ATRU part 6: 2nd ATRU part

7: MCU unit 8: First OTRU unit

8a: 1st COTU part 8b: 2nd COTU part

9: 2nd OTRU part 9a: 3rd COTU part

9b: 4th COTU part 10: 1st DS1E part

11: second DS1E part

Hereinafter, the above-described contents will be described in detail through an embodiment according to the present invention.

As shown in FIG. 2, after receiving four STM-1 signals per unit from an ATM switching network and performing overhead processing, the present invention extracts an ATM cell and sends it to a corresponding OTRU unit and its reverse function. Performing a first ATRU section 5; A second ATRU unit 6 for performing overhead processing by receiving four STM-1 signals per unit from an ATM switching network, extracting an ATM cell, and sending the ATM cell to a corresponding OTRU unit; Main control unit (MCU) that has control functions including general management functions of system such as alarm, provision, performance test, transfer, loopback, etc., and communicates with ONU and FMS. Part 7; Controlled by two central office terminal units (COTUs) 8a and 8b, which are central terminals, receive ATM cells from the DS1E units 10 and 11 and the ATRU units 5 and 6 to receive 4 × 9 A first OTRU unit 8 which performs a function of mapping into an STM-4 class frame having a flow path load of rows (bytes) x 270 columns (bytes) and transmitting the same to the ONU device; Under the control of two COTUs (9a, 9b), which are central terminals, receive ATM cells from DS1E units (10, 11) and ATRU units (5, 6), map them into STM-4 class frames, and turn them on. A second OTRU unit 9 for transmitting to and from the reverse function; A first DS1E unit 10 for receiving a 2.048 Mbps DS1E signal, mapping the same into a payload of an ATM cell, and sending the DS1E signal to the OTRU units 8 and 9 and the reverse function thereof; The present embodiment includes a second DS1E unit 11 which receives a 2,048 Mbps DS1E signal, maps it into a payload of an ATM cell, sends the OTRU unit 8 and 9, and performs a reverse function thereof. .

Hereinafter, an operation process of a host digital terminal using two cell buses configured as described above will be described.

As shown in FIG. 2, the qubit chips mounted on the ATRU board are staggered from each other so as to be connected to the first cell bus 1 and the second cell bus 2, respectively. On the other hand, the OTRU board is equipped with four qubit chips, which are twice the two cell buses, so as to be connected to each cell bus as shown in FIG. The reason for this is that the OTRU board handles two ONUs so that one ONU circuit can be connected to two cell buses so that ATM cells from any ATRU can be transferred to any ONU. DS1E is a structure that is assigned to a specific ONU in the FLC-C standard and transmitted. At this time, up to one or two ports are mounted on one DS1E board, and six ports are multiplexed on one qubit chip. In the DS1E board, two qubit chips are mounted.In this case, the OTRU dedicated to the transmission to ONU is connected to both cell buses. It becomes possible.

On the other hand, in the qubit, a total of 20 qubits per ATRU and 16 of the two OTRUs using 8 ONUs in total, plus 20 pairs of DS1E and 2 dedicated boards per board. By combining the 18 multiplied by the one in the MCU, 19 qubits are distributed over two cell buses, and 30 cell qubits are connected to one cell bus.

As described above, the host digital terminal using the two cell buses of the present invention can secure a bandwidth of about 1.8G byte / sec by designing an HDT system using two cell buses, which is required by the FLC-C standard. It can handle 1.5G byte / sec, and up to 64 qubit chips can be used in 3 or 2 qubit chips through one cell bus, so that HDT can be transmitted from any ATRU to any ONU. The present invention can be configured such that the number of qubits can be reduced to reduce the cost of production cost and cost, and the data processing speed can be increased.

Claims (3)

The qubit chips mounted on the ATRU board are staggered so that they are connected to the first cell bus and the second cell bus, respectively, and the two OTRU boards handle and handle the two ONUs, so four qubit chips, which are twice the two cell buses, are mounted. Connecting to each cell bus and mounting two qubit chips on the DS1E part to connect the two cell buses to each other. The OTRU having four qubit chips and connected to two cell buses, wherein an ONU circuitry is connected to two cell buses so that ATM cells from any ATRU can be randomly connected. A host digital terminal using two cell buses, characterized in that it can be transmitted to the ONU. The method of claim 1, wherein the DS1E unit is equipped with a maximum of one two ports in one DS1E board and six ports are multiplexed on one qubit chip, so two qubit chips are mounted on one DS1E board. Digital terminal using two cell buses.

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