KR100228376B1 - Pstn access apparatus using serial communication way in advanced information and communication processing system - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Telephone network matching device for multi-telephone subscriber service of high speed mass communication processing system.

2. The technical problem to be solved by the invention

When the telephone network subscriber wants to retrieve the information of the information providers connected to the high speed network at the same time, the service control and the high speed network adapter provide smooth service.

3. Summary of Solution to Invention

The telephone network matching device is in charge of carrier transmission through the serial data communication line and the text data line matching means of the multiple subscribers connected through the sub highways, and is formed of a multi-processor structure for allocating multiple channels per processor. It is connected to the high speed data processing means for transmitting data and the high speed data processing means through the common serial bus to perform the bus requestor / coordinator function for managing the resources through the system bus. Equipped with a high speed network coupling means to perform.

4. Important uses of the invention

Used for telephone network matching device of communication processing system.

Description

Telephone network matching device using serial communication method for multi-telephone connection service in high speed large capacity communication processing system

The present invention relates to a Telephone Network Access Subsystem (TNAS) using a serial communication method for a multi-telephone access service of a high speed high-capacity communication processing system (AICPS).

In the conventional communication processing system, a subscriber of a public switched telephone network (PSTN) accesses an information service access point (ISAP) having a 96-channel processing capacity at a speed of 14400bps or less and accesses an information provider (IP) connected to a packet network. Provides a service for retrieving information from an information provider.

The high-speed, high-capacity communication processing system accommodates various public networks such as telephone network, packet switched data network (PSDN), integrated service digital network, and main services for high-speed and multi-subscriber processing unlike existing communication processing systems. There is a need for a multiprocessor architecture of the processor.

Accordingly, the present invention has been made to meet the requirements as described above, the text data service processing board (TSPA) for processing multiple subscribers of 96 channels in the telephone network matching device (TNAS) It is an object of the present invention to provide a telephone network matching device that can provide a smooth service through a high speed network adapter (HSNA) when a telephone network subscriber wants to retrieve information of an information provider connected to a high speed network at the same time.

1 is a structural diagram of a high-speed mass communication processing system to which the present invention is applied.

2 is a configuration diagram of an embodiment of a telephone network matching device according to the present invention.

Figure 3 is a detailed block diagram of one embodiment of a text data service processing board according to the present invention.

4 is a block diagram of an embodiment of a character data service processing board according to the present invention.

5 is an internal common bus diagram of a text data service processing board according to the present invention;

6 is a detailed block diagram of an embodiment of a high-speed data processing board according to the present invention.

* Explanation of symbols for main parts of the drawings

20: telephone network matching board (TNIF)

21: character data line registration board (TDLA)

22: High Speed Data Processing Board (HDPA)

23: Character Data Service Processing Board (TSPA)

24: High Speed Network Adapter (HSNA)

In order to achieve the above object, the present invention provides a telephone network matching device using a serial communication method for a multi-telephone connection service in a high-speed mass communication processing system, the digital PCM (Pulse CodeModulation) trunk of the communication processing system and Telephone network matching means for connecting and matching information input and output to the telephone network; A plurality of text data line matching means for receiving subscriber information through an independent channel, performing carrier transmission through a serial communication line, and connected to the telephone network matching means through an internal sub highway; The carrier, which is matched by the plurality of text data line matching means, is input through the serial communication line and transmitted through a common serial bus, and is formed in a multiprocessor structure for allocating a plurality of channels per processor. High speed data processing means for converting the converted data into data in a transmission format and transmitting the converted data through the common serial bus; Text data service processing means for receiving data transmitted from the high speed data processing means through the common serial bus, performing a bus requestor / coordinator function to use system resources, and performing an interrupt processing function; And a high speed network coupling means connected to the text data service processing means and matching the transferred data to a high speed switching network.

The present invention enables communication in a telephone network interface (TNIF: Telephone Network Interface) (TNIF) of the existing ICPS, and the subscriber modem matching portion has a structure that accommodates 8 channels of V.34 (28800 pbs) standard per board. Also, the text data service processing board (TSPA) processor structure for TNAS service processing, the controller for inter processor communication (IPC), the common bus structure, bus license arbitration and interrupt processing period It provides a configuration for this.

The present invention defines the circuit and operation for the MC68030 (50MHz), the main processor, MC68360 (25MHz), the processor for multiplexing and controlling the subscriber data, and defines the clock, bus license arbitration, reset, etc. required for communication, and describes the implementation signal. .

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is an overall structural diagram of an open high speed / high capacity communication processing system to which the present invention is applied. The high speed / high capacity communication processing system includes a telephone network 11, a data network 12 using an X.25 standard protocol, and a comprehensive information communication network ( 13) Accepts the connection of the ATM network 14 and the like.

The High Speed Switching Fabric (HSSF) subsystem 15 connects various types of network matching modules, service support modules and communication processing modules at high speed to each other, and is responsible for transporting service traffic. Provides interlocking function.

A telephone network matching device (TNAS) is a telephone network matching device for providing various communication services to a personal computer (PC) user connected to a public telephone network.

TNAS is a telephone network interface board (TNIF) module 111 for interfacing with a charge network, a high-speed network adapter (HSNA) module 114 for interfacing with HSSF, and a service processing for controlling and processing a service. Service Processing (SP) module.

TNIF module consists of trunk interface module and subscriber modem interface module supporting V.32bis, V.34, V.42 / V.42bis.

The service processing module is composed of a high data processing board assembly (HDPA) 112 for processing input and output of a subscriber and a text data service processing board (TSPA) 113 for service processing and control.

Unlike the existing communication processing system for interworking with simple telephone network and data network, text data service processing board (TSPA) enables users of telephone network to search database information connected to other networks at the speed of 28800bps at the same time. It delivers the information received from the designated user. TSPA delivers subscriber network matching information, billing information, configuration change information, and failure information to the Operation Administration Maintenance (OAM).

TSPA manages resources required for communication with transmission / reception tasks that operate in a real time operation system (RTOS) for smooth service support of multiple subscribers.

2 is a block diagram of an embodiment of a telephone network matching device (TNAS) according to the present invention.

Referring to FIG. 2, the telephone network matching board 20 may access a digital PCM trunk up to 3 * E1, and subscriber information is a text data line interface board (TDLA) which is a collective modem pool through an independent channel. Assembly 21). At this time, the internal connection is connected through the sub-highway 200 of 2.048bps.

The TDLA 21 and the Highly Data Processing Board Assembly (HDPA) 22 are responsible for carrier transmission up to 57.6 kbps through the serial communication lines 210 and the CD-1864 of RS-232C level. It adopts a multi-processor architecture that handles 8 channels per MC68360 processor and accommodates a total of 32 channels.

The HDPA 22 and TSPA 23 transmit 2Mbps serially transmitted data for each processor via the common serial bus 220 which is also 2Mbps. This is bandwidth allocation using the point that data transfer does not occur simultaneously. The TSPA 23 is interfaced through the HSNA 24 and the VME bus 230 that are responsible for 100Mbps taxi (TAXI) high-speed transmission, and serves as a system bus.

It also serves as a bus requester / arbiter to manage system resources.

In addition, the TSPA 23 operates as a master of the data transmission bus, and can read / write slave data of 32/16/8 bits, and the HSNA 24 as an interrupt handler is provided to the bus 230. It also handles interrupts of level 1-7 required by the system and also handles local interrupts of level 6 and 7 required by MFP (Multi-Function Peripheral) 1 and MFP2.

3 is an embodiment configuration diagram of the TSPA internal communication module according to the present invention, and uses the MC68360 (31), a communication processor dedicated to inter-processor communication (IPC), for communication with a plurality of HDPAs 30, as a dedicated communication processor, Data is transmitted in an interrupt manner through a 1 Mbyte of common memory connected to the local bus (310,320). At this time, the IPC communication processor is input and output to the transmit / receive memory 32 through the three HDPA 30 and each of the 2Mbps common serial bus (300).

TSPA has channels (C, D) for data transmission with other redundant TSPA, where C channel is a bidirectional 8-bit parallel channel, D channel is a 32-bit parallel channel, and active TSPA is a D-channel 330 The read / write DRAM 34 of the standby TSPA can be read through.

TSPA has a fault monitor input port and a hardware control output port. TSPA monitors HDPA and HSNA power alarms through the alarm port.

4 is an exemplary clock generation circuit diagram used in a TSPA according to the present invention. The clocks generated by two oscillators of 50 MHz (41) and 2.4576 MHz (42) are divided 400 to provide various necessary clocks. First, 500 MHz provides the frequency required for the main CPU and control logic and DPRAM-mediated logic (410), while the divided 25 MHz is used as the response (ACK) frequency of the local data strobe (411), again the divided 3 MHz is a serial monitor. It is utilized to provide the frequency required for communication (412).

Second, 2.4576 MHz is used as the timer frequency of the multifunction peripheral (420), and the divided 614.4 KHz is used as the main processor and bus and D-channel time-out and DRAM refresh counter frequencies (421). The divided 19.2 KHz is used as the frequency used for monitoring system shutdown (422). On the other hand, 2.34Hz is a timer prepared for use when needed for screen control (423).

5 illustrates a common structure in which a TSPA according to the present invention can communicate with a high speed switch adapter through an internal common bus, can also be used as a main system bus, and can access a memory.

In this circuit, when the main processor reads the ROM area, the DSACKO * signal is automatically applied according to a predetermined cycle. When the CPU reads / writes DPRAM, DSACKO * and DSACK1 * signals are sent to the CPU under the control of the DPRAM controller.

In this case, to protect the system, if it is not the value of the control register (128/256/512/1024 system clock), it is determined as an operation error and a BERR * signal is applied to the CPU to perform a bus exception handling error.

The TSPA is interfaced with the HSNA via the MPS bus 51 and can communicate with other redundant TSPAs via the D-channel (52). The case where the TSPA reads / writes the DRAM, the MPS bus, and the D-channel and the path where the redundant TSPA reads / writes the DRAM 53 through the D-channel are commonly used (54).

The bus coordinator arbitrates the use of this common path. The role of the coordinator is to decode the signal relating to the bus usage request from the main CPU 55, receive the signal from the D-channel decoder, and license the main CPU, MPS bus, data transfer master, or D-channel, or DRAM controller. It requires operation as an MPS bus controller or a D-channel controller. Terminate the license when a signal indicates the end of use. In this manner, the main processor operates the communication task in a structure capable of processing separate from the user data.

6 is a configuration diagram of an embodiment of a high speed data processing board (HDPA) according to the present invention.

HDPA is mounted in TDBB, the subscriber processing unit of TNAS, and uses MC68360 25MHz Quad Integrated Communications Control (QUICC) as the main processor.

One master processor is used for communication with TSPA and four slave processors are used for communication with subscriber modem.The main processor of HDPA is connected with slave at 2Mbps through internal serial communication controller (SCC). It communicates with the TSPA through the serial communication controller of the main processor and transmits and receives data with the TSPA serial communication controller in a 2Mbps serial communication method.

HDPA's memory has 256Kbyte EPROM and 1Mbyte SRAM in each main and slave processor and transfers I / O data of TDLA through I / O port.

Each slave processor in HDPA handles the modem interface corresponding to the subscriber of the 8-channel TDLA board, and the modem interface that provides the subscriber communication uses the CD1864 chip for 8 channels.

Thus, one HDPA board was designed to process data from 32 subscriber-compatible modems. The serial ports for communication with the monitor terminal and the host computer are located on the main and slave processors, respectively, and one of the four slave processors is shunted for selection.

The software function is for the master processor to connect the communication between the slave and TSPA, and the slave delivers the data received from the subscriber through the modem to the TSPA under the control of the master or the data received from the TSPA to the subscriber. It performs PAD processing and subscriber channel monitoring.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

As described above, the present invention provides the data of the PC communication user in the telephone network matching device of the high speed / high capacity communication processing system as well as smoothly supports the interface even when a large number of subscribers are accommodated to access a heterogeneous network database. It provides the configuration and communication configuration module of resources such as tasks executed in TSPA of matching device, channel identification, transmit / receive buffer, bus usage arbitration, etc., and can accept serial data carrier of 28800bps with up to 96 channels. There is an effect that can be applied to data communication variably.

Claims (3)

A telephone network matching device using a serial communication method for a multi-telephone connection service in a high-speed mass communication processing system, the information being connected to a digital PCM (pulse code modulation) trunk of the communication processing system and input / output information to the telephone network. Telephone network matching means for matching; A plurality of text data line matching means for receiving subscriber information through an independent channel, performing carrier transmission through a serial communication line, and connected to the telephone network matching means through an internal sub-highware; The carrier is matched by the plurality of text data line matching means, is received through the serial communication line, is transmitted through a common serial bus, and is formed in a multi-processor structure for allocating a plurality of channels per processor. High speed data processing means for converting the converted data into data in a transmission format and transmitting the converted data through the common serial bus; Text data service processing means for receiving data transmitted from the high speed data processing means through the common serial bus, performing a bus requestor / coordinator function to use system resources, and performing an interrupt processing function; And a high speed network combining means connected to the text data service processing means and matching the transferred data to a high speed switching network. 2. The apparatus of claim 1, wherein the high-speed data processing means is responsible for carrier transmission up to 57.6 kbps substantially through the serial communication line, and through CD-1864 (commercial product) of RS-232C (commercial product) level. A telephone network matching device using a serial communication method for a multi-telephone connection service in a high-speed mass communication processing system characterized by having a multi-processor structure that is responsible for eight channels per processor. 3. The apparatus of claim 2, wherein the text data service processing means comprises: serial communication control means connected to the high speed data processing means through a common serial bus to control interprocessor communication; Common memory means connected to the serial communication control means via a local bus to store data; And main processing means connected to the common memory means and a local bus, the main processing means having a channel and a data transmission channel for connecting with other redundant character data service processing means. Telephone network matching device using serial communication method.