KR100220638B1 - Adaptation apparatus between atm switch and ds1e transmission apparatus - Google Patents

Abstract

The present invention relates to a matching device for matching an ATM (Asynchronous Tranfer Mode) exchange, which is an asynchronous transmission mode. Particularly, an ATM cell applied from an ATM exchanger is loaded onto a DS1E frame and transmitted on a DS1E frame. A matching device between an ATM switch and a DS1E transmitter for extracting a cell to be output to an ATM switch side.

Conventionally, in order to transfer ATM cells output from an ATM switch to another switching station, a predetermined transmission device must be used. However, conventionally, DS1E (European) transmitters are used for transmitting signals in the switching network. Therefore, matching devices for matching ATM switches have not been developed. Therefore, ATM switches cannot be connected to DS1E transmitters. There was a problem.

The present invention is a device having a matching function between a switch and a transmission line, and has a multicasting function capable of simultaneously sending a single cell to multiple transmission lines, and effectively performs protocol conversion between an ATM switch and a conventional DS1E transmission device. DS1E transmission devices can be accommodated at ATM switches, and cell processing can be effectively performed by minimizing processor intervention in the data transmission path.

Description

Matching device between ATM switch and DS1E transmitter

1 is a block diagram showing the overall configuration of a matching device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the internal structure of the multiplexed demultiplexer shown in FIG.

3 is a diagram showing the routing table shown in FIG.

* Explanation of symbols for main parts of the drawings

10: physical layer processing unit 20: multiplexed demultiplexer

21: routing table matching unit 22: cell conversion / demultiplexing circuit

23: buffer 24: cell conversion / multiplexing circuit

25 counter 30 transmit buffer

40: receiving buffer 50: routing table

60: bus matching unit 70: microprocessor

80: Roman 90: Ram

The present invention relates to a matching device for matching an ATM (Asynchronous Tranfer Mode) exchange, which is an asynchronous transmission mode. In particular, an ATM cell applied from an ATM exchanger is carried in a DS1E frame and transmitted in a DS1E frame. A matching device between an ATM switch and a DS1E transmitter for extracting a cell to be output to an ATM switch side.

ATM switching system is a physical layer level data exchange method among 7 OSI (Open System Interconnection) layers used in Broadband Integrated Service Digital Network, and divides all signals into fixed cells and assigns destinations. As a technology for transmitting data in optical paths, research is being actively conducted to use information as an exchange means constituting an information highway because information can be exchanged at high speed.

On the other hand, in order to transfer the ATM cell output from the ATM switch to another switching station, a predetermined transmission device must be used. However, conventionally, DS1E (European) transmitters are used for transmitting signals in the switching network. No matching apparatus has been developed to match ATM switches. Therefore, ATM switches cannot be connected to DS1E transmitters. There was a problem.

The present invention has been devised to solve the above-mentioned problems, and the multicasting function and multiple transmission lines which convert one cell to multiple transmission lines during transmission at the same time converting an internal cell from the switch system to an ATM cell. It aims to obtain a matching device between an ATM switch and a DS1E transmitter by multiplexing ATM cells, converting them into a single cell stream, and sending them to the switch, and performing protocol conversion between ATM and the existing DS1E transmission system effectively. .

To achieve the above object, a transmission buffer for storing and outputting the applied internal cells in order; A receiving buffer for storing and outputting the inner cells in order; A bus matching unit which transfers an internal cell transmitted from an ATM switch via a bus to the transmission buffer, and delivers a cell applied from the reception buffer to the ATM switch via the bus; A plurality of physical layer processing units for extracting and outputting an ATM cell carried in a DS1E frame through a transmission line from a DS1E transmitter and outputting an ATM cell transmitted to a DS1E transmitter through the transmission line in a DS1E frame; A routing table for recording and storing the authorized routing information corresponding to a virtual path identifier (VPI); The routing information corresponding to the VPI in the header of the inner cell is converted while converting the inner cell of the first predetermined bit transmitted from the transmission buffer into an ATM cell of the second predetermined bit for processing by the physical layer processor. Reads from a table, duplicates an ATM cell based on routing information, outputs it to the physical layer processing unit, converts the ATM cell of a second predetermined bit applied from the physical layer processing unit into an internal cell of a first predetermined bit, and receives the received data. A multiplexing demultiplexer for transmitting to a buffer; A microprocessor configured to read routing information included in an ATM cell applied from the physical layer processor and provide routing information to the routing table; A ROM for inputting a program required for the operation of the microprocessor; And a RAM for storing data generated by the operation of the microprocessor.

The multiplexer / demultiplexer may include a buffer configured to sequentially store and output internal cells transmitted from the transmission buffer; A routing table matching unit configured to read routing information corresponding to a VPI value in a header of an inner cell stored in the buffer from the routing table and output the routing information; After converting the internal cell of the first predetermined bit from the buffer into an ATM cell of the second predetermined bit, the cell is copied based on the routing information transmitted from the routing table matching unit to the physical layer processing unit on the corresponding transmission line side. A cell conversion / demultiplexing circuit for transmitting; A cell conversion / multiplexing circuit for converting an ATM cell of a second predetermined bit extracted from the physical layer processing unit into an internal cell of a first predetermined bit to make a cell stream, and pulling it into the reception buffer; And a counter for outputting a signal bit for controlling the cell processing order of the cell conversion / multiplexing circuit to the cell conversion / multiplexing circuit side.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As shown in FIG. 1, a matching device between an ATM switch and a DS1E transmission device includes a transmission buffer 30, a reception buffer 40, a bus matching unit 60, a plurality of physical layer processing units 10, And a routing table 50, a multiplex demultiplexer 20, a microprocessor 70, a ROM 80, and a RAM 90.

In addition, as shown in FIG. 2, the multiplexing demultiplexer 20 includes a buffer 23, a routing table matching unit 21, a cell conversion / demultiplexing circuit 22, and a cell conversion / The multiplexing circuit 24 and the counter 25 are comprised.

In the configuration of FIG. 1, the transmission buffer 30 stores the internal cells applied from the bus matching unit 60 in the input order and outputs them to the multiplexing demultiplexer 20, and the receiving buffer 40 is multiplexed. The internal cells applied from the multiplexer 20 are sequentially stored and output to the bus matching unit 60. The bus matching unit 60 transfers the internal cells transmitted from the ATM exchanger via the bus to the transmission buffer 30 and transfers the cells applied from the reception buffer 40 to the ATM exchanger via the bus. The plurality of physical layer processing units 10 extract the ATM cells applied to the DS1E frame via the transmission line from the DS1E transmission apparatus, output them to the multiplexing demultiplexer 20, and from the multiplexing demultiplexer 20. The ATM cell, which is input and transmitted to the DS1E transmitter through the transmission line, is loaded on the DS1E frame and output. The routing table 50 records and stores the authorized routing information corresponding to the VPI and provides the routing information to the multiplexing demultiplexer 20. The multiplexing demultiplexer 20 converts an internal cell of the first predetermined bit transmitted from the transmission buffer 30 into an ATM cell of the second predetermined bit so that the physical layer processing unit 10 can process the same. Reads routing information corresponding to the VPI from the routing table 50, duplicates the ATM cell based on the routing information, outputs it to the physical layer processing unit 10, and is applied from the physical layer processing unit 10. ATM cells of two predetermined bits are converted into internal cells of the first predetermined bit and transmitted to the reception buffer 40. The microprocessor 70 reads the VPI and routing information included in the ATM cell applied from the physical layer processing unit 10 and stores the routing information in the position of the routing table 50 corresponding to the corresponding VPI. The ROM 80 stores a program necessary for the operation of the microprocessor 70, and the RAM 90 stores data generated by the operation of the microprocessor 70.

In the multiplexing demultiplexer 20 of FIG. 2, the buffer 23 sequentially stores the internal cells transmitted from the transmission buffer 30, and outputs them to the cell conversion / demultiplexing circuit 22. The routing table matching unit 21 reads the VPI in the header of the internal cell stored in the buffer 23 and reads out routing information corresponding to the corresponding VPI from the routing table 50. The cell conversion / demultiplexing circuit 22 converts the internal cells of the first predetermined bit transmitted from the buffer 23 into ATM cells of the second predetermined bit, and then based on the routing information transmitted from the routing table matching unit 21. The cell is duplicated and transmitted to the physical layer processing unit 10 on the corresponding transmission line side. The cell conversion / demultiplex circuit 24 converts the ATM cell of the second predetermined bit extracted from the physical layer processing unit 10 into an internal cell of the first predetermined bit to form a cell stream and outputs it to the reception buffer 40. . The counter 25 outputs signal bits for controlling the cell processing order of the cell conversion / multiplexing circuit 24 to the cell conversion / multiplexing circuit 24 side.

The matching device according to the present invention configured as described above operates as follows. The operation of the matching device of the present invention can be largely divided into two descriptions. The first is a case of transmitting a cell authorized from an ATM switch to a DS1E transmitter, and the second is a case of receiving a cell authorized from a DS1E transmitter and outputting the cell to an ATM switch.

First, when the ATM switch transmits a cell to the DS1E transmitter, an internal cell composed of 16 bits is transferred from the ATM switch to the bus matching unit 60 via the bus. The bus matching unit 60 outputs the transmitted internal cells to the transmission buffer 30. The transmission buffer 30 uses first-in first-out (FIFO) for outputting cells in a first-in, first-out manner. The transmitting buffer 30 stores the applied internal cells in an input order and provides them to the multiplexing demultiplexer 20. In this case, the multiplexer demultiplexer 20 reads a cell transmitted from the transmission buffer 30 and performs some processing. First, the physical layer processor converts an internal cell transmitted in 16 bits through the transmission buffer 30. Performs a function of converting into an 8-bit ATM cell for processing in (10). As described above, the operation of converting an 8-bit ATM cell is performed by the cell conversion / demultiplexing circuit 22 in the multiplexing demultiplexing unit 20, and the structure thereof is as shown in FIG. The internal cells applied from the bus matching unit 60 are stored in the buffer 23 in order. In this case, the routing table matching unit 21 reads the VPIs in the headers of the cells stored in the buffer 23 and the routing table ( 50). The routing table 50 has the same structure as shown in FIG. 3, and one-byte information recorded corresponding to each VPI is used as routing information. The routing information is used as information for specifying an output path of a cell. do. At this time, the VPI serves as an index for reading a table, and the contents of the address become routing information of a cell having the VPI. For example, in Figure 3, the content of address '00' is '10011001', which means that when a cell with a value of V00 is '00' is transmitted, the cell is copied to the 1st, 4th, 5th, and 8th transmission lines. The routing table matching unit 21 reads the routing information corresponding to the routing table 50 using the VPI input from the buffer 23 and outputs it to the cell conversion / demultiplexing circuit 22 side. do. The reason for having the buffer 23 is to allow time to perform the above functions. Accordingly, the cell conversion / demultiplexer 22 converts the internal cells applied from the buffer 23 into ATM cells based on the routing information from the routing table matching unit 21, and at the same time, the physical layer on the transmission line side. Output to the processing unit 10.

The cell output from the multiplex demultiplexing circuit 22 to the physical layer processing unit 10 has the form of an ATM cell, and the physical layer processing unit 10 loads an authorized ATM cell on a load portion of a DS1E frame and transmits the transmission line. Output to the DS1E transmitter via On the other hand, the contents of the routing table 50 is changed according to the input and output of the cell, the routing table 50 is managed by the microprocessor 70 and the routing table matching unit 21 only reads.

In the case of receiving the cell applied from the DS1E transmitter and outputting it to the ATM switch, when the signal of the DS1E frame applied from the DS1E transmitter through the transmission line is applied to the physical layer processor 10, the physical layer processor 10 Extracts an ATM cell from the corresponding DS1E frame and outputs the ATM cell to the multiplexer / demultiplexer 20 side. At this time, the cell conversion / multiplexing circuit 24 of the multiplexing demultiplexing unit 20 converts a cell input from the physical layer processing unit 10 into an internal cell which can be processed by an ATM exchanger, and then multiplexes it by receiving the buffer side. Output to. In other words, the cell conversion / multiplexing circuit 24 converts an 8-bit ATM cell into a 16-bit internal cell that can be processed by an ATM exchanger, and then outputs a cell stream to the receiving buffer 40. The reception buffer 40, like the transmission buffer 30, is also configured as a FIFO, and stores the applied internal cells in order and outputs them to the ATM exchanger via the bus matching unit 60 via the bus. Meanwhile, the cell conversion / multiplexing circuit 24 processes a cell based on a round-robin method, and performs a repetitive processing operation cyclically according to a signal bit applied from the counter 25. At this time, the cell processed by the cell conversion / multiplexing circuit 24 has an internal cell behavior of 16 bits and then is transmitted to the reception buffer 40. The internal cells stored in the reception buffer 40 are transmitted through the bus through the bus matching unit 60.

As described above, the present invention is a device having a matching function between a switch and a transmission line, and has a multicasting function capable of simultaneously sending a single cell to multiple transmission lines, and converting a protocol between an ATM switch and a conventional DS1E transmission device. As a result, the DS1E transmission device can be accommodated in an ATM switch, and the cell processing can be effectively performed since the processor intervention on the data transmission path is minimized.

Claims (2)

1. A matching device between an ATM switch and a DS1E transmission device, comprising: a transmission buffer 30 for storing and outputting applied internal cells in order; A receiving buffer 40 for storing and outputting the inner cells in order; A bus matching unit which transfers an internal cell transmitted from an ATM exchanger via a bus to the transmission buffer 30 and transfers a cell applied from the reception buffer 40 to the ATM exchanger via the bus ( 60); A plurality of physical layer processing units for extracting and outputting an ATM cell carried in a DS1E frame via a transmission line from a DS1E transmitter and outputting an ATM cell transmitted to a DS1E transmitter through the transmission line in a DS1E frame ( 10); A routing table 50 which records and stores the authorized routing information corresponding to the VPI; The internal cell of the first predetermined bit transmitted from the transmission buffer 30 is converted into an ATM cell of the second predetermined bit for processing by the physical layer processing unit 10 and simultaneously corresponds to a VPI in the header of the internal cell. A second predetermined bit applied to the physical layer processor 10 by replicating an ATM cell based on the routing information by reading routing information from the routing table 50; A multiplexing demultiplexer (20) for converting an ATM cell of the first predetermined bit into an inner cell and transmitting the same to a receiving buffer (40); A microprocessor (70) for reading routing information included in an ATM cell applied from the physical layer processing unit (10) and providing routing information to the routing table (50); A ROM (80) for inputting a program required for the operation of the microprocessor (70); And a RAM (90) for storing data generated by the operation of the microprocessor (70). The apparatus of claim 1, wherein the multiplexing demultiplexer (20) comprises: a buffer (23) for storing and outputting the inner cells transmitted from the transmission buffer 30 in order; A routing table matching unit 21 for reading and outputting routing information corresponding to the VPI in the header of the inner cell stored in the buffer 23 from the routing table 50; After converting the internal cells of the first predetermined bit transmitted from the buffer 23 to the ATM cells of the second predetermined bit, the cell is duplicated based on the routing information transmitted from the routing table matching unit 21 to correspond to the transmission line. A cell conversion / demultiplexing circuit 22 for transmitting to the physical layer processing section 10 on the furnace side; A cell conversion / multiplexing circuit 24 for converting the ATM cell of the second predetermined bit extracted from the physical layer processing unit 10 into an internal cell of the first predetermined bit to form a cell stream and outputting the cell stream to the receiving buffer 4 And; And a counter (25) for outputting signal bits for controlling the cell processing order of the cell conversion / multiplexing circuit (24) to the cell conversion / multiplexing circuit (24). Liver matching device.