KR100219581B1 - The color signal processing circuit of signal transform apparatus - Google Patents

Abstract

The present invention discloses a color signal processing circuit in a MUSE / NTSC converter.

The present invention has the effect of reducing the capacity of the memory and the unit cost of the product by processing the color signal using two field memories in the conventional color signal processing using one field memory.

Description

Color signal processing circuit in signal conversion device

1 is a diagram for explaining a MUSE signal format.

2 is a block diagram of a general signal conversion apparatus.

3 is a block diagram of a color signal processing circuit in a conventional signal conversion apparatus.

4 is a block diagram according to an embodiment of the color signal processing circuit in the signal conversion apparatus according to the present invention.

5A to 5G are operation timing diagrams of the time extension shown in FIG.

6A to 6C are operation timing diagrams of the multiplexer shown in FIG.

7A to 7C are operation timing diagrams of the parallel-to-serial converter shown in FIG.

8A to 8H are operation timing diagrams of the serial-to-parallel converter and the signal separator shown in FIG.

* Explanation of symbols for main parts of the drawings

310: vertical interpolation filter 320: chromatic signal calculation player and aspect ratio conversion unit

321, 322: first and second time extension 323: multiplexer

324 parallel-to-serial converter 325 field memory

326: serial-to-parallel converter 327: time delay

328, 329: 2nd flip flop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color signal processing circuit for reducing color memory by converting a memory capacity in a signal conversion device that enables high resolution video signals to be viewed on a standard television.

Currently, television is a different form by country and region. The differences between television systems include the scanning player, the aspect ratio of the screen, and the scanning method. And current television systems have limited resolution. The reason for this is that the improvement of TV picture quality until now has been difficult due to the limitation of the standard that maintains compatibility with existing methods, and the improvement of picture quality is difficult.

Accordingly, the result of the effort to improve the image quality regardless of the standard or compatibility is that the TV system having a higher resolution than the current TV system resolution, called MUSE (Multiple Sub-Nyquist Sampling Encoding). There is a high definition television system developed in Japan.

The mute method has an aspect ratio of 1125 scan lines and a screen of 9:16. Therefore, the current television receiver of NTSC system having 525 scanning lines and an aspect ratio of 3: 4 screen cannot receive a mute television signal.

Since the price of a separate receiver for receiving the HDTV broadcast is too expensive for the consumer to purchase, the HDTV signal transmitted by the MUSE method is removed in order to satisfy the desire of the HDTV broadcasting program of the consumer with the existing NTSC TV. MUSE / NTSC converters (hereinafter referred to as MNCs) have been developed for reception via NTSC televisions.

FIG. 1 is a diagram for explaining the format of a mute television signal (hereinafter referred to as a mute signal), and FIG. 2 is a block diagram of a general MNC.

The analog MUSE signal is input from the input signal processing unit 100, converted into a digital signal form, and output to the vertical interpolation filter units 210 and 310 for luminance and chromatic signals.

The MUSE signal passing through the luminance and chroma signal vertical interpolation filter unit 210 and 310 is finally output from the output signal processing unit 400 as an analog NTSC signal through the luminance and chroma signal scanning players and the aspect ratio converters 220 and 320. In addition, the control signal generator 500 generates and supplies various control signals necessary for each part.

Here, the luminance and chroma signal scanner and the aspect ratio conversion unit 220 and 320 cut out about 15% of the left and right sides of an HDTV image having an aspect ratio of 9:16, and take only 70% of the center of the HDTV screen in a 3: 4 ratio. Zoom-up mode for viewing at full resolution, full mode for 9–16 aspect ratio TVs with full aspect ratio while maintaining 525 lines at the current 3: 4 aspect ratio, : Vertical interpolation filter unit for luminance and chroma signal according to the wide mode converting so that 25% of the entire screen is displayed as a blanking state without any image on the top, bottom, top or bottom line while all the inside of the NTSC system of 4 is displayed. Muse signals output from (210,310) are written every other line in zoom-up mode and full mode, and every other line is written every other line in wide mode, and NTSC data conversion and aspect ratio conversion are performed. .

Here, the luminance signal vertical interpolation filter unit 210, the luminance signal scanning player and the aspect ratio converter 220 correspond to the luminance signal processing circuit 200, and the chroma signal vertical interpolation filter unit 310, the chroma signal scanning player and The aspect ratio converter 320 corresponds to the color signal processing circuit 300.

3 is a detailed block diagram of the conventional color signal processing circuit shown in FIG.

Referring to FIG. 3, the vertical pass filter 31 (VLPF) refers to the vertical interpolation filter unit 310 for chromaticity signal illustrated in FIG. 2.

In the MUSE method, since the chroma signal consists of two color difference signals of R-Y and B-Y, two field memories are required because the first and second field memories 32 and 33 for the two color difference signals are used, respectively.

However, as can be seen from the muse signal format shown in FIG. 1, in the MUSE method, since the chroma signal has a signal for only 1/4 of the time of the luminance signal, a memory having a capacity of 1/4 of the luminance signal is required. in need. Therefore, even if the two chroma signals are combined, only half of the field memory is required compared to the luminance signal. However, the use of two field memories causes inefficient use of the memory.

An object of the present invention is to provide a color signal processing circuit which can reduce the capacity of a memory in a signal conversion device.

It is still another object of the present invention to provide a color signal processing circuit which reduces the unit cost of a product by converting two color difference signals into one color using a field memory.

In order to achieve the above object, in the signal conversion apparatus according to the present invention, the color signal processing apparatus includes an input signal processing unit for converting a high-definition television signal having an aspect ratio and a scanning player from a standard signal into a digital luminance signal and a chromaticity signal; A luminance signal processing circuit for converting the luminance signal into an aspect ratio of the standard signal and a scanning player, a chromaticity signal processing circuit for converting the chroma signal into an aspect ratio and a scanning player of a standard signal, a luminance signal processing circuit and a chromaticity signal In the signal conversion device having an output signal processing unit for outputting the final standard signal from the output of the processing circuit:

The chroma signal processing circuit

A vertical interpolation filter unit for vertically interpolating the two color difference signals RY and BY output from the input signal processor, and a time extender for extending the N-bit color difference signals output from the vertical interpolation filter unit by N times in the time direction; ; A signal synthesizer for outputting the two color difference signals in one signal sequence at a data rate of N / 2 times the time extension; A parallel-to-serial converter for outputting a signal having n / 2 signal widths by dividing the upper and lower bits at a data rate of N / 4 times from the output of the multiplexer; A field memory for writing data at the clock speed of a high-definition television, reading the data at a clock speed of a standard signal, and outputting the output of the parallel-serial converter as a standard signal; A serial-to-parallel converter for outputting the output of the field memory at a data rate of 1/2 of a standard clock signal and outputting signals of upper and lower bits as a signal string of n bits; And a signal separator for delaying the output of the serial-to-parallel converter to separate the two color difference signals.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the color signal processing circuit in the signal conversion apparatus according to the present invention.

4 is a block diagram according to an embodiment of a color signal processing circuit in the signal conversion apparatus according to the present invention.

The configuration of the present invention is a vertical interpolation filter unit (VLPF: 310) for vertically interpolating the digital color signal of the incoming muse signal,

In order to extend the 8-bit U and V chroma signals output from the VLPF 310 in the time direction, a time extender comprising first and second FIFO memories 321 and 322 and an output of the first or second FIFO memories 321 and 322 are used. A signal synthesizer composed of a multiplexer 323 for configuring a signal sequence of a signal, and one signal string, which is 8 bits of the multiplexer 323, is divided into upper and lower bits, and the signal is multiplied by a time, and the 1/4 signal width is set as the same data rate. 8-bit signal from the 4-bit signal string of the field-to-serial converter 324 for outputting the signal to have, the field memory 325 for converting the output of the parallel-to-serial converter 324 into the NTSC color signal, and the field memory 325. To separate the RY signal from the output of the time-delay converter 326, the time delay 327 for time-delaying the data output by the serial-parallel converter 326, and the time delay 327. First D Flip-Flops (328) And a 2D type flip-flop 329 which separates only the B-Y signal from the output of the serial-to-parallel converter 326 and an aspect ratio converter 320 for the chroma signal.

The time delays 327 and the first and second di flip-flops 328 and 329 correspond to signal separators.

Next, the operation of the color signal processing circuit shown in FIG. 4 will be described with reference to the timing diagrams of FIGS. 5A to 8H.

The VLPF 310 vertically interpolates the color signals of the digital muse signals output from the input signal processing unit (not shown).

The U and V signals output from the VLPF 310 mean color difference signals (R-Y and B-Y are alternately output) which are serialized in sequence. That is, if U = R-Y and V = B-Y in one scan line, V = R-Y and U = B-Y in the next scan line.

In the first and second FIFO memories 321 and 322, two chroma signals U and V each having an 8-bit signal width output from the VLPF 310 are expanded four times in the time direction.

That is, a signal Din output from the vertical interpolation filter 310 shown in FIG. 5A is input to the first and FIFO memories 321 and 322, and this signal Din is the MUSE signal format shown in FIG. As can be seen from Figures 1 to 480, from the 12th to the 105th samples are chromaticity signal intervals, the chromaticity signals are written in the first and second FIFO memories 321 and 322 during this sample interval. The written write control signal WE1 is input.

When the twelfth signal is input, the reset signal RST1 as shown in FIG. 5C, which is a signal for initializing the write address points of the first and second FIFO memories 321 and 322, is activated to activate the first and second FIFO memories. Data writing is started at 321 and 322. When writing to the first and second FIFO memories 321 and 322 is completed, reading starts immediately.

The initialization of the read address points of the first and second FIFO memories 321 and 322 is performed when the reset signal RST4 as shown in FIG. 5E is activated, and has a period of 4 times than the write clock signal CLK shown in FIG. 5D. The read clock signal CLK4 shown in Fig. 5F is read. The signal Dout thus read is as shown in FIG. 5G.

This signal (figure 5G) is a signal extended by four times in the time direction, and the two extended arcs are made into one signal sequence by the following procedure.

That is, in the multiplexer 323, the extended chroma signal output from each of the FIFO memories 321 and 322 is time-multiplied by the selection control signal R / B.

The selection speed of the selection control signal R / B as shown in FIG. 6A is twice that of the read clock signals of the first and second FIFO memories 321 and 322, and the write clocks of the first and second FIFO memories 321 and 322. It has a half-clock degree rather than speed, and this signal makes it a signal sequence with 8 bits of signal width.

Specifically, two chroma signals are applied to the multiplexer 323 as first and second input signals, respectively, as shown in FIGS. 6B and 6C, which are four times elongated. The multiplexer 323 alternately selects two chromaticity signals inputted by the selection control signal R / B shown in FIG. 6A. Since the MUSE signal is serialized, the RY and BY are changed every scan line. It is input to the input of 323.

The selection control signal (R / B) of the multiplexer 323 inverts the phase every scan line in this order, so that the mixed chromaticity signal appearing at the output of the multiplexer 323 shown in FIG. Create and supply control signals so that the relationship is constant.

In parallel-to-parallel converter 324, the upper 4 bits and the lower 4 bits of the signal string (Fig. 7D) having 8 bits outputted from the multiplexer 323 by the clock signal H / L1 at the same speed as the write clock 5D. By time-division by dividing bit by bit, it outputs as a 4-bit signal having the same speed as the input data rate as shown in FIG.

That is, the 8-bit width signal output from the multiplexer 323 is divided into 4 bits each of the upper and lower portions so that the signal width is half and the signal speed is doubled if the time is multiplied on the same principle as the multiplexer 323.

This makes a signal string having the same clock speed as the original signal shown in FIG. 5A and having a signal width of 4 bits, and applying this signal to the field memory 325 to make one signal string 4 bits wide by time multiplexing. Is written as a mute signal clock signal (MUSE WE CK), and then read as an NTSC clock signal (NTSC RE CK) and converted into an NTSC signal.

Here, the clock signal of the mute signal has a 32.4 MHz, which is equal to the frequency of the write clock signal (FIG. 5D) of the FIFO memory, and the read clock signal (FIG. 5F) of the FIFO memory is 1/3 of 32.4 MHz. 4, the selection control signal R / B of the multiplexer 324 is 1/2 of 32.4 MHz, and the frequency of the clock signal H / L1 of the parallel-to-serial converter 324 is also 32.4 MHz.

In order to perform the inverse process of the parallel-serial converter and the multiplexer, the chromaticity signal is finally generated among the NTSC video signals through the serial-to-parallel converter and the signal separator.

That is, in the serial-to-parallel converter 326, the field memory 325 shown in FIG. 8C by the clock signal H / L2 shown in FIG. 8B having 1/2 frequency of the NTSC clock signal shown in FIG. A signal sequence consisting of 4 bits from the output of the C1) outputs a signal as shown in FIG. 8D having a signal width of 8 bits and halving the data rate by time multiplexing. In order to separate the two chroma signals mixed by the multiplexer 323, the time delay unit 327 delays the data of the output of the serial-to-parallel converter 326 (Figure 8D), as shown in Figure 8E. Output the signal.

Here, the NTSC clock signal is set differently according to each screen conversion mode, and has a frequency of 20 MHz in the zoom-up mode and 30 MHz in the full mode and the wide mode.

In the 1D type flip-flop 328, the time delay unit 327 is driven by the clock signal CLK shown in FIG. 8F having a period twice that of the clock signal H / L2 of the serial / parallel converter 326. FIG. An output (Fig. 8E) is input to hold the entire data up to the next rising edge at the moment of the rising edge to output the RY color difference signal sequence as shown in Fig. 8H.

In the 2D flip-flop 329, the output (8D) of the serial-to-parallel converter 326 is kept at the rising edge of the clock signal CLK shown in FIG. 8F immediately before the next rising edge. A BY color difference signal string is output as shown in FIG.

As described above, the color signal processing circuit in the signal conversion device according to the present invention can reduce the quantity of the field memory for chromaticity signal, thereby facilitating the production and reducing the price.

Claims (4)

An input signal processor for converting a high-definition television signal into a digital luminance signal and a chroma signal, and a luminance signal processing circuit for converting the luminance signal into an aspect ratio of the standard signal and a scanning player; And a chroma signal processing circuit for converting the chroma signal into an aspect ratio of the standard signal and a scanning player, and an output signal processing unit for outputting a final standard signal from the outputs of the luminance signal processing circuit and the chroma signal processing circuit. : The chroma signal processing circuit A vertical interpolation filter unit vertically interpolating two color difference signals R-Y and B-Y output from the input signal processing unit; A time extender for extending the n-bit color difference signal output from the vertical interpolation filter unit by N times in a time direction; A signal synthesizer for outputting the two color difference signals in one signal sequence at a data rate of N / 2 times the time extension; A parallel-to-serial converter that outputs a signal having n / 2 signal widths by dividing the upper and lower bits at a data rate of N / 4 times from the output of the signal synthesizer; A field memory for writing data at the clock speed of a high-definition television, reading the data at a clock speed of a standard signal, and outputting the output of the parallel-serial converter as a standard signal; A serial-to-parallel converter for outputting the output of the field memory at a data rate of 1/2 of a standard clock signal and outputting signals of upper and lower bits as a signal string of n bits; And And a signal separator for delaying the output of the serial-to-parallel converter to separate the two color difference signals. The method of claim 1, wherein the signal separator A time delay for delaying the data output by the serial-to-parallel converter; A first delay element for delaying an output signal of the time delay unit to separate a first color difference signal sequence and output the first color difference signal sequence to the output signal processor; And And a second delay element for delaying an output signal of the serial-to-parallel converter to separate a second color difference signal string and output the second color difference signal string to the output signal processor. 2. The signal of claim 1, wherein the time extender comprises first and second FIFO memories for writing data at a data rate of two color difference signals to be input, and reading data at a rate of 1 / N times. Color signal processing circuit in a converter. 4. The color signal processing circuit according to claim 3, wherein the signal synthesizer is a multiplexer for selectively outputting the outputs of the first and second FIFO memories at a rate twice the read speed.