KR100215900B1 - Eeprom memory device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to an EEPROM memory device and a manufacturing method.

Such an EEPROM memory device and a manufacturing method of the present invention comprises the steps of forming a trench in a semiconductor substrate in the form of a matrix, forming an insulating film on the entire surface of the trench formed substrate, and forming a data electrode in the trench, the exposed portion of the insulating film Selectively removing and forming a tunneling insulating film on the front surface, forming a plurality of conductor lines on the tunneling insulating film so as to be positioned above the data electrodes in one direction, and using the conductor lines as masks for the semiconductors Forming an impurity region in the substrate surface, depositing a dielectric film and a conductive layer on the entire surface and patterning the conductive layer, the dielectric film and the conductor line so as to remain between the data electrode and the data electrode in a direction perpendicular to the impurity region Multiple control gates and multiple floating crabs Forming a planar film, depositing a planarization insulating film on the entire surface, and forming a contact hole in each data electrode, and forming a plurality of data lines connected to the data electrode and on the planarization insulating film between the impurity regions. It was made to include.

Description

EEPROM memory device and manufacturing method

The present invention relates to a semiconductor memory device, and more particularly, to an EEPROM memory device and a manufacturing method.

Generally, semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices.

The most representative of the nonvolatile memory devices is an EEPROM memory device.

The conventional EEPROM will be described with reference to the accompanying drawings as follows. FIG. 1 is a plan view of a conventional EEPROM. FIG. 1 is a plan view of a conventional EEPROM. ) Is shown. 2 is a cross-sectional structural view taken along line I-I of FIG. 1, FIG. 3 is a cross-sectional structural view taken along line II-II 'of FIG. 1, and FIG. 4 is a conventional EEPROM circuit diagram.

In the conventional EEPROM memory, a plurality of impurity regions (bit lines, B / L 2) are formed on the surface of the semiconductor substrate 1 at regular intervals and arranged in one direction, and the impurities on the semiconductor substrate 1 are formed. A plurality of data electrodes 5 in which the oxide film 3 and the polycrystalline silicon 4 are stacked in a matrix form is formed between the regions 2. Here, the impurity regions 2 are formed in a high concentration N-type, and the bit lines line).

A tunneling oxide 6 is formed over the semiconductor substrate 1 including the data electrode 5, and the data arranged in the matrix form on the semiconductor substrate 1 between the impurity regions 2. A floating gate 7 is formed between the electrodes 5.

An interlayer dielectric film 8 is formed on the surface of the floating gate 7, and a field oxide film 9 is formed above the impurity region.

On the interlayer dielectric film 8 and the field oxide film 9 on the floating gate 7, a control gate (word line) is arranged in a direction perpendicular to the impurity region 2 at regular intervals. 10 is formed, and an insulating film 11 and a planarizing insulating film 12 are formed on the entire surface of the substrate including the control gate 100.

A contact hole is formed on the data electrode 5, and a data line 13 is formed on each data electrode 5 through the contact hole. Here, the data line 13 is formed on the planarization insulating film 12 between the impurity regions 2 so as to be parallel to the impurity region 2 and perpendicular to the control gate 10. The floating gate 7 is insulated from the insulating film side surface 14.

The characteristic of such an EEPROM cell is that the impurity region 2 is attached to the semiconductor substrate 1 in a line shape and connects the cells with the cells completely symmetrically, and one impurity region 2 is used for any cell. VGM (Virtual Ground Mode) acts as a drain region and as a source region for the next cell. In addition, the data line 13 is connected to the data electrode 5, but the channel widths of the cell transistors are distinguished by forming the islands of the data electrodes 5 in an island shape.

A conventional method of manufacturing an EEPROM having such a feature is not shown in the drawing. However, the oxide film 3 of the data electrode is first defined as a line, and is then etched by Se1f align when the floating gate 7 is patterned. It is etched into an island shape. Similarly, the floating gate 7 is formed in an island shape when patterning the control gate 10.

As described above, in order to realize the above structure, a process of sequentially self-aligning the poly conductive layer (polysilicon) / dielectric layer / conductive layer (polysilicon) is required twice.

The operation of the conventional EEPROM formed as described above will be described with reference to FIG.

First, during programming, the programmer applies a negative voltage to the data lines 13 and DL of the cell and a positive bias to the control gates 10 and W / L. One of the two impurity regions 2 and B / L of the corresponding cell is grounded and the other is applied with a low positive voltage.

Then, electrons are injected from the control gate 10 (W / L) to the floating gate 7 by tunneling. The MOSFET transistors can then be freed from the program's functionality to monitor the degree of electron injection over time, that is, the program.

As more electrons are injected into the floating gate 7, the drain current decreases and the threshold voltage V _T increases.

Therefore, if the program is executed on the array, the threshold voltages of all the programmed cells can be adjusted to be automatically set to a random value.

On the other hand, erasure is performed by tunneling, and electrons injected into the floating gate 7 are mainly erased through a channel, a source, or the like of the MOSFET.

Such a conventional EEPROM has the following problems.

As described in the operation of the prior art, the conventional stacked gate EEPROM cell has better program characteristics than any cell that has appeared so far.

However, two self-alignments are required when forming the data electrode and the floating gate, and the step of the cell is large, so the margin of the process is very small.

Disclosure of Invention The present invention has been made to solve such a problem, and an object thereof is to provide an EEPROM memory device and a manufacturing method capable of simplifying a process and reducing a cell step by using one self-alignment.

1 is a structural plan view of a conventional EEPROM memory device

FIG. 2 is a cross-sectional structural view taken along line II ′ of FIG. 1;

3 is a cross-sectional structural view taken along line II-II 'of FIG.

4 is a schematic block diagram of a conventional EEPROM.

5 is a structural plan view of the EEPROM memory device of the present invention.

FIG. 6 is a cross-sectional view of an EEPROM memory device of the present invention along the line II ′ of FIG. 5;

FIG. 7 is a cross-sectional view of an EEPROM memory device of the present invention on the line II-II ′ of FIG. 5; FIG.

8A to 8I are cross-sectional views of the present invention EEPROM memory device on the line II ′ of FIG. 5.

9A to 9I are cross-sectional views of the inventive EEPROM memory device along the line II-II ′ of FIG. 5.

* Explanation of symbols for main parts of the drawings

21: semiconductor substrate 22, 24, 27, 32, 34, 37: insulating film

23: trench 25,28,33: polysilicon

26 data electrode 29 photosensitive film

30 impurity region 31 protrusion

35: floating gate 36: control gate

38: contact hole 39: data line

40: sidewall insulating film

EEPROM memory device of the present invention for achieving the above object is a semiconductor substrate having a plurality of trenches arranged in a matrix form, a plurality of impurity regions formed in the semiconductor substrate surface between the trenches in one direction at a predetermined interval, A plurality of data electrodes insulated from the semiconductor substrate in the trench, a plurality of floating gates formed in a matrix form between the data electrodes, and a plurality of controls formed above the floating gate in a direction perpendicular to the impurity region It is characterized by including a gate, a floating gate and a plurality of data lines formed to be connected to the data electrode above the data electrode so as to be parallel to the impurity region.

In addition, the method of manufacturing the EEPROM memory device of the present invention for achieving the above object comprises the steps of forming a trench in a matrix form on the first conductivity-type semiconductor substrate, forming an insulating film on the entire surface of the substrate on which the trench is formed and forming a data electrode in the trench Forming a tunneling insulating film on a front surface of the insulating film, selectively removing an exposed portion of the insulating film, and forming a plurality of conductor lines on the tunneling insulating film so as to be positioned above the data electrodes in one direction; Forming an impurity region in the surface of the semiconductor substrate using each conductor line as a mask, depositing a dielectric film and a conductive layer over the entire surface and remaining between the data electrode and the data electrode in a direction perpendicular to the impurity region Patterning a layer, a dielectric film, and the conductor line Forming a troll gate and a plurality of floating gates, depositing a planarization insulating film on the entire surface, and forming a contact hole in each of the data electrodes, and forming a plurality of floating gates on the planarizing insulating film connected to the data electrodes and between the impurity regions. It is characterized by the step of forming a data line.

The present invention as described above will be described in more detail with reference to the accompanying drawings.

Fig. 5 is a plan view of the EEPROM memory device of the present invention, Fig. 6 is a sectional view taken along line II ′ of Fig. 5, and the structure of the present invention on the line EEPROM memory device. EEPROM memory device structure cross section.

In the structure of the EEPROM memory device of the present invention, a plurality of impurity regions 30 are formed in the surface of the semiconductor substrate 21 in one direction (in the horizontal direction in FIG. 5) at regular intervals.

A plurality of trenches 23 are formed in a matrix form in the semiconductor substrate 21 between the impurity regions 30, and are insulated from the semiconductor substrate by an insulating film 24 in the trench 23 to form a plurality of data electrodes ( 26) is formed.

A plurality of floating gates 35 are formed between the data electrodes 26 on which the impurity regions 30 are not formed so that the data electrodes 26 and the corner portions overlap each other in a matrix form. Here, each floating gate 10 has a protrusion 31 between the data electrode 26 and the semiconductor substrate 21.

A plurality of control gates 36 are formed above the floating gate 35 in a direction perpendicular to the impurity region 30, and the floating gate 35 and the data electrode 26 are parallel to the impurity region 30. The data line 39 is formed on the upper side.

Here, an insulating film 34, which is a capacitance dielectric film, is formed between each floating gate 35 and the control gate 36, and a flattening insulating film 37 is formed above the control gate 36 to control the gate. 36 and data line 39 are insulated and data line 39 is electrically connected to data electrode 26. The width of each floating gate 35 and the width of the control gate 36 formed on the upper side are formed to be the same width.

The manufacturing method of the EEPROM memory device of the present invention having such a configuration is as follows.

8 (a) to (i) are cross-sectional views of the EEPROM memory device of the present invention along the II 'line of FIG. 5, and FIGS. 9 (a) to (i) the present invention EEPROM memory on the II-II' line of FIG. Process sectional drawing of an element.

In the method of manufacturing the EEPROM memory device of the present invention, as shown in Figs. 8A and 9A, a first insulating film (oxide film) is formed on a first conductive type (p-type) semiconductor substrate 21 having a specific resistance of about 3 to 20 Ωcm. ) 22 and a photosensitive film (not shown) are sequentially deposited and the trench formation region is defined by exposure and development. At this time, the thickness of the first insulating film 22 is about 100 to 1000 nm.

The first insulating film 22 and the semiconductor substrate 21 are etched to a predetermined depth to form the trench 23. At this time, the depth of the trench 23 is about 1.0 to 2.0 mu m. Then, by using the first insulating film 22 as a mask, ions are implanted into the sidewalls and the bottom surface of the trench 23 for the electrical isolation within the trench. At this time, the dopant uses BF2 and its concentration is about 2.0E12 to 5.0E13 to perform rotation and gradient ion implantation.

As shown in FIGS. 8B and 9B, the photosensitive film and the first insulating film 22 are removed, and a second insulating film 24 is formed on the entire surface of the substrate on which the trench is formed. At this time, the second insulating film 24 is used to isolate the trench from the trench and to isolate the electrode and the substrate to be formed next. The second insulating film 24 is formed by thermal oxidation and has a thickness of about 10 to 20 nm.

The first polysilicon 25 is deposited to a thickness of 1/2 or more of the trench width so as to completely fill the trench 23 on the entire surface of the second insulating layer 24. At this time, the first polysilicon 25 is n-type and in-situ doped or deposited and then doped at the same time as the deposition during CVD.

As shown in FIGS. 8C and 9C, the first polysilicon 25 is etched back and patterned so that the first polysilicon 25 remains only in the trench, thereby forming the data electrode 26. The etching end point may be sensed by the second insulating film 24 exposed on the surface, and chemical mechanical polishing is performed on the etching of the first polysilicon 25 to obtain a more flat surface. It may be.

The exposed portion of the second insulating layer 24 is removed by wet etching.

At this time, inside the trench, the second insulating film 24 lower than the data electrode 26 is left on the side of the trench 23.

As shown in FIGS. 8D and 9D, the third insulating layer 27 and the n-type second polysilicon 28 are sequentially formed on the entire surface of the substrate including the data electrode 26. At this time, the third insulating film 27 is a tunneling insulating film, and is formed by thermal oxidation to a thickness of about 5 to 15 nm.

As shown in FIGS. 8E and 9E, the photoresist layer 29 is deposited on the second polysilicon 28, exposed to light, and developed to form one direction (horizontal direction) of the data electrodes 26 formed in the matrix form. The second polysilicon 28 is patterned so as to be positioned above the data electrodes 26. Then, using the patterned second polysilicon 28 as a mask, impurity ions are implanted into the surface of the semiconductor substrate 21 between the data electrodes 26 (high concentration n-type impurity ions implanted) to thereby form a bit line impurity region 30. ). At this time, the impurity implants As ⁺ ions at a concentration of about 1.0E15 to 2.0E16, and the second polysilicon 28 is formed to have the protrusion 31 at the corner of the data electrode 26. The reason is that the third insulating film 27 is formed on the side surface of the trench 23 with the first insulating film 24 lower than the data electrode 26, so that the semiconductor substrate 21 and the data electrode 26 are formed. The second polysilicon 28 has a protrusion 31 at the portion because is formed so that the step is lower than the peripheral portion thereof.

As shown in FIGS. 8F and 9F, the photoresist film is removed, and a sidewall insulating film (oxide film) 40 is formed on the sidewall of the patterned second polysilicon 28, and then a fourth insulating film, which is an interlayer dielectric film, on the front surface. 32 is deposited. The third polysilicon 33 and the fifth insulating film (CVD oxide film) 34 are sequentially deposited on the fourth insulating film 32. In this case, the fourth insulating layer 32 uses a silicon oxide film / silicon nitride film / silicon oxide film ONO to secure a capacitive coupling ratio between the floating gate and the control gate.

As shown in FIGS. 8G and 9G, the fifth insulating layer 34 and the third poly may be left between the data electrode 26 and the data electrode 26 in a direction perpendicular to the impurity region 30. The silicon 33, the fourth insulating film 32, and the second polysilicon 28 are patterned. Here, the second polysilicon 28 is patterned in an island shape between the data electrodes 26 to form a floating gate 35, and the third polysilicon 33 is a control gate (or word line) 36. The edges of the floating gate 35 and the data electrode 26 overlap each other.

8 (h) and 9 (h), the planarization sixth insulating film 37 is deposited on the entire surface, and the sixth insulating film 37 and the third insulating film 27 are selectively removed to remove each data electrode ( A contact hole 38 is formed in 26. In this case, the sixth insulating layer 37 is formed by stacking a doped oxide layer and BPSG doped with boron or phosphorus (P).

8 (i) and 9 (i), a metal layer is deposited on the entire surface, and a data line 39 is formed on the sixth insulating layer 37 for planarization so as to be perpendicular to the control gate 35 and remain only between the impurity regions. do. In this case, the data line 39 is electrically connected to the data electrode 26.

As described above, the EEPROM manufacturing method of the present invention has the following effects.

First, since trenches are formed in the semiconductor substrate, data lines are connected, and data electrodes for injecting electrons into the floating gate are formed in the trenches, thereby eliminating a step, thereby facilitating subsequent processes and improving contact margins.

Second, since the first patterning is performed in the form of a line when forming the floating gate, and then the floating gate is patterned into an island shape when the control gate is formed, the process is simplified because the mask process is reduced.

Claims (20)

A semiconductor substrate having a plurality of trenches arranged in a matrix; A plurality of impurity regions formed in the semiconductor substrate surface between the trenches in one direction at regular intervals; A plurality of data electrodes insulated from the semiconductor substrate in the trench; a plurality of floating gates formed in a matrix form between the data electrodes; A plurality of control gates formed above the floating gate in a direction perpendicular to the impurity region; And a plurality of data lines formed on the floating gate and an upper axis of the data electrode so as to be connected to the data electrode so as to be parallel to the impurity region. The semiconductor device of claim 1, further comprising: a dielectric film formed between the floating gate and the control gate; A planarization insulating layer formed between the control gate and the data line; And a tunneling insulating film formed between the data electrode and the floating gate. The EEPROM memory device of claim 1, wherein each of the floating gates and the control gates has the same width. The EEPROM memory device of claim 1, wherein each of the floating gates is formed such that the edges of the floating data electrodes overlap each other. The EEPROM memory device of claim 1, wherein each floating gate has a protrusion between an adjacent data electrode and a semiconductor substrate. Forming a trench in the form of a matrix on the semiconductor substrate; Forming an insulating film on the front surface of the substrate, the trench, and forming a data electrode in the trench; Selectively removing the exposed portions of the insulating film and forming a tunneling insulating film on the entire surface of the insulating film; Forming a plurality of conductor lines on the tunneling insulating layer so as to be positioned above the data electrodes in one direction; Forming impurity regions in the surface of the semiconductor substrate using the respective conductor lines as masks; A dielectric film and a conductive layer are deposited on the entire surface, and the conductive layer, the dielectric film, and the conductive line are patterned so as to remain between the data electrode and the data electrode in a direction perpendicular to the impurity region, thereby controlling the plurality of control gates and the plurality of floating gates. Forming a; Depositing a planarization insulating film on an entire surface and forming contact holes in each of the data electrodes; And forming a plurality of data lines on the planarization insulating film between the impurity regions and connected to the data electrodes. 7. The semiconductor substrate of claim 6, wherein the semiconductor substrate has a resistivity of 3 to 20. An EEPROM memory device manufacturing method characterized by using a P-type semiconductor substrate of cm. The method of claim 6, wherein the trench has a depth of about 1.0 μm to about 2.0 μm. 7. The method of claim 6, further comprising ion implanting impurities for electrical isolation in the trench into sidewalls and bottom surfaces of the trench. 10. The method of claim 9, wherein the impurity uses BF ₂ and the concentration is 2.0E12 to 5.0E13 to rotate or incline ion implantation. 7. The method of claim 6, wherein the insulating film is formed by thermal oxidation and has a thickness of about 10 to 20 nm. The method of claim 6, wherein the method of forming a data electrode is performed by depositing polysilicon to a thickness of at least 1/2 of the trench width, and etching back the polysilicon to pattern the polysilicon to remain only in the trench. EEPROM memory device manufacturing method characterized in that. The method of claim 12, wherein the polysilicon is formed in an n-type, and the data electrode is formed in the trench using chemical mechanical polishing to etch the polysilicon. The method of claim 6, wherein the insulating layer is formed on the side of the trench to be lower than the data electrode when the insulating layer is removed. The method of manufacturing a EEpROM memory device according to claim 6, wherein the tunneling insulating film is formed by thermal oxidation at 5 to 15 nm. 7. The method of claim 6, wherein the impurity region is formed by implanting As ⁺ ions at a concentration of 1.0E15 to 2.0E16. The method of claim 6, wherein the floating gate is formed to have a protrusion between the semiconductor substrate and the data electrode. 7. The method of claim 6, further comprising forming a sidewall insulating film on the sidewalls of the conductor lines. 7. The method of claim 6, wherein the dielectric film is formed of a silicon oxide film / silicon nitride film / silicon oxide film (ONO). 7. The method of claim 6, wherein the floating gate and the data electrode are formed such that edge portions thereof overlap each other.