KR100214483B1 - Dram for multi-bit input and output - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a DRAM for a multi-bit input / output, and conventionally, a data bus is allocated to each sense amplifier array, and the number of memory cell arrays do. However, since the sense amplifier array is a block used repeatedly in a layout, when a data bus is added, the chip size becomes large due to an increase in the layout area, and when the number of simultaneously operating memory cell arrays increases, power consumption becomes large. Therefore, according to the present invention, the data bus is shared between the adjacent sense amplifier arrays only by changing the twist of the data bus and the column decoder control, thereby doubling the number of data bits input / output to / from the memory cell without increasing the layout area. When applied, the test time can be reduced, and the number of bits processed in parallel can be increased to make the chip faster.

Description

Dram for multi-bit input and output

FIG. 1 is a diagram showing a conventional DRAM structure for multi-bit input / output.

FIG. 2 is a diagram showing a DRAM structure for multi-bit input and output according to the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

100a, 100A: memory cell array 200a, 200A: sense amplifier array

300, 300A: column switches 400a, 400A: column decoder

The present invention is directed to increase the number of bits output from a memory cell or input to a memory cell without increasing the layout area and access time in a DRAM, and in particular, a data bus is provided between a sense amplifier array and a sense amplifier array adjacent to the sense amplifier array. Bit input / output, which can be used by doubling the number of data bits input to or outputted from a memory cell without increasing the layout area by using the data bus with a twist.

As shown in FIG. 1, a conventional DRAM structure for a multi-bit input / output is a memory cell array (hereinafter, referred to as " DRAM ") having a plurality of structures each having a cell connected between a word line and a bit line, A plurality of amplifiers 10A for amplifying the sensed signals at the full-logic level and for sensing the bit lines according to the driving signals SP or SNB, respectively, A sense amplifier array 20 consisting of sense amplifiers of the memory cell array 10a and 10A is connected to the memory cell arrays 10a and 10A via a block selection switch BSU or BSD, a data bus DB for writing data in a memory cell or transferring data in a memory cell to a peripheral circuit is connected to the sense amplifier array 20 by a column switch 30 and the column switch 30 is connected to a column address Decode Is configured to input a control signal from the column decoder (40a) or (40b).

Further, the dummy adjacent to the lower side also has the same configuration.

The conventional technique configured as described above will be described as follows.

When the block select switch BSU or BSD is turned on by an external row address, the equalized signal EQPR transits from the high state H to the low state L, The transistor is turned off so that the pre-charge of the sense amplifier array 20 is released and the preamplifier does not operate.

Then, when one word line in the memory cell array 10a or 10A is selected, the data of the memory cell is outputted as a bit line.

At this time, the amplifier driving signals SP and SNB transit to high H and low L, respectively, so that the sense amplifier of the sense amplifier array 20 can operate.

The sense amplifier senses data of a memory cell transferred to the bit line, and amplifies the sensed signal to a full-logic level.

When the column decoder 40a or 40b receives and decodes the column address and outputs the selected selection signal to the selection switch 30, the selection switch 30 selects the column decoder 40a or 40b ) Receives the selection signal and turns on one of the column switches.

Then, the sense amplifier array 20 and the data bus DB are connected by the ON column switch, and the data output from the sense amplifier array 20 is output to the required peripheral circuit through the data bus DB.

On the other hand, a sense amplifier not selected in the sense amplifier array 20 maintains the precharge state, and the data bus on the sense amplifier remains in the precharge state.

When data is inputted from the outside through the data bus DB, one of the column switches 30 is turned on by the column decoder 40a or 40b to turn on the sense amplifier of the sense amplifier array 20 And the signal amplified by the selected sense amplifier is stored in the memory cell in the memory cell array 10a or 10A selected by the block selection switch (BUS) or (BSD).

However, according to the conventional technique as described above, the number of bits input to or output from a memory cell at the same time is increased due to a demand for a high-speed operation and a multi-bit parallel test. Of the total number.

Therefore, in the conventional art, the data buses are allocated to each sense amplifier array, so that the number of memory cell arrays which increase the number of data buses or operate simultaneously must be increased for each sense amplifier array. However, since the sense amplifier array is a block used repeatedly in a layout, when a data bus is added, the chip size becomes large due to an increase in the layout area, and when the number of simultaneously operating memory cell arrays increases, power consumption becomes large.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data bus which is twisted with a data bus of a sense amplifier array in the middle of a sense amplifier array so that the number of data bits input to or output from a memory cell And to provide a DRAM for a multi-bit input / output which can be used by doubling it.

Another object of the present invention is to provide a DRAM for a multi-bit input / output which enables a high-speed chip by increasing the number of parallel processed bits by using a data bus in a twisted state.

According to an aspect of the present invention, there is provided a DRAM structure for a multi-bit input / output, the memory array including a word line and a bit line, A column switch for selecting the upper and lower memory cell arrays under the control of a sense amplifier array and a column decoder is sequentially disposed in the memory cell array above and the memory cell array is disposed between the column switch and the lower memory cell array, The data bus for writing the data input to the memory cell into the memory cell or transmitting the data of the memory cell to the peripheral circuit is configured by being twisted with the data bus of the adjacent sense amplifier array.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a diagram showing the structure of a DRAM for input / output of a plurality of bits according to the present invention. As shown in FIG. 2, the memory cell array 100a (100a) includes a plurality of memory cells connected between a word line and a bit line, The sense amplifier array 200 and the column decoders 400a and 400b, which are composed of a plurality of sense amplifiers for amplifying the bit lines to the full-logic level after sensing the bit lines, A column switch 300 for selecting the upper or lower memory cell array is sequentially arranged under the upper memory cell array 100a and between the lower memory cell array 100A and the column switch 300 A data bus (DB) for writing data inputted from the outside into the memory cell or transferring the data of the memory cell to the peripheral circuit is connected to the data bus of the adjacent sense amplifier array It is twisted and constitutes.

The operation and effect of the present invention will be described in detail as follows.

The arrangement of the memory cell arrays 100a and 100a and the sense amplifier array 200 is the same as that of the prior art but the data bus DB connected to the sense amplifier array 200 through the column switch 300 is connected to the adjacent sense amplifier array 200A with the data bus DBa.

At this time, if the word line strap region is used for the data bus twist, the data bus twist is possible without increasing the layout area.

In addition, the column decoders 400a and 400b have one left and right based on the data bus twist, and the two column decoders 400a and 400b can operate simultaneously.

That is, when the two column decoders 400a and 400b selected by the column address operate simultaneously, the data of the sense amplifier arrays 200 and 200A selected by the column decoder 400a is supplied to the adjacent sense amplifier arrays 200 ' The data of the sense amplifier arrays 200 'and 200A' selected by the column decoder 400b are output to the peripheral circuits through the data bus DB on the selected sense amplifier array 200A 200 'to the peripheral circuit via the data bus DB.

Input / output of data based on the operation of the data bus DB described so far will be described. When the block select switch BSU or BSD is turned on by an externally input row address, the equalized signal EQPR, The transition from the high state H to the low state L causes the equalizing MOS transistor to be turned off so that the precharging of the sense amplifier array 200 is canceled and the preamplifier is not operated.

Then, if one word line in the memory cell array 100a is selected, for example, the data of the memory cell is output to the bit line.

At this time, the amplifier driving signals SP and SNB transit to high H and low L, respectively, and the sense amplifier of the sense amplifier array 200 operates.

The sense amplifier senses data of the memory cell transferred to the bit line, and the sensed signal is amplified to a full-logic level.

The column decoder 40a receives and decodes the column address and outputs the decoded selected signal to the selection switch 300. The selection switch 300 receives the selection signal output from the column decoder 400a Turn on one of the column switches.

Then, the sense amplifier array 200 and the data bus DB are connected by the ON column switches, so that the data output from the sense amplifier array 200 is supplied to the sense amplifier array 200A 'through the data bus of the adjacent sense amplifier array 200A' To the peripheral circuit.

At the same time, if one word line in the memory cell array 100a 'is selected, the data of the memory cell is output to the bit line, and the sense amplifier array 200' is turned on by the amplifier driving signal SP (SNB) A sense amplifier operates and senses and amplifies the sensed signal to a full-logic level.

At this time, the column decoder 400b receives and decodes the column address, and outputs the selected selection signal to the selection switch 300 '. When the selection switch 300' receives the selection signal from the column decoder 400b, And turns on one of the column switches.

Then, the sense amplifier array 200 'and the data bus are connected by the ON column switches so that the data output from the sense amplifier array 200' is supplied to the necessary peripheral circuits through the data bus of the adjacent sense amplifier array 200A .

That is, the data of the sense amplifier array selected by one of the column decoders is outputted to the peripheral circuit through the data bus on the selected sense amplifier array by operating the column decoders at the left and right of the data bus twist simultaneously or simultaneously, The data of the selected sense amplifier array is outputted to the peripheral circuit through the data bus on the adjacent sense amplifier array.

As described above, by sharing the data bus between adjacent sense amplifier arrays only by changing the twist of the data bus and the column decoder control, the number of data bits input / output to / from the memory cell simultaneously increases twice without increasing the layout area. The test time can be reduced and the number of bits to be processed in parallel can be increased, which makes it possible to speed up the chip.

Claims (3)

By arranging a memory cell array composed of word lines and bit lines on the upper and lower sides respectively and controlling the sense amplifier array and the column decoder for sensing the bit lines and amplifying them to a full logic level, A column switch for selecting one of the column switches is sequentially arranged under the memory cell array above the memory cell array, and the memory cell array is disposed between the column switches and the lower memory cell array, Wherein the data bus for transmitting data to the sense amplifier array is twisted with a data bus of an adjacent sense amplifier array. 2. The DRAM of claim 1, wherein the column decoder causes the left and right decoders to operate concurrently on the basis of the data bus twist. 2. The DRAM of claim 1, wherein the data bus twist is used in a word line strap region.