KR100205241B1 - Row decoding circuit of nonvolatile semiconductor memory - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a row decoder of a nonvolatile semiconductor memory device for selecting word lines of a memory cell array and driving it to a voltage required in each operation mode. According to this apparatus, a predetermined voltage level is applied to the gate of the transfer transistor corresponding to the non-selected external address by using precharge means to prevent GIBV of the transfer transistor of the row decoder from being lowered. Thus, the GIBV of the transfer transistor corresponding to the non-selected external address can be increased. Thus, by applying the voltage of zero volts to the gate of the transfer transistor corresponding to the non-selected external address in the conventional manner at a predetermined voltage level through the precharge means, the program voltage is sufficiently supplied to the word line Line. Therefore, not only the program speed can be increased, but also the program yield can be prevented from being lowered.

Description

A row decoder of a nonvolatile semiconductor memory device. (row decoder of non volatile semiconductor memory device)

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a row decoder of a nonvolatile semiconductor memory device for selecting word lines of a memory cell array and driving it to a voltage required in each operation mode.

The NAND type flash memory device or the EEPROM (electrically erasable programmable read only memory) is composed of a plurality of NAND cell units including a plurality of memory cells. Each of the memory cells has a structure in which a source and a drain are formed with a channel therebetween, and a gate oxide film, a floating gate, an ONO film, and a control gate are sequentially formed on the channel. Each corresponding word line is connected to a control gate of each memory cell of each NAND cell unit. Then, each memory cell is programmed using F-N tunneling in which electrons move from the channel region to the floating gate through the gate oxide film. At this time, to program the memory cells, a high voltage is applied to the selected word line connected to the control gates of the memory cells. Here, a row decoder is needed which can hold or maintain the high voltage at a constant reference value and transfer it only to necessary word lines to write or erase data.

1 is a circuit diagram showing a circuit of a row decoder of a conventional nonvolatile semiconductor memory device.

1, the memory cell array 10 includes a plurality of NAND cell units CU, and each of the NAND cell units CU includes a floating gate and a control gate And a plurality of memory cells. The control gates of the memory cells of each of the NAND cell units CU are commonly connected to corresponding word lines W / Lk-W / Ln, where k and n are positive integers. Each word line W / Lk-W / Ln of the memory cell array 10 is selected by the row decoder 20 and receives the word line voltage required in each operation mode from the row decoder 20. The row decoder 20 is composed of row decoder blocks 22k-22n corresponding to the word lines W / Lk-W / Ln of the memory cell array 10, respectively. Each of the row decoder blocks 22k to 22n includes a NAND gate G1, diffusion MOS transistors D1 and D2, a switch pump 11 and a transfer transistor T1. An address (k_address), a clock signal (1o), and a control signal (VSi + Vth, where VSi represents an external high voltage applied from the outside in a program or read operation and Vth represents a threshold voltage of the transfer transistor T1) to the gate of the transfer transistor T1 do.

That is, a high level is applied to the selected external address, a low level is applied to the non-selected external address, and the clock signal 1o is applied to the square wave having the predetermined frequency. The NAND gate G1 is enabled only when an external address is selected and transmits the clock signal 1o to the switch pump 11 so that the switch pump 11 operates to set the high voltage VSi + Vth) is output and the high voltage (VSi + Vth) is applied to the gate of the transfer transistor T1. Accordingly, the high voltage VSi (high voltage for performing the program or read operation) applied from the outside through the transfer transistor Tl is transferred to the word line corresponding to the selected external address.

Hereinafter, the operation of the conventional row decoder will be described with reference to FIG.

The selected external address (k_address - n_address) inputted to the row decoder 20 during the program operation or the read operation is applied to the high level and the non-selected external address is applied to the low level, respectively, and the clock signal 1o And is applied to a square wave having a predetermined frequency. A NAND gate G1 receiving an externally selected external address (k_address) and a clock signal 1o having a predetermined frequency is enabled by the signals (k_address, '1o) to switch the clock signal 1o To the pump (11). Therefore, the switch pump 11 performs a voltage pumping operation by the clock signal 1o to generate a high voltage (VSi + Vth), and the high voltage (VSi + Vth) generated from the switch pump 11 is supplied to the conductive path (L1). Thus, the transfer transistor T1 whose gate is connected to the conductive path L1 is turned on and a high voltage which is an external voltage VSi applied to the drain of the transfer transistor T1 is applied to a word line corresponding to a selected external address (k_address) (W / Lk).

On the other hand, when the external address applied from the outside is not selected, the control signal The control transistor 3 to which the gate of the control transistor 3 is applied and the depletion MOS transistor D2 whose gate is connected to the power supply terminal 5 to which the power supply voltage Vss is applied are all turned on, A non-selected external address (n_address) of a low level is transferred to the conductive path L1. Accordingly, the transfer transistor T 1 whose gate is connected to the conductive path L 1 is turned off, and a high voltage VSi applied from the outside is applied to the word line W / Ln corresponding to the non-selected external address n_address Thereby blocking the transmission.

However, according to the row decoder as described above, a high voltage (external high voltage (Vsi) applied from the outside + threshold voltage (Vth) of the transfer transistor) is applied to the gate of the transfer transistor corresponding to the external address selected in the program operation, 0 volt is applied to the gate of the transfer transistor corresponding to the selected external address. The gate induced breakdown voltage (GIBV) of the MOS transistor has a lower GIBV when zero volts are applied to its gate and the voltage level that can be transmitted through the transistor is lowered. That is, since the gate of the transfer transistor corresponding to the non-selected external address is applied with 0 volt, the GIBV value of the transistor is lowered. Therefore, current leakage occurs due to the downward GIBV value when a high voltage (VSi) equal to or higher than the GIBV value of the transfer transistor is applied to the drain thereof.

Therefore, even when the external high voltage (VSi) is applied at a high level, the program voltage applied to the word line of the cell can not be increased beyond the GIBV value of the transfer transistor corresponding to the non-selected external address. As a result, a high voltage (VSi) required for a word line corresponding to an external address selected in a program operation is limited to the downward GIBV value, and a high voltage is applied to the word line. Therefore, since the external high voltage VSi (program voltage) required for the program operation is limited to the downward GIBV value, it is not sufficiently transferred to the word line, resulting in a problem that the cell programming time becomes longer and the program speed is lowered. In addition, when the memory cell is not programmed by the down GIBV, the yield is lowered.

Therefore, an object of the present invention is to provide a row decoder of a nonvolatile semiconductor memory device for increasing a GIBV value of a transfer transistor for transferring a high voltage to a word line.

1 is a circuit diagram showing a circuit of a row decoder of a conventional nonvolatile semiconductor memory device;

2 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a first preferred embodiment of the present invention;

3 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a second preferred embodiment of the present invention;

DESCRIPTION OF REFERENCE NUMERALS

10: memory cell arrays 22k-20n, 32k-32n, 42k-42n: row decoder blocks

11: Switching pump

According to an aspect of the present invention, there is provided a semiconductor memory device including NAND cell units including a plurality of memory cells each having a control gate and a floating gate, A memory cell array connected in common to each word line corresponding to the memory cell array and a word line of the memory cell array and transmitting a predetermined voltage required in each operation mode to the selected word line, A row decoder of a nonvolatile semiconductor memory device having row decoder blocks, wherein each of the row decoder blocks includes: a conductive path charged with a predetermined voltage; An external address applied externally and a clock signal applied from the outside and having a predetermined frequency, the clock signal output in response to the external address of the first level, and the clock signal in response to the external address of the second level, An input unit for interrupting the output of the signal; A switch pump which receives a clock signal output from the input means and performs a voltage step-up operation in response to the clock signal to output a predetermined high voltage to the conductive path, and does not operate when the clock signal is not output from the input means; A first control signal and a second control signal applied from the external address, and a second control signal applied from the exterior, and in response to a high voltage being required in a predetermined word line of the memory cell array, Precharge means for precharging the semiconductor memory device to a predetermined voltage level; Wherein when the external address selected by the input means is inputted, the high voltage transmitted from the switch pump to the conductive path is received, and an external voltage applied from the outside is transmitted to the corresponding word line in response to the high voltage, And transmission means for receiving the predetermined voltage level charged in the conductive path when the selected external address is input and blocking the external voltage from being transferred to the word line in response thereto.

According to a preferred embodiment of the present invention, the pre-charging means includes a gate connected to a first control terminal to which the first control signal is applied, and a source-drain A first transistor having a channel connected thereto; A second transistor having a gate connected to a second power supply terminal to which a power supply voltage is applied from the outside, and a source-drain channel connected between the node 1 and the conductive path; And a third transistor having a gate connected to a second control terminal to which the second control signal is applied, and a source-drain channel connected between the second power supply terminal and the conductive path.

In a preferred embodiment of the device, the first transistor and the third transistor are n-channel-conduction-type MOS transistors.

In a preferred embodiment of the device, the second transistor is a depletion type MOS transistor.

According to another aspect of the present invention, there is provided a semiconductor memory device including NAND cell units each including a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit being common to the corresponding word lines And a plurality of row decoders corresponding to the word lines and a nonvolatile memory cell array having a plurality of row decoder blocks corresponding to the word lines, A row decoder of a semiconductor memory device, wherein each row decoder block includes: a first input terminal to which an external address is inputted from the outside; A second input terminal to which a clock signal having a predetermined frequency is input from the outside; A first control terminal to which a first control signal is externally applied; A first power supply terminal for receiving an external voltage applied to the word lines in each operation mode; A second power supply terminal to which a power supply voltage is applied from the outside; A second control terminal to which a second control signal is externally applied; A conductive path charged with a predetermined voltage; A NAND gate having its input terminal connected to the first input terminal and the second input terminal; A switch pump connected between the output terminal of the NAND gate and the conductive path; An NMOS transistor having a source-drain channel connected between the first input terminal and the node 1 and having a gate connected to the first control terminal; A depletion MOS transistor having a source-drain channel connected between the node 1 and the conductive path and a gate connected to the second power supply terminal; An NMOS transistor having a source-drain channel connected between the second power supply terminal and the conductive path, and a gate connected to the second control terminal; And an NMOS transistor having a source-drain channel connected between the first power supply terminal and a word line of the memory cell array.

According to another aspect of the present invention, there is provided a semiconductor memory device including NAND cell units including a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit being connected to corresponding word lines A memory cell array connected in common and a word line of the memory cell array, a plurality of row decoder blocks corresponding to each word line, A row decoder of a volatile semiconductor memory device, wherein each row decoder block includes: a first conductive path charged with a predetermined voltage; A second conductive path charged with a predetermined voltage; An external address applied externally and a clock signal applied from the outside and having a predetermined frequency, the clock signal output in response to the external address of the first level, and the clock signal in response to the external address of the second level, An input unit for interrupting the output of the signal; And a switch pump which is activated when the clock signal is not output from the input means, wherein the switch means is configured to output a high voltage to the first conductive path by performing a voltage step-up operation in response to the clock signal output from the input means, Wow; A first control signal, a second control signal, and a third control signal applied from the external address, and an external address selected or not selected when a high voltage is required in a predetermined word line of the memory cell array Precharge means for precharging the second conductive path to a predetermined voltage level before being input; Wherein when the external address selected by the input means is inputted, the high voltage transferred from the switch pump to the conductive path and the predetermined voltage level charged to the second conductive path are input to the external voltage, Line, and when a non-selected external address is inputted to the input means, a voltage of a second level from the conductive path and a predetermined voltage level charged to the second conductive path are inputted respectively, And a transmission means for blocking transmission to the line.

In a preferred embodiment of the device, the proc- essing means includes a first control terminal to which a source-drain channel is connected between a first input terminal to which the external address is applied and a node 2, A fourth transistor having a gate connected thereto; A fifth transistor having a source-drain channel connected between the node 2 and the first conductive path and a gate connected to a second power supply terminal to which a power supply voltage is applied; A sixth transistor having a source-drain channel connected between the first conduction path and the second conduction path and a gate connected to the first conduction path; A seventh transistor having a source-drain channel connected between the second power supply terminal and the second conductive path and a gate connected to the second control terminal; An eighth transistor having a source-drain channel connected between the second conductive path and the node 3 and having a gate connected to the second power supply terminal; And a ninth transistor having a source-drain channel connected between the node 3 and a third power terminal to which a ground voltage is applied, and a gate connected to a third control terminal to which the third control signal is applied.

In a preferred embodiment of the device, the fourth transistor and the fifth transistor are provided as a depletion MOS transistor.

In a preferred embodiment of the device, the sixth to ninth transistors are n-channel conduction type MOS transistors.

In a preferred embodiment of the device, the ninth transistor discharges the second conductive path in response to the third control signal after each operation mode is finished.

In a preferred embodiment of this device, the transfer means comprises: a first transfer transistor having a source-drain channel connected between a word line of the memory cell array and a node 4 and a gate connected to the first conduction path; And a second transfer transistor having a source-drain channel connected between the node 4 and the first power terminal, and a gate connected to the second conductive path.

In a preferred embodiment of the device, the first transfer transistor is an n-channel conduction type MOS transistor.

In a preferred embodiment of the apparatus, the second transfer transistor is provided with a discharge MOS transistor.

According to another aspect of the present invention, there is provided a semiconductor memory device including NAND cell units including a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit being connected to corresponding word lines A memory cell array connected in common and a word line of the memory cell array, a plurality of row decoder blocks corresponding to each word line, A row decoder of a volatile semiconductor memory device, wherein each row decoder block includes: a first input terminal to which an external address is inputted from the outside; A second input terminal to which a clock signal having a predetermined frequency is input from the outside; A first control terminal to which a first control signal is externally applied; A first power supply terminal for receiving an external voltage applied to the word lines in each operation mode; A second power supply terminal to which a power supply voltage is applied from the outside; A second control terminal to which a second control signal is externally applied; A third control terminal to which a third control signal is externally applied; A third power supply terminal to which a ground voltage is applied from the outside; A first conductive path charged with a predetermined voltage; A second conductive path charged with a predetermined voltage; A NAND gate having its input terminal connected to the first input terminal and the second input terminal; A switch pump connected between the output terminal of the NAND gate and the first conductive path; A depletion MOS transistor having a source-drain channel connected between the first input terminal and the node 2, and a gate connected to the first control terminal; A depletion MOS transistor having a source-drain channel connected between the node 2 and the first conductive path, and a gate connected to the second power supply terminal; An NMOS transistor having a source-drain channel connected between the first conduction path and the second conduction path and a gate connected to the first conduction path; An NMOS transistor having a source-drain channel connected between the second power supply terminal and the second conductive path, and a gate connected to the second control terminal; An NMOS transistor having a source-drain channel connected between the second conductive path and the node 3 and having a gate connected to the second power supply terminal; An NMOS transistor having a source-drain channel connected between the node 3 and the third power terminal, and a gate connected to the third control terminal; A first transfer transistor having a source-drain channel connected between the node 4 and a word line of the memory cell array, the NMOS transistor having a gate connected to the first conductive path; And a second transfer transistor having a source-drain channel connected between the first power supply terminal and the node 4 and a depletion MOS transistor having a gate connected to the second conduction path.

With such a device, it is possible to prevent the degradation of the program speed and the yield due to the leakage of the current by making the GIBV value of the transfer transistor high through the precharge means which lowers the transfer transistor.

Reference will now be made in detail to the preferred embodiments of the present invention with reference to FIGS. 2 to 3. FIG.

2 to 3, the same reference numerals are assigned to the constituent elements having the same functions as those of the constituent elements shown in Fig.

First Embodiment

2 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a first preferred embodiment of the present invention.

Referring to FIG. 2, the memory cell array 10 is provided with NAND cell units (UC) composed of a plurality of memory cells having control gates and floating gates, and the memory cells of the respective NAND cell units The control gates are connected in common to the respective word lines W / Lk - W / Ln corresponding thereto. The row decoder 30 selects each word line (W / Lk-W / Ln) of the memory cell array 10 and transfers the required voltage in each operation mode to the selected word line, / Lk - W / Ln). Each row decoder block 32 includes an input means 33 composed of a NAND gate G1, a precharging means 34 composed of NMOS transistors MN1 and MN2 and a depletion MOS transistor D5, A voltage pump means 11 and a transmission means 35 composed of an NMOS transistor T1. Each of the row decoder blocks 32k-32n includes an external address (k_address) applied from the outside, a clock signal 1o, first and second control signals , WE), and an external voltage (VSi).

The input means 33 receives the external address (k_address) applied from the outside and the clock signal 1o and outputs the clock signal 1o in response thereto. That is, when the external address k_address is a selected external address, a low level 'low level' is applied when the high level 'high level' is an unselected external address, and the clock signal 1o is a rectangular wave having a predetermined frequency . Therefore, when the signals (k_address, 1o) are applied to the NAND gate G1 of the input means 33, when the external address k_address selected first is applied, the clock signal 1o And the non-selected external address is applied, the clock signal 1o is not output from the NAND gate G1. The switch pump 11 performs a voltage pumping operation in response to the output of the clock signal 1o from the input means 33 to supply a high voltage (the external voltage VSi + the threshold voltage Vth of the NMOS transistor T1) L2, and when the clock signal 1o is not output from the input means 33, the voltage pumping operation is not performed.

When an operation not requiring a high voltage is performed on the word line, the NMOS transistor MN2 of the precharge means 34 is turned off and the NMOS transistor MN1 is turned on, Voltage is transferred to the gate of the transfer transistor. The precharge means 34 receives the external address (k_address) and the first control signal And the second control signal WE and precharges the conductive path L2 to a predetermined voltage level (Vcc-Vth2). A row decoder block 32k to which a selected external address (k_address) of each row decoder block 32 is inputted and a row decoder block 32n to which a non-selected external address (n_address) is input Let's assume. In the case of an operation requiring a high voltage, the conductive path L2 is precharged to a predetermined voltage level (Vcc + Vth2) before a selected external address (k_address) and a non-selected external address (n_address) are inputted. That is, the NMOS transistors MN1 and MN2 of the precharge means 34 are turned on by the first control signal And is turned on in response to the second control signal WE so that the conductive path L2 is precharged to the voltage level Vcc-Vth2 through the NMOS transistor MN2 and is supplied to the gate of the transfer transistor T1 corresponding thereto .

The row decoder block 32k receiving the selected external address k_address inputs a high voltage VSi + Vth (where VSi is an external voltage) to the conductive path L2 through the input means 33 and the switch pump 11 The NMOS transistor T1 of the transfer means 35 whose gate is connected to the conductive path L2 is turned on and the external voltage VSi applied from the outside Voltage) is transferred to the word line (W / Lk) corresponding to the selected external address (k_address). If the non-selected external address (n_address) is input, the input decoder 33 is disabled by the low-level external address (n_address) so that the switch pump 11 performs the voltage pumping operation . Thus, the voltage level Vcc-Vth2 is applied to the gate of the transfer transistor T1 corresponding to the conductive path L2 of the row decoder block 32n precharged at the voltage level (Vcc-Vth2) initially . Thus, the GIBV of the transfer transistor Tl of the row decoder block 32n can be raised to prevent current leakage of the external voltage VSi, thereby preventing the word line W / Lk (k) corresponding to the selected external address (k_address) So that a sufficient external voltage VSi can be delivered.

In other words, in an operation in which a high voltage is not required, the NMOS transistor MN1 of the precharge means 34 is turned on and the NMOS transistor MN2 is turned off, A voltage is applied to the gate of the transistor. On the other hand, in the case of transmitting a high voltage such as a program operation, the NMOS transistor MN1 of the precharging unit 34 is turned off and the NMOS transistor MN2 is turned on so that the voltage of each of the row decoder blocks 32k- And precharges each conductive path L2 to a predetermined voltage level (Vcc-Vth2). At this time, when the selected external address (k_address) is inputted to the row decoder block 32k, the switch pump 11 performs a voltage pumping operation through the input means 33 to generate a high voltage VSi + Vth, L2 to the gate of the transfer transistor T1. On the other hand, when the non-selected external address (n_address) is input to the row decoder block 32n, the switch pump 11 is not operated and the initial precharge voltage (Vcc-Vth2) Is applied to the gate of the cell transistor T1 to transfer the external voltage VSi necessary for the cell program to the word line.

Second Embodiment

3 is a circuit diagram showing a circuit of a row decoder of a nonvolatile semiconductor memory device according to a second preferred embodiment of the present invention.

Referring to FIG. 3, the memory cell array 10 is provided with NAND cell units (UC) composed of a plurality of memory cells each having a control gate and a floating gate, and the memory cells of the NAND cell unit The control gates are connected in common to the respective word lines W / Lk - W / Ln corresponding thereto. The row decoder 40 selects each word line W / Lk-W / Ln of the memory cell array and transfers the required voltage in each operation mode to the selected word line, And a plurality of row decoder blocks 42k-42n corresponding to W / Ln. Each of the row decoder blocks 42k to 42n includes an input means 43 composed of a NAND gate G1 and a precharge means 42 composed of NMOS transistors MN3 to MN6 and discharge MOS transistors D4 and D5, A switch pump 11 and a transmission means 45 composed of an NMOS transistor T1 and a depletion MOS transistor T2. Each of the row decoder blocks 42k to 42n receives an externally applied external address (k-address), a clock signal 1o and first to third control signals , WE, and REC, and an external voltage VSi.

The input means 43 receives the external address (k_address) applied from the outside and the clock signal 1o and outputs the clock signal 1o in response thereto. That is, when the external address k_address is a selected external address, a low level 'low level' is applied when the high level 'high level' is the non-selected external address n_address, and the clock signal 1o is a square wave . Therefore, when the signals (k_address, 1o) are applied to the NAND gate G1 of the input means 43, the clock signal 1o is outputted from the NAND gate G1 when the external address selected first is applied When the non-selected external address is applied, the clock signal 1o is not output from the NAND gate G1. The switch pump 11 performs a voltage pumping operation in response to the output of the clock signal 1o from the input means 43 to convert the high voltage (the external voltage VSi + the threshold voltage Vth of the NMOS transistor T1) Path L3 and does not perform the voltage pumping operation when the clock signal 1o is not output from the input means 43. [

The precharge means 44 includes an external address and a first control signal The second control signal WE and the third control signal REC and precharges the second conductive path L4 to a predetermined voltage level Vcc-Vth. In the case of an operation requiring high voltage, a row decoder block 42k to which a selected external address (k_address) of each row decoder block 42k to 42n is inputted and a row decoder block 42k to which a non-selected external address (n_address) (42n). In the case of an operation requiring a high voltage, the first and second conductive paths L3 and L4 are precharged to a predetermined voltage level before the selected external address (k_address) and the non-selected external address (n_address) are inputted. That is, the discharge MOS transistors D4 and D5 of the precharge unit 44 are turned on to charge the first conductive path L3 of each row decoder block 42k-42n to 0 volts, The NMOS transistors MN5 and MN6 are turned on to precharge the second conductive path L4 of each row decoder block 42k to 42n to a predetermined voltage level Vcc-Vth. Here, the third control signal REC applied to the gate of the NMOS transistor MN7 of the precharge means 44 is temporarily enabled to discharge the unnecessary voltage of the second conductive path L4, And remains in the turned-off state in the remaining operation period except for the case of FIG.

The row decoder block 42k receiving the selected external address k_address receives a high voltage VSi + Vth through the input path 43 and the switch pump 11 to the first conductive path L3 , The NMOS transistor T1 of the transmission means 45 whose gate is connected to the first conductive path L3 is turned on. The NMOS transistor MN6 having the gate connected to the first conductive path L3 is also turned on so that the high voltage VSi + Vth charged in the first conductive path L3 flows through the transistor MN6, A high voltage VSi having a voltage lowered by the voltage Vth is transferred to the second conductive path L4. The external voltage VSi applied from the outside through the depletion MOS transistor T2 of the transfer means 45 whose gate is connected to the second conductive path L4 and the NMOS transistor T1 corresponds thereto Word line (W / Lk).

The NAND gate G1 of the input unit 43 is disabled by the external address n_address in the row decoder block 42n to which the non-selected external address n_address is input, The first conductive path L3 is charged to the low level because the first conductive path 11 does not perform the voltage pumping operation. The NMOS transistor T1 of the transfer means 45 having the gate connected to the first conductive path L3 is turned off so that the external voltage VSi applied to the drain thereof is supplied to the corresponding word line W / Lt; RTI ID = 0.0 > Ln. ≪ / RTI > Then, the NMOS transistor MN6 of the precharge means 44 is turned off by the first conductive path L3 charged at the low level. The NMOS transistor MN3 of the precharge means 44 charges the second conduction path L4 to a predetermined voltage level Vcc-Vth, and the gate of the transfer means 45, The GIBV of the MOS transistor T2 can be raised and the leakage of the external voltage VSi can be prevented. Therefore, a sufficient external voltage (VSi) is transferred to the word line (W / Lk) corresponding to the selected external address (k_address).

In other words, at the time of the program operation, the NMOS transistor MN5 of the precharge means 44 is turned on, and the switch pump 11 is driven by the selected external address, and the gate is connected to the first conductive path L3. (VSi + Vth) is applied to the NMOS transistor T1 of the NMOS transistor 45. The NMOS transistor MN6 of the precharging means 44 is turned on by the high voltage (VSi + Vth) charged in the first conductive path L3 so that the voltage is lowered by the threshold voltage Vth thereof And the VSi value is transferred to the second conductive path L4. The drain of the NMOS transistor T2 is connected to the second conduction path L4 through the gate of the second conduction path L4 so that the external voltage VSi is not dropped. To the word line corresponding to the external voltage VSi. On the other hand, since the switch pump 11 is not driven by the non-selected external address, the first conductive path L3 is charged to the low level and the NMOS transistor T1 of the transfer means 45 having the gate connected thereto is supplied with 0 volt So that the voltage is not transferred to the word line. The GIBV can be raised by applying a predetermined voltage level (Vcc-Vth) to the gate of the depletion MOS transistor T2 of the transfer means 45 through the NMOS transistor MN3 of the precharge means 44 It was.

As described above, in order to prevent GIBV of the transfer transistor of the row decoder from being lowered, a predetermined voltage level is applied to the gate of the transfer transistor corresponding to the non-selected external address by using the precharge means. Thus, the GIBV of the transfer transistor corresponding to the non-selected external address can be increased. Thus, by applying the voltage of zero volts to the gate of the transfer transistor corresponding to the non-selected external address in the conventional manner at a predetermined voltage level through the precharge means, the program voltage is sufficiently supplied to the word line Line. Therefore, not only the program speed can be increased, but also the program yield can be prevented from being lowered.

Claims (14)

(UC) comprising a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit (UC) being connected to corresponding word lines (W / Lk (W / Lk - W / Ln) of the memory cell array 10 and the memory cell array 10 commonly connected to the word lines W / Ln (where k and n are positive integers) And a plurality of row decoder blocks (32k-32n) corresponding to the word lines (W / Lk-W / Ln) for transferring a predetermined voltage required in each operation mode to selected and selected word lines In a row decoder of a device, Each of the row decoder blocks 32k - A conductive path L2 charged with a predetermined voltage; Receives an external address k_address applied from the outside and a clock signal 1o applied from the outside and having a predetermined frequency and outputs the clock signal 1o in response to the external address k_address of the first level An input means (33) for blocking the output of said clock signal (1o) in response to said external address (k_address) of a second level; And a control unit for receiving the clock signal 1o output from the input unit 33 and outputting a predetermined high voltage to the conductive path L2 by performing a voltage step-up operation in response to the clock signal Io, A switch pump (11) which does not operate when the output signal (1o) is not output; The external address (k_address) and the externally applied first control signal ) And a second control signal WE in response to which a high voltage is required in a predetermined word line of the memory cell array 10 before the selected or unselected external address k_address is inputted, Precharge means (34) for precharging the power supply voltage to a predetermined voltage level; An external voltage VSi applied from the outside in response to the high voltage transferred from the switch pump 11 to the conductive path L2 when the external address k_address selected by the input means 33 is input, To the corresponding word line (W / Lk), and when the non-selected external address (k_address) is inputted to the input means (33), the predetermined voltage level charged in the conductive path (L2) And a transfer means (35) for blocking the transfer of the external voltage (VSi) to the word line (W / Ln) in response to the external voltage (VSi). The method according to claim 1, The precharge means (34) includes a first control signal A first transistor MN1 having a gate connected to the first control terminal 3 to which the first input terminal 1 is applied and a source-drain channel connected between the first input terminal 1 and the node 1 to which the external address k_address is applied, ; A second transistor (D3) having a gate connected to a second power supply terminal (5) to which a power supply voltage (Vcc) is applied from the outside and a source-drain channel connected between the node (1) and the conductive path (L2); A third transistor connected to a gate of the second control terminal 6 to which the second control signal WE is applied and to which a source-drain channel is connected between the second power supply terminal 5 and the conductive path L2 (MN2) of the nonvolatile semiconductor memory device. 3. The method of claim 2, Wherein the first transistor (MN1) and the third transistor (MN3) are n-channel conduction type MOS transistors. 3. The method of claim 2, And the second transistor (D3) is a depletion type MOS transistor. (UC) comprising a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit (UC) being connected to corresponding word lines (W / Lk (W / Lk - W / Ln) of the memory cell array 10 and the memory cell array 10 commonly connected to the word lines W / Ln (where k and n are positive integers) And a plurality of row decoder blocks (32k-32n) corresponding to the word lines (W / Lk-W / Ln) for transferring a predetermined voltage required in each operation mode to selected and selected word lines In a row decoder of a device, Each of the row decoder blocks 32k - A first input terminal (1) to which an external address (k_address) is inputted from the outside; A second input terminal 2 to which a clock signal 1o having a predetermined frequency from outside is input; A first control signal (" A first control terminal 3 to which the first control terminal 3 is applied; A first power supply terminal 4 receiving an external voltage VSi applied to the word lines W / Lk-W / Ln in each operation mode; A second power supply terminal 5 to which a power supply voltage Vcc is applied from the outside; A second control terminal 6 to which a second control signal WE is applied from the outside; A conductive path L2 charged with a predetermined voltage; A NAND gate G1 having its input terminal connected to the first input terminal 1 and the second input terminal 2; A switch pump 11 connected between the output terminal of the NAND gate G1 and the conductive path L2; An NMOS transistor MN1 having a source-drain channel connected between the first input terminal 1 and the node 1 and having a gate connected to the first control terminal 3; A depletion MOS transistor D3 having a source-drain channel connected between the node 1 and the conductive path L2 and a gate connected to the second power supply terminal 5; An NMOS transistor MN2 having a source-drain channel connected between the second power supply terminal 5 and the conductive path L2 and a gate connected to the second control terminal 6; And an NMOS transistor T1 having a source-drain channel connected between the first power supply terminal 4 and the word line W / Lk of the memory cell array 10. The nonvolatile semiconductor memory device according to claim 1, Row decoder. (UC) comprising a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit (UC) being connected to corresponding word lines (W / Lk (W / Lk - W / Ln) of the memory cell array 10 and the memory cell array 10 commonly connected to the word lines W / Ln (where k and n are positive integers) And a plurality of row decoder blocks (42k-42n) corresponding to the word lines (W / Lk-W / Ln) for transferring a predetermined voltage required in each operation mode to the selected word line In a row decoder of a device, Each of the row decoder blocks 42k - A first conductive path L3 charged with a predetermined voltage; A second conductive path L4 charged with a predetermined voltage; An external address (k_address) applied from the outside and a clock signal (1o) applied from the outside and having a predetermined frequency, and outputs the clock signal (1o) in response to the external address (k_address) An input means (43) for blocking output of the clock signal (1o) in response to the external address (k_address) of two levels; Wherein the input means receives the clock signal lO outputted from the input means and performs a voltage step-up operation in response to the clock signal to output a predetermined high voltage to the first conductive path L3, A switch pump 11 that does not operate when the clock signal 1o is not output; The external address (k_address) and the externally applied first control signal (K_address) when a high voltage is required in a predetermined word line of the memory cell array 10 in response to the first control signal WE, the second control signal WE, and the third control signal REC, A precharge means (44) for precharging the second conduction path (L4) to a predetermined voltage level before the voltage is input; Wherein when the external address (k_address) selected by the input means (33) is input, the high voltage transferred from the switch pump (11) to the conductive path (L3) and the high voltage supplied to the second conductive path (L4) Level to the word line W / Lk corresponding to the external voltage VSi in response to the level input, and when the non-selected external address (k_address) is input to the input means 33, L2 and a predetermined voltage level charged in the second conductive path L4, respectively, and blocks the external voltage VSi from being transferred to the word line W / Ln in response to the second level voltage and the predetermined voltage level charged to the second conductive path L4 And a transfer means (45). ≪ Desc / Clms Page number 13 > The method according to claim 6, A source-drain channel is connected between a first input terminal (1) to which the external address (k_address) is applied and a node (2), and the first control signal A fourth transistor D4 whose gate is connected to the first control terminal 3 to which the first control terminal 3 is applied; A fifth transistor (D5) having a source-drain channel connected between the node (2) and the first conductive path (L3) and a gate connected to the second power supply terminal (5); A sixth transistor MN6 having a source-drain channel connected between the first conductive path L3 and the second conductive path L4 and a gate connected to the first conductive path L3; A second control terminal 6 to which a source-drain channel is connected between the second power supply terminal 5 to which the power supply voltage Vcc is applied and the second conductive path L4 and to which the second control signal WE is applied, A seventh transistor MN3 having a gate connected to the gate of the seventh transistor MN3; An eighth transistor MN4 having a source-drain channel connected between the second conductive path L4 and the node 3 and a gate connected to the second power supply terminal 5; A source-drain channel is connected between the node 3 and a third power supply terminal 8 to which a ground voltage Vss is applied and a gate is connected to a third control terminal 7 to which the third control signal REC is applied And a ninth transistor (MN5). 8. The method of claim 7, Wherein the fourth transistor (D4) and the fifth transistor (D5) are provided as a depletion MOS transistor. 8. The method of claim 7, And the sixth to ninth transistors (MN6, MN3, MN4, MN5) are provided as n-channel conductivity type MOS transistors. 10. The method according to claim 7 or 9, And the ninth transistor MN5 discharges the second conductive path L4 in response to the third control signal REC after each operation mode is finished. The method according to claim 6, The transfer means 45 includes a first transfer transistor M3 having a source-drain channel connected between the word line W / Lk of the memory cell array 10 and the node 4 and a gate connected to the first conductive path L3, (T1); And a second transfer transistor (T2) having a source-drain channel connected between the node (4) and the first power supply terminal (1) and a gate connected to the second conductive path (L4) A row decoder of a memory device. 12. The method of claim 11, Wherein the first transfer transistor (T1) comprises an n-channel conduction type MOS transistor. 12. The method of claim 11, And the second transfer transistor (T2) is provided with a depletion MOS transistor. (UC) comprising a plurality of memory cells each having a control gate and a floating gate, the control gates of the memory cells of each NAND cell unit (UC) being connected to corresponding word lines (W / Lk (W / Lk - W / Ln) of the memory cell array 10 and the memory cell array 10 commonly connected to the word lines W / Ln (where k and n are positive integers) And a plurality of row decoder blocks (42k-42n) corresponding to the word lines (W / Lk-W / Ln) for transferring a predetermined voltage required in each operation mode to the selected word line In a row decoder of a device, Each of the row decoder blocks 42k - A first input terminal (1) to which an external address (k_address) is inputted from the outside; A second input terminal 2 to which a clock signal 1o having a predetermined frequency from outside is input; A first control signal (" A first control terminal 3 to which the first control terminal 3 is applied; A first power supply terminal 4 receiving an external voltage VSi applied to the word lines W / Lk-W / Ln in each operation mode; A second power supply terminal 5 to which a power supply voltage Vcc is applied from the outside; A second control terminal 6 to which a second control signal WE is applied from the outside; A third control signal 7 to which a third control signal REC is applied from the outside; A third power supply terminal 8 to which a ground voltage Vss is input from the outside; A first conductive path L3 charged with a predetermined voltage; A second conductive path L4 charged with a predetermined voltage; A NAND gate G1 having its input terminal connected to the first input terminal 1 and the second input terminal 2; A switch pump (11) connected between an output terminal of the NAND gate (G1) and the first conductive path (L3); A depletion MOS transistor D4 having a source-drain channel connected between the first input terminal 1 and the node 2 and having a gate connected to the first control terminal 3; A depletion MOS transistor D5 having a source-drain channel connected between the node 2 and the first conductive path L3 and a gate connected to the second power supply terminal 5; An NMOS transistor MN6 having a source-drain channel connected between the first conductive path L3 and the second conductive path L4 and having a gate connected to the first conductive path L3; An NMOS transistor MN3 having a source-drain channel connected between the second power supply terminal 5 and the second conductive path L4 and having a gate connected to the second control terminal 6; An NMOS transistor MN4 having a source-drain channel connected between the second conductive path L4 and the node 3 and having a gate connected to the second power supply terminal 5; An NMOS transistor MN5 having a source-drain channel connected between the node 3 and the third power terminal 8 and a gate connected to the third control terminal 7; A first transfer transistor T1 (NMOS transistor) having an NMOS transistor whose source-drain channel is connected between the node 4 and the word line W / Lk of the memory cell array 10 and whose gate is connected to the first conductive path L3, )Wow; A second transfer transistor T2 having a source-drain channel connected between the first power supply terminal 4 and the node 4 and a depletion MOS transistor having a gate connected to the second conductive path L4 And the row decoder of the nonvolatile semiconductor memory device.