KR100200696B1 - Dram device - Google Patents

Abstract

The present invention relates to Ta; It consists of at least one element or compound selected from the group consisting of metals selected from the group consisting of Ce, Zr, Y, Th, and Hf, oxides thereof, and mixtures thereof, wherein the amount of the elements or compounds The present invention relates to a diffusion barrier film composition for use in a D-RAM device which is 0.1-50 at% of the composition, and a semiconductor device comprising a diffusion barrier film made of the composition.

Description

Diffusion barrier composition comprising Ta and metal or oxide and D-RAM device comprising the diffusion barrier

1 is a basic structural diagram of a D-RAM device.

2 is a graph showing the sheet resistance of a conventional Ti _x N _y diffusion barrier film during heat treatment for 30 seconds under vacuum.

3a to 3c are graphs showing the surface resistance when the control specimen prepared in Example 1 and the specimen of the present invention were heat-treated for 30 minutes at each temperature under vacuum.

4 is a graph of the diffraction angle measured by X-ray diffraction after the specimen prepared in Example 1 was heated for 30 minutes at each temperature under vacuum.

FIG. 5 is a graph showing an Auger electron depth profile of the specimen prepared in Example 1 without heat treatment (A) or after heat treatment at 850 ° C. for 30 minutes under vacuum (B).

6 is a graph of the diffraction angle measured by X-ray diffraction after heat-treating the specimen prepared in Example 3 at each temperature under vacuum.

FIG. 7 is a graph showing the Auger electron depth profile of the specimen prepared in Example 3 without heat treatment (A) or after heat treatment at 850 ° C. for 30 minutes under vacuum (B).

8 is a graph measuring the sheet resistance after heat-treating the specimen prepared in Example 4 at each temperature in air for 30 minutes.

9 is a graph of the diffraction angle measured by X-ray diffraction after heat-treating the specimen prepared in Example 4 at each temperature under vacuum for 30 minutes.

a: CeO ₂ sputter power: 170 W, diffusion barrier thickness: 100 kW

b: CeO ₂ sputter power: 170 W, diffusion barrier thickness: 500 kW

c: CeO ₂ sputter power: 200 W, diffusion barrier thickness: 500 kPa

* Explanation of symbols for main parts of the drawings

1: substrate 2: word

3: bit line 4: insulating film

5: lower electrode 6: dielectric

7 upper electrode 8 wiring metal

The present invention relates to a diffusion barrier film used in a semiconductor device made of Ta, a metal or a metal oxide, and a D-RAM device having the diffusion barrier film.

The metal is preferably Ce, Zr, Y, Th or Hf, and the metal oxide is preferably MO _2-x (M: Ce, Zr, Y, Th or Hf, 0 ≦ x ≦ 1).

The configuration of the D-RAM basically has a cell structure of 1 transistor + 1 capacitor, so the integration can be increased. The basic structure of the D-RAM is well known and can be simply expressed as shown in FIG. 1. As the multilayer of the wiring connecting the low resistance wiring in parallel to the upper layer of the semiconductor element is further reduced in order to further lower the resistance by the wiring material. Two or more wiring metal wires may be laminated.

As the ultra-high integration of devices progressed, the cell area, which is a unit for storing information, was gradually reduced, and the area of the capacitor for storing information in the form of electric charges was restricted. Ways to widen were presented. However, even with this method, the dielectric constant becomes thinner to the extent that tunneling occurs and the dielectric constant is no longer changed to reach the limit of increasing the capacitor area. The choice of material is inevitably considered.

Currently, as ferroelectrics, PZT (PbZr _1-x T _x O ₃ ), PLZT (PbLa _1-x Zr _x TiO ₃ ), Ta ₂ O ₅ , and BST (Ba _1-x SrTiO ₃ ) have been widely studied.

On the other hand, in order to drive the ferroelectric layer to the element a, to be formed in the lower electrode, but has a relatively electrode characteristics are good RuO ₂ and Pt in recent years been actively studied as an electrode material, RuO ₂ is deposited condition without a bad leakage current characteristic Pt has good leakage current characteristics, but Pt diffuses into a silicon substrate, a silicide used as an insulating film, and polycrystalline silicon, whereby platinum and silicon react to form platinum-silicide. In addition, since these electrode materials pass oxygen contained in the dielectric thin film, when the dielectric thin film is formed on the lower electrode in a high temperature coral plasma atmosphere, the oxygen passed through the electrode diffuses to the polysilicon to form silicon oxide, thereby producing electricity in the electrode layer. There is a problem in that the resistance is increased, or the polysilicon diffuses toward the silicon atom electrode to form silicide, thereby degrading the reliability of the device.

Therefore, there is a demand for the development of a new diffusion barrier composition that can effectively prevent the diffusion of oxygen in the dielectric material, electrode material, and silicon in the substrate or insulating film, which reduces the reliability of the device.

At present, D-ram capacitor electrodes are used as diffusion barriers, such as TiN, TaN, and WN _1-x- filled polycrystalline nitride barriers filled with oxygen or nitrogen. However, these materials easily transfer oxygen and nitrogen even at low temperatures. It does not completely block the movement of silicon and oxygen, silicon oxide and platinum as an electrode material diffuses to form platinum-silicide.

On the other hand, the deterioration of the reliability of the device due to the interdiffusion of metal and silicon is another problem.

That is, as a final step of the semiconductor integrated circuit manufacturing process, a wiring process or a metallization process for electrically connecting the devices formed by the planar process is required. As the degree of integration of devices increases, the wiring process in the integrated circuit manufacturing process Has become a key for high yield and reliable device fabrication.

Recently, multilayer wiring of lower resistances has been achieved by connecting low-resistance wires in parallel to upper layers of semiconductor devices, and aluminum or aluminum-based materials are widely used as single-layer or single-layer wiring materials. Low melting point and low strength have a problem of reliability in long term device operation.

As a next-generation semiconductor wiring material, various metals are actively researched, and among them, copper is actively researched because of its advantages of low electrical resistance and higher resistance to electrical movement than aluminum. However, most metal wiring materials, in particular copper, move very quickly in most other metals and Si, and therefore diffuse into Si in the substrate by diffusion, resulting in disconnection of the device.

Therefore, in order to prevent rapid diffusion of the metal wiring material into silicon, it is necessary to provide a diffusion barrier.

Among the developed diffusion barriers, amorphous ternary diffusion barriers (amorphous-Ta-Si-N, W-Si-N, etc.) are known to be the best, but even when used as diffusion barriers for capacitor electrodes, the diffusion of oxygen or silicon is completely Since it is not hard and amorphous, there is a disadvantage in that crystallization occurs at high temperature and a long time heat treatment.

The diffusion barrier film must be free of chemical affinity with the metal used as the electrode material or wiring material, free from defects such as grain boundary formation up to high temperature, and have a high resistance to high solid solubility and high diffusion of metal and Si.

The present invention provides a diffusion barrier composition that can effectively block the interdiffusion of metals, oxygen or silicon, etc. used in the D-RAM device to solve this problem.

The anti-diffusion film composition of the present invention is composed of Ta and at least one material selected from the group consisting of Ce, Zr, Y, Th, Hf and oxides of these metals.

The amount of material is 0.1-50 at% based on the total diffusion barrier composition.

Since diffusion in a polycrystalline thin film such as a Ta thin film is mainly a diffusion through the grain boundary rather than a diffusion through the inside of the grain, in the present invention, the grain boundary of Ta is added by adding one or more of the above-mentioned metals or compounds thereof. It is possible to improve the diffusion prevention performance by blocking the formation of grain boundaries in the polycrystalline diffusion barrier by filling the.

In the present invention, by adding such metals or oxides thereof, the added metals or oxides serve to fill the grain boundaries of Ta, so that the metals constituting the electrode material, the metal wiring material or the other metal layer are Ta crystals of the diffusion barrier. Since diffusion can be prevented at the grain boundary, breakage of the diffusion barrier can be prevented.

Metals that can be used in the present invention to perform such a function have a high melting point, high thermal stability, and have a high tenon of segragation and a large atomic radius when used with Ta (FR deBoer). Et al., Cohesion in metals (Transition metal alloys), Vol. 1 (1988), North-Holland Press).

In order to satisfy these conditions, in particular, an element or compound selected from the group consisting of metals, oxides thereof and mixtures thereof selected from the group consisting of Ce, Zr, Y, Th and Hf is preferred.

The metal compound is represented by MO _2-x (M: Ce, Zr, Y, Th or Hf, 0 ≦ x ≦ 1), and one or more thereof may be used together.

The amount and composition of the element or compound may be changed by changing the deposition conditions, and as the amount of the element or compound increases, the diffusion preventing property may be excellent but may adversely affect the electrical properties. Consider the amount.

In the D-RAM device, the diffusion barrier film is used to prevent the diffusion of oxygen and silicon from the metal constituting the device, and is thus located at the boundary between the metal layer and the silicon-containing insulating film or the silicon-containing substrate in the device. The diffusion barrier composition of the present invention is also used in some or all of the general diffusion barrier positions irrespective of the semiconductor structure.

Referring to the basic D-RAM structure shown in FIG. 1 by way of example, the diffusion barrier layer is formed on the lower surface of the lower electrode 5, the word line 2 and the insulating film 4 or the substrate 1, for example, in a capacitor. It is used for the contact surface of the bit line 3 and the insulating film 4 or the substrate 1, the contact surface of the wiring metal 8 and the insulating layer, and when the wiring metal is multilayered, each wiring metal layer and the insulating layer and It is also used for the contact surface of.

FIG. 1 is merely for illustrative purposes. As described above, various changes can be made to the shape of a device, such as three-dimensional capacitor shape, in order to store more information. A barrier film is still needed and the present invention will be used in all types of D-RAM devices.

The present invention will be described in more detail through the following examples, but the scope of the present invention is not limited by the examples.

Example 1

For deposition, a radio frequency magnetron sputtering system, an ion beam-assisted deposition system, and an ion plating system were used.

Si (100) substrate was added to standard cleaning and BOE (buffered oxide echant) 7: 1 solution to remove the native oxide film, and then charged into a vacuum vessel so that 10 at% CeO _2-X (0≤x≤1) was added to Ta. It was deposited to a thickness of 500 mm 3 and deposited 1000 mm Cu without breaking the vacuum. Different experimental variables and deposition conditions for each deposition equipment are shown in Table 1 below.

Cu deposited specimens were maintained in a vacuum (1-5 x 10 ^-6 torr) state for 30 minutes in the temperature range of 500-900 ℃ and then cooled at room temperature.

As a control, using Ta as the diffusion barrier material, a Ta diffusion barrier film was deposited on the silicon 100 substrate in the same manner as above, and Cu was deposited thereon. Vacuum deposited Cu specimens (1-5 x 10) torr) was maintained for 30 minutes in the temperature range of 500-900 ℃ and then cooled to room temperature.

In order to examine the diffusion prevention characteristics of the specimen, the specimen was heat-treated at a temperature in the range of 500-850 ° C. for 30 minutes, and then sheet resistance using a 4-point probe (manufactured by Chang Min Co., Ltd.). Was measured.

As can be seen in FIG. 3, in the case of the Ta diffusion barrier, the sheet resistance was rapidly increased after heat treatment at 700 ° C. for 30 minutes, but the sheet diffusion resistance of the Ta diffusion barrier according to the present invention remained almost constant up to 850 ° C. FIG.

The diffraction angle was measured by X-ray diffraction on the unannealed specimen and the specimen heat-treated at 700-850 ° C (Fig. 4). Auger electron sepectrometry OJ electron depth profile was analyzed (FIG. 5). From the results, it can be seen that the diffusion barrier film according to the present invention did not occur in the interdiffusion of copper or silicon even after the heat treatment for 30 minutes at 850 ℃.

Example 2

As a control, TiN and TiN were respectively deposited on the silicon (100) substrate according to the method of Example 1 using a diffusion barrier material, and Cu was deposited thereon. Vacuum deposited Cu specimens (1-5 x 10) torr) was maintained for 30 seconds in the temperature range of 400-900 ℃ and then cooled to room temperature.

The sheet resistance of the prepared specimen was measured by the method described in Example 1. As can be seen in FIG. 2, in the case of the TiN and TiN diffusion barrier films, the diffusion barrier was damaged when heat-treated at 700 ° C. and 900 ° C. for 30 seconds, and the sheet resistance rapidly increased.

Example 3

A specimen was prepared in the same manner as in Example 1 except that the CeO sputter power was set to 200 W and the thickness of the Ta + CeO diffusion barrier was set to 300 mW. X-ray diffraction angles were measured on specimens not heat-treated and specimens heat-treated at 700-850 ° C. (FIG. 6), and the OJ electron profile was analyzed (FIG. 7).

Example 4

According to the conditions described in Example 1, the Si / TiSi wafer was subjected to the same method as in Example 1 except that the CeO sputter power was set to 200 W, 170 W and 170 W, respectively, and the thickness of the Ta + CeO diffusion barrier film was set to 500 kW, 500 kW and 300 kW. The specimen was prepared.

Platinum was deposited to a thickness of 500 kV at 35 kV and 230 mA using an electron beam evaporator on each specimen on which the diffusion barrier film was deposited.

Sheet resistance was measured by the method described in Example 1 on the specimen which was not heat-treated and the specimen heat-treated at 600-800 ° C. in air, and the results are shown in FIG. 8. In addition, the diffraction angle was measured by X-ray diffraction (Figs. 9a, 9b, and 9c). As can be seen from the results, the diffusion barrier film according to the present invention did not cause the diffusion of platinum or silicon even after the heat treatment. In addition, it can be seen that the formation of silicon oxide did not occur due to the diffusion of oxygen passed through the fermentation.

Claims (7)

With Ta; It is composed of one or more elements or compounds selected from the group consisting of metals selected from the group consisting of Ce, Zr, T, Th and Hf, oxides thereof and mixtures thereof, and the amount of the elements or compounds is total diffusion barrier An anti-diffusion film composition for use in D-RAM devices, wherein the composition is 0.1-50 at%. The diffusion barrier of claim 1, wherein the composition comprises a diffusion barrier layer on a lower surface of the lower electrode of the capacitor, a contact surface of a word line and an insulating film or a substrate, a contact surface of a bit line and an insulating film or a substrate, and a contact surface of a wiring metal and an insulating film in a D-RAM device. The composition used. The composition of claim 2, wherein the substrate or insulating film is a substrate or insulating film containing silicon. A D-RAM device having a diffusion barrier, wherein the diffusion barrier is formed of Ta; It consists of at least one element or compound selected from the group consisting of metals selected from the group consisting of Ce, Zr, Y, Th and Hf, oxides thereof and mixtures of oxides, the amount of said elements or compounds being total A D-RAM device comprising a composition which is 0.1-50 at% of the diffusion barrier composition. 5. The D-RAM device of claim 4, wherein the diffusion barrier layer is positioned below the lower electrode of the capacitor, on the contact surface between the word line and the insulating film or the substrate, the contact surface between the bit line and the insulating film or substrate, or the contact surface between the wiring metal and the insulating film. The D-RAM device according to claim 4, wherein the wiring metal has a multilayer structure with an insulating layer interposed therebetween. The D-RAM device according to claim 4, wherein the wiring metal is copper.