KR100187713B1 - Semiconductor memory module and manufacturing method of the same - Google Patents

Abstract

The present invention is designed on a wafer to be implemented as a SIMM memory module device by continuously increasing the unit capacity of the memory by utilizing the potted die checked in the electrical die sorting (EDS) step after wafer fabrication before wafer level port partial die marking. Manufacturing a wafer through various semiconductor manufacturing processes according to a circuit pattern; Checking the wafer manufactured in the step into a good die and a potial die through an electrical die sorting test; Marking the potial die through a wafer level test after the step; Obtaining a package by performing an assembly unit process using the semiconductor chip which has undergone the above steps; Assembling a single in-line memory module using the package obtained by the above steps; The present invention relates to a semiconductor memory module device and a manufacturing method using a potial die including mounting and reliability testing of the memory module device assembled in the above step. Therefore, it is usefully applied to various high amount of semiconductor memory module devices.

Description

Semiconductor memory module device using port partial die and manufacturing method thereof

1 is a process flowchart showing a manufacturing method of a memory module device using a semiconductor partial die in a process order;

2 shows a conventional semiconductor memory module device,

(a) is a block diagram,

(b) the module unit,

3 illustrates an embodiment of a semiconductor memory module device using a port partial die according to the present invention.

(a) is a block diagram,

(b) the module device.

4 illustrates another embodiment of a semiconductor memory module device using a pot partial die according to the present invention.

(a) is a block diagram,

(b) is a module device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory module device using a pot partial die and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor memory module device having a memory capacity of 4M or 16M. The present invention also relates to a semiconductor memory module device using a port partial die and a method for manufacturing the same, which can be assembled into a semiconductor memory module device using a port partial of 64M.

The conventional memory module device is based on 4M DRAMs of 4Mx8 and 4Mx9 (8 + 1 (parity bit check)). By mounting eight 4M DRAMs serially on a printed circuit board, they were able to interface data in parallel to achieve the expansion of memory capacity on the system.

In addition, the memory modules 16M × 8 (KMM5816000) and 16M × 9 (8 + 1 (for parity bit check)) are based on 16M DRAM, which is equipped with eight 16M DRAMs serially mounted on a printed circuit board in parallel between systems. By interfacing the data, the system's memory capacity was expanded.

1 is a process flowchart showing a manufacturing process of a memory module device using a semiconductor partial die, and FIG. 2 is a view showing a semiconductor memory module device of the prior art.

First, referring to FIG. 1, a manufacturing process of a conventional semiconductor memory module device may include manufacturing a wafer through various semiconductor manufacturing processes according to a circuit pattern designed on the wafer (S100); Marking the pot partial die through a wafer level test on the wafer manufactured in the step (S102); (S103) obtaining a package by performing an assembly unit process using the semiconductor chip which has passed the above steps; Assembling into a SIMM module using the package obtained by the above step (S104); In step S105, the memory module device assembled in the above step is mounted and tested for reliability.

Next, FIG. 2 (a) shows a block diagram of the concept of the conventional partial die application method of the conventional 4M × 8 DRAM SIMM module, and serially arranges DRAMs of 4M × 8 (U1 to U8). The write terminals W and the address terminals A0 to A10 of the respective units are serially connected so that they can be driven in parallel, CAS and RAS are connected in parallel, and each unit is connected to the individual data output terminals DQ0 to. DQ7).

In addition, FIG. 2 (b) shows the module device as shown in FIG. 2 (a). The upper part is a semiconductor memory module mounting area and the lower part is provided with a plurality of tab terminals for connection between systems.

However, since the conventional semiconductor memory module device using a partial die uses a partial die of BGD (Bin Grade Down) concept in the final mounting and testing stage after packaging is completed, as shown in FIG. There is a disadvantage that high capacity is difficult to realize.

Therefore, the present invention was invented to solve the technical disadvantage of high capacity in the above-described conventional semiconductor memory module device, and an object of the present invention is to perform electrical die sorting (EDS) before wafer level port partial die marking after wafer fabrication. The present invention provides a semiconductor memory module device using a high capacity port partial die and a method of manufacturing the same, which can be realized as a SIMM memory module device by continuously increasing the capacity of a single component of the memory by using the checked port partial die.

A semiconductor memory module manufacturing method using a potial die according to the present invention for achieving the above object comprises the steps of manufacturing a wafer through a variety of semiconductor manufacturing process according to the circuit pattern designed on the wafer; Checking the wafer manufactured in the step into a good die and a potial die through an electrical die sorting test; Marking the potial die through a wafer level test after the step; Performing an assembly unit process using the potted die which has undergone the above steps to obtain a package; Assembling a single in-line memory module using the package obtained by the above steps; There is a point consisting of the mounting and reliability test of the memory module device assembled in the above step.

In addition, in the semiconductor memory module device using the potial die according to the present invention, a wafer is manufactured through various semiconductor manufacturing processes according to a circuit pattern designed on the wafer, and the wafer is formed into a good die and a potial die through an electrical die sorting test. A plurality of packages manufactured by dividing and checking the markings, marking the potial dies through a wafer level test, and performing an assembly unit process using the potential dies; The packages are arranged in a serial unit, the printed circuit board having a signal line connected to each of the input and output terminals of the signal corresponding to each package and the clay, and a tab terminal connected to the signal line, respectively.

The port partial die of the semiconductor memory module device may be implemented as a 2-port partial or 4-port partial die to have a 16M capacity of 4M × 2 units and a 64M capacity of 16M × 2 units.

Hereinafter, a preferred embodiment of a semiconductor memory module device and a method of manufacturing the same using a potial die according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, first, a wafer is manufactured through various semiconductor manufacturing processes according to a circuit pattern designed on a wafer (S100).

Next, the wafer manufactured in step S100 is divided into a good die and a pot partial die through an electrical die sorting test (S101).

Here, the step S101 is a step of marking the 16M DRAM port partial die or the 64M DRAM port partial die through an EDS test. In order to implement a SIMM module having a capacity of 4M × 8 or 4M × 9, the 16M DRAM [( 4M × 4, 2-port partial die (4M × 2)] can be packaged and used in 4. Similarly, to implement a 16 × 8 (KMM581600) SIMM module, 64M DRAM ((16M × 4, 2-port partial) 4 dies 16M × 2. ”In this case, the marking is done by marking the pot partial die at one point and the pot rejection at two points (S102).

In other words, the 16M DRAM port partial die is EDS-tested and marks 4M × 2, which is fully driven by two of the four 4M × 4 ports of the 16M DRAM 4M × 4 for application to 4M × 4 and 4M × 9 SIMM module devices. S102).

In addition, for application to the SIMM module device of 16 × 8 (KMM5816000) using 16M DRAM, the EDS test marks 16M × 2 in which two ports of four ports of 64M DRAM 16 × 4 are fully driven (S102). .

Next, a step of obtaining a package by performing an assembly unit process using a port partial die, which has passed the step (S102) as in the prior art (S103), and assembling into a single in-line memory module using the package obtained by the step Step S104 and step S105 of mounting and reliability testing the memory module device assembled in the step are performed.

3 and 4 show embodiments of a semiconductor memory module device using a potial die according to the present invention, where (a) is a block diagram and (b) is a module device.

First, referring to FIG. 3, the conventional 4M × 8 memory module device at the left end is simply configured as 16M × 4 as at the right end.

That is, the semiconductor memory module device arranges packages having a capacity of 16M of 4M × 2 units in serial units, and then inputs / outputs (CAS, RAS) (W, A0 to A10) (DQ0 to AQ) of signals corresponding to each package. DQ7) is connected in common with the corresponding signal line, and the package is mounted on a printed printed circuit board having tab terminals of a common signal input / output terminal.

That is, four 16M (4Mx4) two-port partial chips for 4Mx2 operation are required, and four configurations of 4Mx2 operate at 4Mx8 for 4Mx2x4.

Therefore, the 16M having a two-port partial die instead of the 4M DRAM is operated by inputting eight CAS, RAS, W, and address signals and eight input / output data signals into each package using four 16M DRAMs.

Next, referring to FIG. 4, the conventional 16Mx8 memory module device at the left end is simply configured as 64Mx4 as at the right end.

That is, the semiconductor memory module device arranges a packaging unit composed of a two-port partial die unit having a 16M capacity of 16M × 2 units in a serial unit, and then inputs / outputs (CAS, RAS) (signals of signals corresponding to each packaging unit) ( W, A0 to A10 (DQ0 to DQ7) are connected in common with the corresponding signal lines, and the packaging unit is mounted on a printed printed circuit board having tab terminals of a common signal input / output terminal.

Four two port partial chips of 64M (16M × 4) for 16M × 2 operation are required, and four configurations of 16M × 2 operate at 16M × 8 for 16M × 2 × 4.

Therefore, the two-port partial (16M × 2) of the 64M DRAM (16M × 4) has the same CAS, RAS, W and address signals and eight input / output data respectively inputted in the same way as four 16M DRAMs. It is operated by interfacing the signal.

As described above, the semiconductor memory module device and its manufacturing method using the pot partial die according to the present invention have the following effects.

First, the proper utilization of the potial die obtained in the EDS test step enables the unit-level repair when configuring the SIMM module device, thereby increasing its utilization.

Second, as the capacity of semiconductor chip is expected to increase to 16M, 64M, 128M, and 256M, the number of partial dies of the port concept is expected to increase. The configuration of is possible.

Third, there is an advantage that the reliability of the memory module device can be improved by appropriately utilizing the portial die obtained in the EDS test step, rather than using a product packaged by the mounting and testing step.

Fourth, since the use of the potial die reduces the number of packages to be mounted on the printed circuit board in half compared to the conventional, there is an advantage in terms of space utilization of the printed circuit board compared to the conventional.

Claims (4)

Manufacturing a wafer through various semiconductor manufacturing processes according to a circuit pattern designed on the wafer; Checking the wafer manufactured in the step into a good die and a potial die through an electrical die sorting test; Marking the potial die through a wafer level test after the step; Performing an assembly unit process using the potted die which has undergone the above steps to obtain a package; Assembling a single in-line memory module using the package obtained by the above steps; A method of manufacturing a semiconductor memory module using a potial die / reject die, characterized in that the step of mounting and reliability test the memory module device assembled in the step. The wafer is manufactured through various semiconductor manufacturing processes according to a circuit pattern designed on the wafer, and the wafer is divided into good die and a partial die by an electrical die sorting test, and the wafer is marked by a wafer level test. A plurality of packages manufactured by performing an assembly unit process using the pot partial die; And a printed circuit board having the package arranged in serial units and having a signal line connected to the input / output terminals of the signal corresponding to each package in common, and a tab terminal connected to the signal line, respectively. A semiconductor memory module device using a port partial die. 3. The semiconductor memory module device according to claim 2, wherein the port partial die is a two port partial die having a capacity of 16M of 4M × 2 units. 3. The semiconductor memory module device according to claim 2, wherein the port partial die is a two port partial die having a capacity of 64M of 16M × 2 units.