KR100186529B1 - Image signal format transformation apparatus - Google Patents

Abstract

The present invention relates to an apparatus for converting an NTSC video signal output from various video devices into a PAL (Phase Alternation by Line) signal. In particular, after adjusting the resolution of the NTSC video synchronization signal using a dual port RAM A video signal format converter for converting a PAL video signal.

In the video signal conversion device of the present invention is a video signal format conversion device for converting an NTSC-type composite video signal through an analog decoder and detecting a synchronization signal and converting it into a PAL-type composite video signal. A RAM which converts the digital signal to a temporary buffer, a first counter that counts the pixel clocks and outputs them to a column address among the write addresses of the RAM, and a second counter that counts the vertical synchronization signals and outputs a row address among the RAM addresses. A write address generator including a PAL synchronous generator, a PAL synchronous generator for counting pixel clocks, and generating horizontal and vertical synchronous signals of the PAL method, and a reset of the PAL synchronous signal by generating a low pulse every predetermined period of the vertical synchronous signal; And an address for outputting the stored RGB signal from the RAM. A configured to comprise a read address generator for production is characterized.

Therefore, there is an advantage that NTSC-type various video screens can be used in PAL-type video devices even in countries that currently adopt the PAL system as a broadcasting standard.

Description

Video signal format converter

1 is a block diagram of a video signal conversion apparatus according to the present invention.

2 is a detailed block diagram of the write address generator according to the present invention.

3 is a detailed block diagram of a read address generator according to the present invention.

4 is a signal waveform diagram according to the present invention.

5 is a row address output timing diagram of a write address generator according to the present invention.

* Explanation of symbols for main parts of the drawings

11: analog decoder 12: sync signal separator

13 clock generator 14 AD converter

15: Dual Port RAM 16: Write Address Generator

17: read address generator 18: DA converter

19: Analog encoder 161,164,173,176,178: Counter part

163,175: AND gate 162,174: 2-minute cycle

171: PAL synchronization generating unit 172: reset unit

177: 6-minute cycle 179: subtractor

The present invention relates to an apparatus for converting an NTSC video signal output from various video devices into a PAL (Phase Alternation by Line) signal. In particular, after adjusting the resolution of the NTSC video synchronization signal using a dual port RAM A video signal format converter for converting a PAL video signal.

In general, the NTSC method converts an R (Red) .G (Green) .B (Blue) signal into one luminance signal (Y) and two chrominance signals (I, Q), and then converts the image band into two chrominance signals. Modulate to a subcarrier with a frequency of 3.5 MHz within

The composite signal obtained by adding the modulated chrominance signal and the luminance signal is modulated and transmitted by a carrier having a higher frequency.

On the other hand, the PAL method differs from the NTSC method in terms of color difference signals BY and RY, and the color subcarriers are modulated at right angles in two phases to be transmitted to the luminance signal. The signal obtained by modulating one color difference signal is inverted in polarity for each frequency. Is to transmit.

The receiver reproduces the color difference signal by the sum and difference of the color difference signals of two adjacent main waves.

In addition, the bandwidth is 5.5 MHz, the color carrier uses 4.43 MHz, and the scanning player is 625, whereas the NTSC scanning player is 525.

The PAL method is currently adopted as a broadcasting standard in China, while the use of various video devices using the NTSC method is increasing.

This is due to the impact of the rich variety of software produced in the culture that follows the method.

Therefore, in order to use various video screens of the NTSC system as a background screen of a karaoke device in a karaoke establishment, there is a problem that a NTSC system karaoke device and a TV must be simultaneously equipped.

However, NTSC karaoke devices do not meet the official broadcasting standards, and PAL video devices cannot be used.

The present invention has been made to solve the above problems, and provides a video signal format conversion apparatus that can use a variety of video screens adopting the NTSC method as a background screen even in a country that adopts the PAL method as a broadcast standard. Its purpose is to.

The video signal format conversion apparatus of the present invention for achieving the above object is an analog decoder for decoding a composite video signal of the NTSC system into an analog RGB signal, and a synchronization for separating horizontal and vertical synchronization signals from the composite video signal of the NTSC system A signal separator, a clock generator for generating a pixel clock by separating the horizontal synchronization signal input from the synchronization signal separator, an A / D converter for converting an analog RGB signal into a predetermined digital signal in synchronization with the pixel clock; A dual port RAM storing an RGB signal converted into the digital signal, a write address generator generating an address to which the digital RGB signal is written to the dual port RAM, and outputting an RGB signal stored from the dual port RAM. A read address generator for generating an address and the dual port RAM And a D / A converter for converting the output digital R.G.B signal into an analog signal, and an analog encoder for outputting the analog R.G.B signal by encoding the composite R.G.B signal into a composite video signal of the PAL method.

Hereinafter, a video signal conversion apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for converting a video signal according to the present invention, and an analog decoder 11 for decoding an NTSC composite video signal into an analog RGB signal, and a horizontal (HS ₁ ) from the NTSC composite video signal. And a clock generator 13 for generating a pixel clock PCLK by dividing the synchronization signal separator 12 separating the vertical synchronization signal VS ₁ and the horizontal synchronization signal HS ₁ input from the synchronization signal separator 12. And the first, second and third AD converters 14 for converting the RGB signals of the analog decoder 11 into digital 8-bit signals in synchronization with the PCLK, and the RGB signals converted into the digital signals. The first, second, and third dual port RAMs each having a size of 512 × 512 (width × length) as a frame buffer to be stored, and the digital RGB signal by using the horizontal and vertical synchronization signals and PCLK, , 2, 3 to generate an address to be written to the dual port RAM 15 Sites in line with the (Write), the address generator 16, and a vertical synchronizing signal and using the PCLK level of the PAL system and a vertical synchronizing signal (HS ₂₎ (VS _2), an output, and also the sync signal of the first, Read address generator 17 for generating an address to output a stored signal from the 2, 3 dual port RAM 15, and from the first, 2, 3 dual port RAM 15 in synchronization with PCLK. PAL using first, second, and third DA converters 18 for converting the digital RGB signals to analog RGB signals, and vertical and horizontal sync signals output from the read address generator 17 to the analog RGB signals. It consists of an analog encoder 19 for encoding and outputting a composite video signal of the scheme.

In this case, the write address generator 16 counts the PCLK as shown in FIG. 2 so that a 9-bit binary counter output corresponds to a low address among the write addresses of the first, second, and three dual port RAMs 15. A first counter unit 161 outputting to a column address, a two-dividing unit 162 for dividing the vertical synchronization signal VS ₁ by two, and a horizontal synchronization signal to clear the first counter unit 161. An AND gate 163 for ANDing and outputting the HS ₁ and a vertical synchronization signal divided by two, and writing a 9-bit binary count output of the 1, 2, and 3 dual port RAMs 15 by counting the horizontal synchronization signal. The second counter unit 164 outputs a row address corresponding to a high address among the addresses, and the binary count output is cleared while the output of the divider 162 is low.

Also, as shown in FIG. 3, the read address generator 17 includes a PAL sync generator 171 which counts PCLK to generate horizontal and vertical sync signals HS ₂ and VS ₂ of the PAL method, and 12 of the vertical sync signals. A reset unit 172 which resets the PAL sync generator 171 by making a low pulse once every cycle, and a 9-bit binary count output corresponding to a low address among the read addresses of the dual port RAM 15 by counting PCLK. 2 minutes of dividing the first counter unit 173 for outputting the column address and the vertical synchronization signal VS ₂ generated by the PAL synchronization generator 171, and generating a pulse at the poly edge of the divided signal. And gates for clearing the first counter unit 173 at a low period of the period 174, the horizontal synchronization signal HS ₂ of the PAL synchronization generator 171, and the output signal of the divider 174. 175 and while the output of the divider 174 is low And the horizontal synchronizing signal of the second counter 176 and the PAL sync generator 171, which counts the horizontal synchronizing signal (HS ₂₎ outputs a binary count of the 9 bits of the PAL sync generator 171 (HS ₂ 6 division 177 for outputting the clock by dividing 6), a third counter unit 178 for counting the output of the 6 division 177 and performing a 9-bit binary count output, and the second counter. The difference between the unit 176 and the third counter unit 178 is a subtractor 179 that outputs a row address corresponding to a high address among the read addresses of the first, second, and third dual port RAMs 15. It is composed.

In order to convert the NTSC video signal into PAL video signal in real time, the video signal converting apparatus of the present invention configured as described above decomposes the analog RGB decoder 11 into an analog RGB signal by synthesizing the NTSC video composite signal and synchronizing the signal signal. Reference numeral 12 separates the horizontal HS ₁ and the vertical synchronization signal VS ₁ from the NTSC composite video signal.

Then, the clock generator 13 generates the pixel clock PCLK by separating the horizontal synchronization signal input from the synchronization signal separator 12.

The PCLK is 512 times the horizontal synchronous signal period. That is, the number of pixels constituting one horizontal line is 512.

The first, second and third AD converters 14 convert the R.G.B signals of the analog decoder 11 into digital 8-bit signals in synchronization with the PCLK.

The first, second, and third dual port RAMs 15, which are frame buffers for storing the digital R.G.B signals, each have a size of 512 × 512 (width × length).

The address at which the digital RGB signal is to be written to the first, second and third dual port RAM 15 is generated by the write address generator 16 and outputs the stored signal from the first, second and third dual port RAM 15. The address is generated by the read address generator 17.

The write address generator 16 counts the PCLK in the first counter unit 161 to generate a 9-bit binary count output column corresponding to a row address among the write addresses of the first, second, and third dual port RAMs 15. The address is output, and the output of the horizontal synchronization signal HS ₁ and the divider 162 are input from the AND gate 163 to the clear terminal of the first counter unit 161.

The second counter unit 164 counts the horizontal synchronization signal HS ₁ separated by the synchronization signal separator 12 to output a 9-bit binary count output to the write address of the first, second, and third dual port RAMs 15. The binary count output is cleared while the output is sent to the row address corresponding to the middle high address and the output of the divider 162 is low.

The divider 16 divides the vertical synchronization signal VS ₁ (FIG. 4 (a)) in order to clear the first and second counters 161 and 164 every frame (two fields). A pulse is generated at the falling edge of the divided signal (FIG. 4B) and input to the clear terminal of the second counter unit 164 so that two high widths are equal to 512 horizontal synchronization signals.

In addition, the PAL sync generator 171 of the read address generator 17 counts PCLK to generate horizontal and vertical sync signals HS ₂ (VS ₂ ) of the PAL method, and the reset unit 172 is a vertical sync of NTSC. By receiving the signal VS ₁ and generating a low pulse (Fig. 4 (e)) once every 12 cycles of the vertical synchronization signal, the PAL synchronization generator 171 is reset to reset the horizontal and vertical synchronization signals HS ₂ of the PAL method. (VS ₂ ) By synchronizing with the vertical synchronization signal VS ₁ , write and read operations to the first, second, and third dual port RAMs 15 always have a constant timing relationship.

By counting the PCLK, the first counter unit 173 sends a 9-bit binary count output to a column address corresponding to a row address among the read addresses of the first, second, and third dual port RAMs 15. In order to clear the first counter unit 173, the horizontal synchronization signal HS ₂ generated by the PAL synchronization generator 171 and the vertical synchronization signal VS ₂ at the second divider 174 (FIG. 4 (d). The signal divided by 2) is ANDed at the AND gate 175, and is output to the clear terminal.

The divider 174 generates a pulse at the polling edge of the divided signal so that the two high widths are equal to 596 horizontal synchronization signals (FIG. 4 (c)), and the second counter unit 176 is configured to generate the pulse at the falling edge of the divided signal. The output of the divider 174 is cleared while it is low, and the horizontal synchronous signal is counted (FIG. 5 (a)) to output a 9-bit binary count output to the subtractor 179.

When the horizontal synchronization signal HS ₂ is divided into six divisions in the six-division period 177 and input as a clock by the third counter unit 178, the third counter 178 counts (bit 5) (9b). Sends the binary count output of to the subtractor 179.

Then, the subtractor 179 displays the difference (figure (c)) between the second counter part 176 and the third counter part 178 in the read addresses of the first, second, and third dual port RAMs 15. Export to the row address corresponding to the high address.

Here, the maximum value of the binary counter outputs of all the counter units is 511.

Therefore, the first, second, and third dual port RAMs 15 are written as the data of frame 1 increases from 0 to 511 of the write address during the first period of FIG. 4 (b). Similarly at the same time the written data is immediately output as the read address increases from 0 to 511.

Then, the sixth cycle of FIG. 4 (b) and the fifth cycle of FIG. 4 (c) are almost finished at the same time because they have similar frequencies.

Therefore, the data of frame 6 written in the first, second, and third dual port RAMs 15 begins to be rewritten into frame 7 of the signal b before being read into frame 6 of the signal C, so that the first , Among the frames output to the 2,3 dual port RAM 15, the frames 6, 12, 18, etc. (one for every six frames) are not output.

Meanwhile, the total number of lines recorded in the first, second, and third dual port RAMs 15 is 512, but since the total number of output lines is repeatedly outputted every six lines, 512/6 (≒ 85.3) is added. The result is 512 + 86 = 598.

The digital R.G.B signals output from the first, second and third dual port RAMs 15 are converted into analog R.G.B signals in synchronization with the PCLK by the first, second and third DA converters 18.

The converted analog R.G.B signal is converted into a PAL composite video signal using the synchronization signal obtained by the read address generator 17.

As described above, the apparatus for converting a video signal format of the present invention has an advantage that NTSC video screens can be used in a PAL video device even in a country currently adopting the PAL system as a broadcast standard.

Claims (1)

A video signal format conversion apparatus for converting an NTSC composite video signal into an analog decoder to detect RGB signals and converting a synchronization signal into a PAL composite video signal, wherein the RGB signal is converted into a digital signal and temporarily buffered. A write address generator including a RAM, a first counter that counts pixel clocks and outputs the column addresses among the write addresses of the RAM, a second counter that counts vertical synchronization signals and outputs row addresses among the RAM addresses; A PAL synchronous generator for counting pixel clocks to generate horizontal and vertical synchronous signals, and a reset unit for resetting the PAL synchronous signals by generating a low pulse every fixed period of the vertical synchronous signal. A read address generator that generates an address for outputting an RGB signal Video signal format conversion apparatus according to claim adapted to the box.