KR0185919B1 - 25/24 modulation method of sp/vcr data - Google Patents

Abstract

The present invention relates to a 25/24 demodulation method of SD-VCR data, wherein the most significant bit of 25-bit parallel data is removed, and the remaining 24-bit data is stored in 8-bit units using a demodulation clock divided into 8 serial clocks. As a result, the output of the error correction coding before the recording of the data is the same as the output, thereby facilitating the data processing during the reproduction of the SD-VCR data.

Description

25/24 demodulation method of SD-VCR data

1 is a block diagram of a data reproducing apparatus for explaining a 25/24 demodulation method of SD-VCR data according to the present invention;

2 is a morphology diagram of SD-VCR data before and after 25/24 demodulation and a waveform diagram of a clock according to the present invention.

* Explanation of symbols for main parts of the drawings

10: synchronization signal detector 20: clock generator

30: S / P converter 40: 25/24 demodulator

The present invention relates to a 25/24 demodulation method of SD-VCR data.

With the development of semiconductor technology, digital signal processing is possible not only for sound signals but also for wide bandwidth video signals. As the recording media and recording technologies are improved, the appearance of home VCRs by digital signal processing becomes possible.

Therefore, various manufacturers have made home digital VCRs with their own formats and technologies, and each manufacturer has negotiated a unified format compatible with each other. This is called a standard digital VCR (SD-VCR).

According to the format of the SD-VCR, error-correction coding (ECC) and channel modulation are performed to reduce the occurrence of errors before recording video data or audio signal data on the tape.

There are many ways of channel modulation developed so far, but SD-VCR uses 24/25 modulation.

Data that is error corrected coded is output by 1 byte (8 bits), and 24/25 modulation is three sets of 1 byte (8 bit) data that is error corrected coded, that is, 3 bytes (24 bits) of dataword ( One bit extra bit (EB) is inserted at each head of the dataword to convert the bit into 25 bits. The data of one bit to be inserted is selected as '0' or '1'. More specific information is disclosed in US Pat. No. 5,142,421, and the description is omitted here.

The modulated data is serially converted according to the format of the SD-VCR and recorded on the tape in the form of a bit stream. During playback, the serial data is converted into parallel data based on a synchronous signal. S / P conversion) and then playback through 25/24 demodulation.

First, the data recording format of SD-VCR and S / P conversion of data according to the SD-VCR format will be described.

The data of the audio signal or the video signal is recorded in the form of a bit stream in the sound signal sector and the video signal sector on the track, respectively, by a serial clock of 41.85 MHz after 24/25 modulation.

Each center starts with a pre-sync signal, followed by a synchronization signal at intervals of 750 bits behind the pre-sync signal. That is, a data sync block (Data Sync. Block) indicating the size (including the size of the sync signal) of the data from the sync signal to the next sync signal is 750 bits.

The present invention relates to the 25/24 demodulation of data conforming to the SD-VCR format as described above, in particular 8-bit parallel data in which the demodulated output is the same as the form of the output by error correction coding performed before the data is recorded. It is characterized by being.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data reproducing apparatus to which the 25/24 demodulation method of SD-VCR data of the present invention is applied.

The synchronization signal detection unit 10 detects a synchronization signal in the SD-VCR format of the serial data reproduced in the bit stream form by the serial clock.

The clock generation unit 20 uses a serial clock based on the synchronization signal detected by the synchronization signal detection unit 10, and a parallel clock for S / P conversion of data divided by 25 serial clocks and 8 serial divisions of the serial clocks. Each demodulated clock is generated.

According to the format of the SD-VCR, since the frequency of the serial clock is 45.85 MHz, the frequency of the parallel clock is 1.834 (= 45.85 / 25) MHz, and the frequency of the demodulation clock is 5.73125 (= 45.85 / 8) MHz.

The S / P converter 30 outputs the parallel data in 25-bit units in order to parallelize the serial data input using the parallel clock divided into 25 serial clocks.

The 25/24 demodulator 40 receives each parallel data in 25-bit units output from the S / P converter 30, and inverses 25/24 modulation to remove the most significant bit (MSB) of the input parallel data. Perform the process.

Meanwhile, in the present invention, the 25/24 demodulator 40 outputs the remaining 24 bits of data in the form of demodulated data in units of 8 bits using a demodulation clock divided by 8 serial clocks.

2 is a shape diagram of SD-VCR data before and after 25/24 demodulation and a waveform diagram of a clock according to the present invention.

As shown in FIG. 2, the parallel data converted in synchronization with the rising edge of the parallel clock in the S / P converter 30 is in units of 25 bits. / 25 Contains modulated data. The output data demodulated in synchronization with the rising edge of the clock for demodulation in the 25/24 demodulator 40 is in units of 8 bits. Here, the parallel clock distinguishes parallel data by dividing the serial clock into 25 divisions, and the demodulation clock outputs the demodulated data in 8-bit units after 25/24 demodulation as the serial data is divided into 8 divisions.

According to the 25/24 demodulation method of the SD-VCR data of the present invention by the operation described above, not only can 25/24 demodulation be performed, but also the output form of the demodulated data is set to 8 bits. The output of the error correction coding before the recording of the data is the same as that of the SD-VCR data, which facilitates data processing.

Claims (3)

(Correction) A method for reproducing SD-VCR data modulated and recorded according to a 24/25 modulation method, comprising: an S / P conversion step for converting serial data in an input bitstream form into parallel data in units of 25 bits; Performing 25/24 demodulation to remove the most significant bit from the converted parallel data in units of 25 bits; Generating a demodulation clock by dividing the serial clock corresponding to the serial data by eight; And outputting 24-bit demodulated data having the most significant bit removed by the 25/24 demodulation by 8 bits according to the generated clock for demodulation. (delete) (Correct) The method according to claim 1, wherein the serial clock is divided into eight and generated as a demodulation clock so that the output form of the demodulated data is the same as the output form of the error correction coding before being modulated at the time of writing. 25/24 demodulation method of SD-VCR data.