KR0183349B1 - Data interface controller between different processor modules - Google Patents

Abstract

The present invention relates to a data interface between heterogeneous processor modules, and more particularly, to a data interface controller between heterogeneous processor modules for efficiently interfacing and transferring data between heterogeneous processor modules.

In the related art, when data is transmitted and received between heterogeneous processor modules, the data transmission and reception speed of the processor module is different due to the different types of processor modules, so that the processor module of the transmitting side and the receiving side cannot efficiently transmit and receive data. have.

According to the present invention, when data is transmitted and received between heterogeneous processor modules having different data transmission / reception rates, the data can be efficiently interfaced and transmitted, thereby making it possible to reliably transmit and receive data between processor modules.

Description

Data interface controller between heterogeneous processor modules

The present invention relates to a data interface between heterogeneous processor modules, and more particularly, to a data interface controller between heterogeneous processor modules for efficiently interfacing and transferring data between heterogeneous processor modules.

In general, a system such as an electronic exchange includes a plurality of processor modules to perform a given function while transmitting and receiving data between corresponding processor modules.

In the related art, when data is transmitted and received between heterogeneous processor modules, the data transmission and reception speed of the processor module is different due to the different types of processor modules, so that the processor module of the transmitting side and the receiving side cannot efficiently transmit and receive data. have.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and when data is transmitted and received between heterogeneous processor modules having different data transmission / reception speeds, the data transmission and reception between the processor modules can be reliably transmitted by interfacing the data efficiently. The purpose is to provide a data interface controller between heterogeneous processor modules.

In order to achieve the above object, a feature of the present invention is a data interface controller between processor modules for interfacing data transmitted and received between processor modules, the input being applied from a first processor module by operating according to an output control signal. A first data bus controller which outputs data as write data and receives read data and outputs the output data to the first processor module; A first data write / read controller for generating an output control signal and outputting the output control signal to the first data bus controller according to an address applied from the first processor module, and generating and outputting a read selection address and a write selection address; A first data latch / read selection logic section for latching write data applied from the first data bus controller and selecting the read data according to an applied read selection address and outputting the read data as read data; A second data latch / read selection logic section for latching applied write data, selecting the read data according to a read select address applied from the first data write / read controller, and outputting the read data to the first data bus controller as read data; Operating in accordance with the applied output control signal, the input data applied from the second processor module is output as write data to the second data latch / read selection logic section, and read from the first data latch / read selection logic section. A second data bus controller which receives data and applies the output data to the second processor module side; According to the address applied from the second processor module, an output control signal is generated and output to the second data bus controller side, a read selection address is generated and output to the first data latch / read selection logic unit side, And a second data write / read controller for generating a write select address and outputting the write select address to the second data latch / read select logic section.

According to the present invention, when data is transmitted and received between heterogeneous processor modules having different data transmission / reception rates, the data can be efficiently interfaced and transmitted, thereby making it possible to reliably transmit and receive data between the processor modules.

1 is a block diagram showing a data interface controller between heterogeneous processor modules according to the present invention.

FIG. 2 is a configuration diagram of the first and second data bus controllers shown in FIG. 1; FIG.

FIG. 3 is a configuration diagram of the first and second data write / read controllers shown in FIG. 1; FIG.

FIG. 4 is a configuration diagram of the first and second data latch / read select logic sections shown in FIG. 1; FIG.

* Explanation of symbols for main parts of the drawings

10a, 10b: first and second data bus controllers

20a, 20b: first and second data write / read controllers

30a, 30b: first and second data latch / read select logic sections

BF1, BF2: first and second buffer sections

CL: Combination logic section RS0 to RSm-1: Register

DSL: Data selector SLEN: Select encoder

The data interface controller between the heterogeneous processor modules according to the present invention may include the first and second data bus controllers 10a and 10b, the first and second data write / read controllers 20a and 20b, and the first and second data bus controllers as shown in FIG. And first and second data latch / read select logic sections 30a and 30b. The first data bus controller 10a controls output from the first data write / read controller 20a to input / output of data D transmitted / received to the first processor module (not shown) via the data bus. In order to control according to the signal OTE, the data applied from the first processor module is output as the write data WD to the first data latch / read select logic section 30a, and the second data latch / read select logic section Read data RD is received from 30b, and output as read data D to the first processor module side. The first data write / read controller 20a generates an output control signal OTE according to the address ADD applied from the first processor module, outputs it to the first data bus controller 10a, and simultaneously selects a read. The address RSAD is generated and output to the second data latch / read select logic section 30b, and the write select address WSAD is generated and output to the first data latch / read select logic section 30a. The first data latch / read select logic section 30a also writes the write data WD applied from the first data bus controller 10a from the first data write / read controller 20a. (L) and selects according to the read select address (RSAD) applied from the second data write / read controller (20b) and outputs the read data (RD) to the second data bus controller (10b) side. The second data latch / read select logic section 30b transfers the write data WD applied from the second data bus controller 10b to the write select address WSAD from the second data write / read controller 20b. By latching accordingly, the data is selected according to the read selection address RSAD applied from the first data write / read controller 20a and output as read data RD to the first data bus controller 10a. On the other hand, the second data bus controller 10b receives input / output of data D transmitted / received to the second processor module (not shown) from the second data write / read controller 20b via the data bus. In accordance with the output control signal OTE, the data D applied from the second processor module is output as the write data WD to the second data latch / read select logic section 30b, and the first data latch is generated. The read data RD is received from the read select logic unit 30a and output as the data D to the second processor module. The second data write / read controller 20b generates an output control signal OTE according to the address ADD applied from the second processor module, outputs it to the second data bus controller 10b, and simultaneously selects a read. The address RSAD is generated and output to the first data latch / read select logic section 30a, and the write select address WSAD is generated and output to the second data latch / read select logic section 30b.

Meanwhile, each of the first and second data bus controllers 10a and 10b includes a first buffer unit BF1 and a second buffer unit BF2 as shown in FIG. 2. The first buffer unit BF1 may read the read data RD applied from the first or second data latch / read select logic units 30a and 30b to the first or second data write / read controller 20a, According to the output control signal OTE from 20b, the output is performed as output data D on the first or second processor module side, and the second buffer unit BF2 is applied from the first or second processor module. The first or second data latch / read selection logic section 30a, 30b according to the output control signal OTE from the first or second write / read controllers 20a, 20b. Is output as the write data WD.

Further, each of the first and second data write / read controllers 20a and 20b is constituted as a combination logic portion CL as shown in FIG. The combinational logic unit CL decodes an address ADD applied from the first or second processor module to generate and output a write select address WSAD, a read select address RSAD, and an output control signal OTE.

Each of the first and second data latch / read select logic sections 30a and 30b includes a plurality of registers RS0 to RSm-1, a data select section DSL, and a select encoder section as shown in FIG. It is made with (SLEN). The registers RS0 to RSm-1 latch the data, and write / write the write data WD applied from the first or second data bus controllers 10a and 10b to the first or second data write / read controllers. It latches in accordance with the write select addresses WSAD from (20a) and (20b), and applies them to the data selector DSL side as output data TMP. The selection encoder SLEN may read the read selection signal RSEL generated by encoding a read selection address RSAD applied from the first or second data write / read controllers 20a and 20b. Output to the DSL) side. The data selector DSL selects the output data TMP applied from the registers RS0 to RSm-1 in accordance with the read select signal RSEL from the select encoder section SLEN, so that the first or second data bus is selected. The data is output to the controllers 10a and 10b as read data RD.

The data interface controller of the present invention configured as described above operates as follows.

For example, when the first processor module transmits data to the second processor module side, the first processor module simultaneously outputs the data D to the first data bus controller 10a side to transmit the data. The address ADD is output to the first data write / read controller 20a. The combination logic unit CL of the first data write / read controller 20a outputs a high level as the address ADD is applied. The control signal OTE is output to the first data bus controller 10a side, the write select address WSAD is generated, and output to the first data latch / read select logic section 30a side. Accordingly, the second buffer section BF2 of the first data bus controller 10a receives the data D applied from the first processor module and receives the first data latch / read selection logic section 30a as the write data WD. The registers RS0 to RSm-1 of the first data latch / read select logic section 30 output the write data WD applied from the first data bus controller 10a to the first data write / The data is latched in accordance with the write select address WSAD from the read controller 20a and applied to the data selector DSL side as output data TMP.

At this time, if the address ADD from the second processor module is applied to the second data write / read controller 20b, the combination logic unit CL of the second data write / read controller 20b is the address ADD. Is applied, the low level output control signal OTE is output to the second data bus controller 10b side, and a read select address RSAD is generated to output to the first data latch / read select logic section 30a. do. Accordingly, the read select signal generated by encoding the read select address RSAD from the second data write / read controller 20b by the selection encoder section SLEN of the first data latch / read select logic section 30a. RSEL) is outputted to the data selector DSL side, so that the data selector DSL of the first data latch / read select logic unit 30a is applied from the registers RS0 to RSm-1. Is selected according to the read select signal RSEL from the select encoder section SLEN and output as read data RD to the second data bus controller 10b. In addition, the first buffer unit BF1 of the second data bus controller 10b receives the read data RD applied from the first data latch / read select logic unit 30a to the second data write / read controller 20b. The output signal D is output to the second processor module side in accordance with the low level output control signal OTE from.

That is, when the first processor module transmits data to the second processor module side, the transmission data output from the first processor module is the first data bus controller 10a and the first data latch / read selection logic unit 30a. And a second level of the second processor module via the second data bus controller 10b, wherein the first data write / read controller 20a is generated according to the address ADD from the first processor module. Outputs an output control signal OTE to the first data bus controller 10a to receive data from the first processor module by the first data bus controller 10a so as to receive the first data latch / read selection logic section. Outputting to the 30a side, and the first data latch / read select logic section 30a latches the data in accordance with the write select address WSED from the first data write / read controller 20a to generate the second data. day The second data bus controller 10b outputs to the second data bus controller 10b in accordance with the read select address RSAD from the write / read controller 20b, and the second data bus controller 10b outputs the second data write / read controller 20b. The data is output to the second processor module side according to the low level output control signal OTE applied from the second processor module.

In addition, when the second processor module transmits data to the first processor module side, the transmission data output from the second processor module includes the second data bus controller 10b and the second data latch / read selection logic unit 30b. ) And the first data bus controller 10a to the first processor module, where the second data write / read controller 20b is generated according to the address ADD from the second processor module. By outputting the output control signal OTE of the level to the second data bus controller 10b side, the second data bus controller 10b receives data from the second processor module to receive the second data latch / read selection logic. The second data latch / read select logic section 30b latches the data according to the write select address WSED from the second data write / read controller 20b. 1 day The first data bus controller 10a outputs the data to the first data bus controller 10a according to the read select address RSAD from the write / read controller 20a, and the first data bus controller 10a outputs the first data write / read controller 20a. The data is output to the first processor module side in accordance with the low level output control signal OTE applied from the controller.

Therefore, when data is transmitted and received between heterogeneous processor modules having different data input / output rates, the corresponding data may be efficiently interfaced.

As described above, in the present invention, when data is transmitted and received between heterogeneous processor modules having different data transmission and reception speeds, the data can be efficiently interfaced and transmitted, thereby making it possible to reliably transmit and receive data between the processor modules.

Claims (7)

In the data interface controller between the processor module for interfacing data transmitted and received between the processor module, A first data bus controller operating in accordance with an applied output control signal to output input data applied from a first processor module as write data, and receiving read data and outputting the output data to the first processor module side; A first data write / read controller for generating an output control signal and outputting the output control signal to the first data bus controller according to an address applied from the first processor module, and generating and outputting a read selection address and a write selection address; A first data latch / read selection logic section for latching write data applied from the first data bus controller and selecting the read data according to an applied read selection address and outputting the read data as read data; A second data latch / read selection logic section for latching applied write data, selecting the read data according to a read select address applied from the first data write / read controller, and outputting the read data to the first data bus controller as read data; Operating in accordance with the applied output control signal, the input data applied from the second processor module is output as write data to the second data latch / read selection logic section, and read from the first data latch / read selection logic section. A second data bus controller which receives data and applies the output data to the second processor module side; According to the address applied from the second processor module, an output control signal is generated and output to the second data bus controller side, a read selection address is generated and output to the first data latch / read selection logic unit side, And a second data write / read controller for generating a write select address and outputting the write select address to the second data latch / read select logic unit. The method of claim 1, The first data bus controller outputs read data applied from a second data latch / read selection logic unit as output data to the first processor module in accordance with an output control signal from the first data write / read controller. 1 buffer section; And a second buffer unit configured to output the input data applied from the first processor module to the first data latch / read select logic unit as write data according to an output control signal from the first data write / read controller. A data interface controller between heterogeneous processor modules. The method of claim 1, The second data bus controller outputs read data applied from the first data latch / read selection logic unit as output data to the second processor module in accordance with an output control signal from the second data write / read controller. 1 buffer section; And a second buffer unit configured to output the input data applied from the second processor module to the second data latch / read select logic unit as write data according to an output control signal from the second data write / read controller. A data interface controller between heterogeneous processor modules. The method of claim 1, The first data write / read controller may be a combination logic unit configured to decode an address applied from a first processor module to generate and output the write select address, read select address, and an output control signal. Data interface controller. The method of claim 1, The second data write / read controller may be a combination logic unit configured to decode an address applied from a second processor module to generate and output the write select address, read select address, and output control signal. Data interface controller. The method of claim 1, The first data latch / read selection logic section includes a plurality of registers for latching write data applied from a first data bus controller according to a write select address from the first data write / read controller and outputting the output data as output data; A selection encoder section for outputting a read selection signal generated by encoding a read selection address applied from the second data recording / reading controller; And a data selector for selecting output data applied from the register according to a read select signal from the select encoder and outputting the read data to the second data bus controller as read data. . The method of claim 1, The second data latch / read select logic section includes a plurality of registers for latching write data applied from a second data bus controller according to a write select address from the second data write / read controller and outputting the output data as output data; A selection encoder section for outputting a read selection signal generated by encoding a read selection address applied from the first data write / read controller; And a data selector for selecting output data applied from the register according to a read select signal from the select encoder and outputting the read data to the first data bus controller as read data. .