KR0179787B1 - Sense amp circuit of wide voltage region - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit in a wide voltage range. In the related art, when a pair of data signals are pulled down by receiving a low power supply voltage, the memory cells are affected and wrong data is stored in the cells. Malfunctions may occur, and the detection speed becomes very slow by the lowered voltage. Therefore, the present invention senses a low power supply voltage, and by increasing the size of the PMOS transistor for limiting the current at a low power supply voltage, thereby increasing the size of the PMOS transistor to detect a stable and fast data signal regardless of the voltage in a wide voltage range It can be amplified.

Description

Sense Amplifier Circuit in Wide Voltage Range

1 is a block diagram of a conventional sense amplifier circuit.

2 is a block diagram of a sense amplifier circuit of the present invention.

* Explanation of symbols for main parts of the drawings

10, 40: pull-down part 20, 50: current limiting part

30: low voltage detection unit SE: sense amplifier enable signal

LV: Low voltage detection signal DATA, DATAB: Data signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier, and more particularly, to a sense amplifier circuit capable of quickly detecting and amplifying data output from a memory cell at a wide range of power supply voltages regardless of whether the power supply voltage is high or low.

The conventional sense amplifier circuit includes a pull-down unit 10 which pulls down a pair of data signals DATAB and DATA according to the sense amplifier enable signal SE, as shown in FIG. A current limiter 20 for limiting the current by the power supply voltage VCC and the data signal DATA applied from the memory cell are input to the gate, and an NMOS drain connected to the current limiter 20. EnMOS transistor MN2 that receives a transistor MN1 and a data signal DATAB applied from a memory cell as a gate, and has a drain connected to the current limiter 20 to output amplified data SOUT. And the NMOS transistor MN3 having the sense amplifier enable signal SE input to the gate and grounded.

When the pull-down unit 10 receives the sense amplifier enable signal SE as a gate and receives the data signal DATA as a source, the pull-down unit 10 includes the NMOS transistor MN4 having the source grounded and the sense amplifier enable signal ( SE) is inputted to the gate, and the data signal DATA is inputted to the source, and the source is composed of the NMOS transistor MN5 grounded.

The current limiter 20 receives a power supply voltage VCC as a source, a drain transistor and a gate connected to the drain of the NMOS transistor MN1, and a power supply voltage VCC as a source. The gate is connected to the drain and the gate of the PMOS transistor MP1 in common, and the drain is configured to the PMOS transistor MP2 to be connected to the drain of the NMOS transistor MN2.

The operation of the conventional sense amplifier circuit configured as described above is as follows.

The sense amplifier circuit enabled by the high level sense amplifier enable signal SE detects and amplifies the difference between the data signals DATA and DATAB.

That is, a pair of data signals DATA and DATAB output from the memory cell are applied to the drains of the NMOS transistors MN4 and MN5, respectively, and at this time, a high level sense amplifier enable signal SE is applied. Is input to the NMOS transistors MN4 and MN5, the data signals DATA and DATAB are pulled down to a predetermined level lower than the power supply voltage VCC. In addition, the NMOS transistor MN3 is also turned on by the high level sense amplifier enable signal SE.

Subsequently, the level of the data signal DATA is higher than the level of the data signal DATAB, the level of the output data SOUT becomes high, and conversely, the level of the data signal DATA is lower than the level of the data signal DATAB. If it is, the level of output data SOUT goes low.

When the low level sense amplifier enable signal SE is input, the sense amplifier circuit is disabled and does not operate.

However, in the conventional sense amplifier circuit as described above, when a high level power supply voltage is input, a pair of data signals can be pulled down to obtain a fast amplification speed. However, a pair of data signals can be received by receiving a low level power supply voltage. Pulling down may affect the memory cell, causing wrong data to be stored in the cell, causing a malfunction of the memory device. In addition, the detection speed becomes very slow by the lowered voltage. That is, in order to operate stably even at a low level power supply voltage, the data signal cannot be pulled down, but instead, the size of the PMOS transistor receiving the power supply voltage must be increased so that the data signal can be amplified to the level of the power supply voltage. However, in this case, a large current flows at a high power supply voltage, which leads to a disadvantage in that the current consumption increases.

Accordingly, an object of the present invention is to pull down the data signal at a high power supply voltage, to reduce the current consumption without increasing the size of the sense amplifier circuit, and to suppress the pulldown and to limit the current at a low power supply voltage. By increasing the size, it is possible to provide a sense amplifier circuit capable of detecting and amplifying a data signal stably and rapidly regardless of voltage in a wide voltage range.

According to the present invention for achieving the above object, a low voltage sensing means for outputting a low voltage sensing signal, a low voltage sensing signal output from the low voltage sensing means and a sense amplifier enable for driving the sense amplifier According to the signal, the pull-down means for pulling down the level of the data signals applied from the memory cell to a predetermined level, and the low voltage detection signal output from the low voltage sensing means to both sides to receive the output current by the power supply voltage A current limiting means for limiting, a first NMOS transistor whose gate is input with one of the data signals, and whose drain is connected with one output terminal of the current limiting means; A second NMOS transistor connected to the other output terminal of the current limiting means The gate is input to the sense amplifier enable signal, the drain is commonly connected to the source of the first and second NMOS transistor, characterized in that the source is composed of a third NMOS transistor receiving the ground voltage. .

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 2, the sense amplifier circuit in the wide voltage range according to the present invention includes a low voltage sensing unit 30 for outputting a low voltage sensing signal LV according to a change in the power supply voltage VCC, and According to the low voltage detection signal LV output from the low voltage detection unit 30 and the sense amplifier enable signal SE for driving the sense amplifier, data signals DATA and DATAB applied from the memory cell. The pull-down unit 40 which pulls down the level of the signal to a predetermined level, and the low voltage detection signal LV output from the low voltage detection unit 30 are input to both sides, and output current by the power supply voltage VCC is received. The limiting current limiter 50, the gate is inputted with the data signal DATA, the drain is connected to one output terminal of the current limiter 50, the NMOS transistor MN1, and the gate is the data signal DATAB. ) Is inputted and the drain is connected to the other output terminal of the current limiting section 50 to increase An NMOS transistor MN2 for outputting the data SOUT, a gate thereof receives a sense amplifier enable signal SE, and a drain thereof is commonly connected to a source of the NMOS transistors MN1 and MN2, The source consists of an EnMOS transistor (MN3) that receives a ground voltage.

The pull-down unit 40 includes NMOS transistors MN4 and MN5 that receive data signals DATAB and DATA as drains and sense amplifier enable signals SE as gates, respectively, and the NMOS transistors thereof. The MN4 and MN5 are connected in series with each other, receive the low voltage detection signal LV as a gate, and are composed of NMOS transistors MN6 and MN7 as ground sources.

The current limiter 50 receives a power supply voltage VCC as a source, a PMOS transistor MP1 having a gate and a drain connected to the drain of the NMOS transistor MN1, and a power supply voltage VCC as a source. A low voltage signal outputted from the low voltage sensing unit 30, the PMOS transistor MP3 connected to the drain of the NMOS transistor MN1 and the source connected to the drain of the PMOS transistor MP3. VL) is input to the gate, the gate of which is connected to the drain of the NMOS transistor MN1, the PMOS transistor MP5 and the power supply voltage VCC as a source, and the gate and the drain of the NMOS transistor MN2 are input. PMOS transistor MP2 connected to the drain, PMOS transistor MP4 connected to the drain of the NMOS transistor MN2 by receiving a power supply voltage VCC as a source, and a source of the PMOS transistor Is connected to the drain of the transmitter MP4 and receives the low voltage signal LV output from the low voltage sensing unit 30 as a gate, and the gate is connected to the PMOS transistor MP6 connected to the drain of the NMOS transistor MN2. It is composed.

The operation and effects of the sense amplifier circuit in the wide voltage region according to the present invention configured as described above are as follows.

First, at a high power supply voltage, the low voltage detection unit 30 outputs a high level low voltage signal LV. Accordingly, as in the prior art, the pull-down unit 40 pulls down a pair of data signals DATA and DATAB, and applies data signals DATA and DATA which are applied to the gates of the NMOS transistors MN1 and MN2, respectively. According to the difference of DATAB, the amplified data SOUT is output to the outside.

Meanwhile, at a low power supply voltage, the low voltage detection unit 30 outputs a low level low voltage signal LV. Accordingly, the nMOS transistors MN6 and MN7 of the pull-down unit 40 are turned off so that the data signals DATA and DATAB are not pulled down, but the PMOS transistors MP5 and the current limiter 50 are pulled down. The MP6 is turned on so that a large amount of current due to the power supply voltage VCC flows to the drains of the enMOS transistors MN1 and MN2. Therefore, a fast amplification speed can be obtained even at a low power supply voltage.

As described above, the present invention pulls down the data signal at a high power supply voltage, thereby eliminating the need to increase the size of the sense amplifier circuit, thereby reducing the current consumption, and suppressing the pulldown affecting the memory cell at a low power supply voltage. Instead, by increasing the size of the PMOS transistor that limits the current, it is possible to obtain a high gain at the level of the power supply voltage and to amplify the data signal at a high speed. That is, the present invention can detect and amplify the data signal output from the memory cell stably and rapidly regardless of the voltage level in a wide voltage range.

Claims (3)

According to the change in the power supply voltage level, the low voltage sensing means for outputting the low voltage sensing signal, the low voltage sensing signal output from the low voltage sensing means, and the sense amplifier enable signal for driving the sense amplifier are applied from the memory cell. Pull-down means for pulling down the level of the data signals to a predetermined level, current-limiting means for receiving the low-voltage sensing signal output from the low-voltage sensing means on both sides, and limiting the output current by the power supply voltage; A first NMOS transistor connected to one output terminal of the current limiting means, a gate of which receives another data signal among the data signals, and a gate to receive another data signal among the data signals, and the drain to the current limiting signal; A second NMOS transistor for outputting the amplified signal connected to the other output terminal of the means, A sense amplifier in a wide voltage region configured to receive the sense amplifier enable signal, a drain of which is commonly connected to the sources of the first and second NMOS transistors, and a source of which is a third NMOS transistor which receives a ground voltage. Circuit. 2. The first and second NMOS transistors of claim 1, wherein the pull-down means receives a pair of data signals applied from a memory cell as drains and sense sense enable signals as gates, respectively. And a third and fourth NMOS transistors connected in series with a second NMOS transistor, receiving the low voltage sensing signal as a gate, and receiving ground voltages as a source, respectively. The method of claim 1, wherein the current limiting means is a first PMOS transistor having a power supply voltage as a source, the gate and the drain is connected to the drain of the first NMOS transistor, a power supply voltage as a source and the gate is the first A second PMOS transistor connected to the drain of the 1 N MOS transistor, a source connected to the drain of the second PMOS transistor, a low voltage signal output from the low voltage sensing means is input to the gate, and the gate is the first NMOS transistor A third PMOS transistor connected to the drain of the transistor, a fourth PMOS transistor connected to the drain of the second NMOS transistor, a gate and a drain of the second NMOS transistor, and a gate to the gate; A fifth PMOS transistor connected to the drain of the second NMOS transistor, and a source of the fifth PMOS transistor Connected to the lane and receive input for a low-voltage signal output from the low-voltage detection means to a gate wherein the gate of the sense amplifier in a broad voltage region consisting of the sixth PMOS transistor connected to the drain of the MOS transistor 2 en circuit.