KR0179760B1 - Output data check circuit of programmable logic controller - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output data check circuit of a programmable logic controller. In the related art, a programmable logic controller (PLC) is used in an industrial field, and data destruction is easily caused by noise from invading from the outside. While the memory READ and WRITE of the internal memory have high reliability, there is a problem that the CPI and the special card are vulnerable to external noise when transmitting and receiving data.

Therefore, the present invention uses a checksum circuit to quickly detect a data error when a large amount of data is exchanged between a CPI and a special card so as not to perform transmission and reception when an error occurs and to perform transmission and reception when the error does not occur. To improve the efficiency of the transmission.

Description

Output data check circuit of programmable logic controller

1 is a block diagram showing mounting of various cards of a general programmable logic controller (PLC).

2 is an output data check circuit diagram of a conventional programmable logic controller.

3 is an explanatory diagram showing a data output form in FIG.

4 is a process diagram showing the checksum operation of CFIU and a special card.

5 is an output data check circuit diagram of the programmable logic controller of the present invention.

6 is a detail of the checksum circuit in FIG.

7 is another configuration diagram of the checksum circuit in FIG.

8 is a write operation process of the common RAM data according to FIG.

FIG. 9 is a signal waveform diagram when the write signal is used as the second latch signal in FIG.

FIG. 10 is a signal waveform diagram when the selection signal is used as the second latch signal in FIG.

* Explanation of symbols for main parts of the drawings

10: CPI 20: Shared RAM

30: special card processor 40: checksum circuit

41: first latch 42: adder

43: second latch 44: buffer

45: Oagate

The present invention relates to an output data check circuit of a programmable logic controller (PLC). In particular, when a large amount of data is exchanged with a special card, the output of the programmable logic controller can quickly detect data errors and improve the efficiency of data transfer. It relates to a data check circuit.

The general configuration of the programmable logic controller is as shown in Fig. 1, in which CPI (101) is mounted, general digital input / output (I / O) cards (102, 103, 106, 107) are mounted, and special cards (104, 105, 108, 109) are mounted. It is showing the status.

As shown in FIG. 2, the configuration for checking output data between the CPI and the special card in the programmable logic controller equipped with the card as shown in FIG. 2 is a checksum operation for exchanging data with the special card. And a special card for performing a checksum operation on the data transmitted from the CPI 201 and transmitting the result data obtained by performing the operation to the CPI 201. The common memory 202 is configured to exchange data between the processor 203 and the CPU 201 and the special card processor 203.

The conventional technology configured as described above will be described with reference to the operation flowchart of FIG. 4.

First, referring to the operation of CPI according to (a) of FIG. 4, when CPI 201 tries to write data to the common RAM 202, it first addresses through the ADD BUS and assigns the address to the designated address. After clearing the corresponding A buffer, add '0' data to the value of A buffer (A).

The data '0' is then written to the common RAM 202.

Thereafter, data '1' corresponding to the designated address is added to A and output again to the common RAM 202.

As shown in FIG. 3, the checksum data obtained by adding up the data designated for each address and the designated data is sequentially written to the common RAM 202. FIG.

After all data is output, the result of the checksum from the special card processor 203 is waited for.

Here, the special card processor refers to a microprocessor having a function capable of controlling these various controllers because the controllers controlled by the CPI of the programmable logic controller (PLC) have a wide variety of functions.

At this time, the special card processor 203 reads data from the common RAM 202, adds all the data, and stores the result in the B buffer of the common RAM 202. ) And compare it to the data stored in the B buffer.

The result of the comparison is notified to the CPI 201.

Therefore, the CPI 201 enters the next execution if the comparison result is notified from the special card processor 203, that is, checksum OK, and retries from the beginning if it is not the checksum OK.

The operation of the special card processor 203 is similar to the operation of the CPI 201, and after clearing the B buffer, the C 202 reads the data written from the CRAM 201 to the common RAM 202 and sequentially adds the data to the final data. The sum of the checksum results and the checksum transmitted from the CPI 201 is added, and if the two results are the same, a checksum OK signal is output to the CUI 201, and an error signal is output.

As described above, the CPI and the special card of the programmable logic controller transmit and receive data.

However, in the prior art as described above, since the programmable logic controller (PLC) is used in the industrial field, data destruction occurs easily due to noise from invading from the outside, and in particular, the read of the memory inside the special card or CPI. ), While the WRITE is highly reliable, there is a problem that the CPI and the special card are vulnerable to external noise when transmitting and receiving data.

It executes a checksum to compensate for the above weakness, which writes the checksum result in the common RAM and reads it from the special card, and until the check is completed, CPI cannot send the next data and must wait. When equipped with a lot of problems that become very inefficient.

Accordingly, an object of the present invention for solving the conventional problems as described above is to reduce the waiting time according to the data output when a large amount of data is transmitted to the special card or when a plurality of special cards are mounted to reduce the data output more efficiently It provides an output data check circuit of a programmable logic controller that makes it possible.

The output data check circuit configuration of the programmable logic controller of the present invention for achieving the above object, as shown in Figure 5, outputs a control signal to send and receive data with a special card and perform the task according to the result of the data transmitted and received A CPI oil 10 to perform, a special card processor 30 having a function of exchanging data with the CPI 10 to control various controlled devices, between the CPI 10 and the special card processor 30 And a checksum circuit 40 for detecting a data error during data transmission and reception between the CPU 10 and the special card processor 30.

As shown in FIG. 6, the checksum circuit includes a first latch 41 for latching data or outputting the latched data by the clear signal and the write signal WR; An adder 42 for adding the output of the first latch 41 and the second latch output, and a second latching and padding data added through the adder 42 to the input of the adder 42. The buffer 44 receives a result of the latch 43, the second latch 43, and transmits the result of the second latch 43 to the CPI, and a signal formed by combining the selection signal and the read signal received from the CPI. It consists of an oragate 45 which controls an operation.

When described in detail with respect to the operation and effect of the present invention configured as described above.

When data is output from the CPI 10 through the data bus, the data is input to the common RAM 20 and the checksum circuit 40, respectively.

Then, the special card processor 30 reads data from the common RAM 20 through the data bus, sums the read data, and stores the data again in the common RAM 20.

In this case, the checksum circuit 40 will be described with reference to FIG.

When the write signal WR is output from the CPI 10, the first latch 41 is inputted to the clock terminal CK thereof to latch data transmitted from the CPI 10 through the data bus, and the latched data. (A) is output to the adder 42.

Then, the adder 42 receives the output data of the first latch 41 and the output data B of the second latch 43 by adding them back and outputs the added data to the second latch 43.

Accordingly, the second latch 43 latches the result data added by the adder 42 by the second latch signal transmitted from the CPI.

When the second latch 43 outputs the latched data to the buffer 44, the CPI 10 outputs all data and compares the value obtained by adding the output data with the value read from the buffer 44. If there is a match, the write operation is completed. If there is a mismatch, the retry is performed from the beginning.

Instead of the adder 42 and the second latch 43, an adder having a clear terminal shown in FIG. 7 may be used.

Referring to FIG. 8 again for the process as described above, CFI 10 first clears the checksum buffer A, and then clears the first latch 41 and the second latch 43. Leave data A and data B '0'.

Thereafter, CPI 10 adds output data '0' to the checksum buffer A, writes the data '0' to the common RAM 20, and outputs data to the first latch 41. Latch it.

The latched data A is added with the data B output from the second latch 43 by the adder 42 and taken as result data.

At this time, when the selection signal is used as the second latch signal as shown in FIG. 10, the output signal is output to the second latch 43 simultaneously with the data output. As shown in FIG. 9, when the write signal is used as shown in FIG. Is output, the operation result data is latched in the second latch 43.

Therefore, when using the write signal, the last data must be written and one more meaningless data is output. The checksum result is latched to the second latch 43.

Next, the output data '1' is added to the checksum buffer A and the data '1' is output to the common RAM 20.

It is output to the common RAM 20 and latched to the first latch 41 and the previous checksum data B and the data A are added and output as a result.

In this way, when data '0' to 'n' is outputted, the checksum data (B) becomes data '0' + data '1' + data '2' +... … … + The result of data 'n' is preserved.

Then, CPI 10 outputs all data and reads the checksum data B output through the second latch 43 through the buffer 44 and compares the data added through the internal checksum buffer A. FIG. If the comparison result is the same, the write operation is completed and if it is different, it is retried from the beginning.

As described above, when CPI 10 writes data to the common RAM 20 and simultaneously outputs the data to the checksum circuit 40, the CSI 10 is latched to the checksum circuit 40 and added to the previous checksum data, and the result is added. Checksum data is outputted, and all data are output from the CPI 10. The checksum data read from the checksum is read from the checksum circuit 40 and compared with the data added in the CPI 10. Since this is an error, retry again and repeat the above operation.

As described in detail above, the present invention has an effect of increasing the efficiency of data transmission by quickly detecting a data error by using a checksum circuit when sending and receiving a large amount of data.

Claims (3)

A programmable logic controller for controlling a special card processor having various special functions through a common RAM through which data is transmitted / received by CPI, wherein the CPI is output from the CPI when the special card processor exchanges a large amount of data. And a checksum circuit which adds the data to be written, compares the added checksum data with the addition data added in the CPI, terminates the write operation if it is equal, and retries if not equal. Output data check circuit of the controller. The method of claim 1, wherein the checksum circuit adds a first latch for latching or outputting the latched data by the clear signal and the write signal, the output of the first latch, and the second latch output; And an adder for outputting the added checksum data, a second latch for latching the checksum data through the adder, padding and passing the result to the input of the adder, and a buffer receiving the result of the second latch and transmitting the result to the CPI. And an ore gate configured to control the operation of the buffer using a signal made by combining a selection signal and a read signal received from the CPI. The checksum circuit of claim 1, wherein the checksum circuit acquires checksum data by adding a first latch for latching data transmitted from the CPI and a data output from the first latch and its output data fed back according to a clear signal. And an adder and a buffer for transmitting the output of the adder to the CPI.