KR0178849B1 - Fdd control device of personal computer - Google Patents

Abstract

The present invention relates to a floppy disk drive (FDD) control apparatus for a personal computer.

Since the conventional FDD control circuit controls the 3 mode FDD using the keyboard controller, some of the output pins of the keyboard controller should be allocated for the 3 mode FDD control. Therefore, there is a problem in that the corresponding output pin of the keyboard controller cannot be used for other purposes, so that various other functions can not be added to the keyboard controller, and the use of the keyboard controller may be slightly different from system to system. There was a problem that could not be used.

According to the present invention, the 3-mode FDD is controlled using PAL without using a keyboard controller. Therefore, the output pin of the keyboard controller can be used for other purposes as well as it can be applied to all systems without having to assign an output pin for FDD control to the keyboard controller. have.

Description

FDDI controller of personal computer

1 is a block diagram of an FDD controller of a conventional personal computer.

2 is a block diagram of an FDD control apparatus for a personal computer according to the present invention.

3 shows the PAL of FIG.

4 is a diagram showing a detailed configuration of a PAL.

* Explanation of symbols for main parts of the drawings

1: Keyboard Controller 2: Input / Output Controller

3,4 AND gate 5: FDD connector

10: PAL 20: FDD Connector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floppy disk drive (FDD) control apparatus for a personal computer. In particular, the FDD control of a personal computer enables the personal computer to read information recorded in 720kbyte, 1.2Mbyte, and 1.44Mbyte types on a floppy disk in a compatible manner. Relates to a device.

Currently, 3.5-inch floppy diskettes used in personal computers have 2HD and 2DD types, 2HD floppy diskettes are used in 1.44Mbyte and 1.2Mbyte types, and 2DD floppy diskettes have one kind of 720kbyte type.

In addition, IBM-compatible personal computers can read 720kbyte and 1.44Mbyte types of information recorded on 3.5-inch floppy diskettes through their own FDD, while NEC-compatible personal computers use 3.5-inch FDD. The information recorded in the 1.2Mbyte type on the floppy disk can be read. IBM-compatible and NEC-compatible personal computers record and read information in different formats when recording / reading information on 3.5-inch floppy diskettes, and at different rotational speeds for driving 3.5-inch FDD. It is running. Therefore, 1.44Mbyte type information of 3.5-inch floppy diskette used by IBM compatible personal computer cannot be read by NEC compatible personal computer and 1.2 of 3.5-inch floppy diskette used by NEC compatible personal computer. Mbyte type information cannot be read by IBM compatible personal computers.

Accordingly, there is a problem in that software written on a 3.5-inch floppy diskette cannot be used interchangeably between an IBM-compatible personal computer and a NEC-compatible personal computer.

To solve this problem, a three-mode FDD has been developed that can record / read information on both 2HD and 2DD floppy diskettes.

In order to control such a three-mode FDD, the FDD controller shown in FIG. 1 has been proposed. The FDD control device of FIG. 1 includes a keyboard controller 1, an input / output controller 2, an AND gate 3, 4, and a connector 5.

The keyboard controller 1 outputs the mode signals MODE A and MODE B for selecting 2HD floppy diskettes of the 2HD type (1.44 Mbyte, 1.2 Mbyte) to the AND gates 3 and 4, and the input / output controller 2 ) Outputs a write density signal DENSEL for selecting a 2DD type (720 kbyte) floppy diskette to the AND gates 3 and 4. The AND gates 3 and 4 are control signals MODESEL formed by ANDing the mode signals MODE A and MODE B from the keyboard controller 1 and the recording density signal DENSEL from the I / O controller 2. By outputting A, MODESEL B) to the 3 mode FDD side through the connector 5, the 3 mode FDD is driven corresponding to each floppy diskette type, and each control signal (MODESEL A, MODESEL B) is connected to the different 3 mode FDD. As supplied, two three-mode FDDs can be controlled.

Since the conventional FDD control circuit controls the 3 mode FDD using the keyboard controller 1, some of the output pins of the keyboard controller 1 need to be allocated for the 3 mode FDD control. Therefore, there is a problem in that the corresponding output pin of the keyboard controller 1 cannot be used for other purposes, so that various other functions cannot be added to the keyboard controller 1. In addition, since the usage of the keyboard controller 1 may be different for each system, there is a problem in that this method cannot be applied to all systems in common.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to control the three-mode FDD even without using the keyboard controller, so that the FDD control output pin of the keyboard controller can be used for other purposes as well as to all personal computers. The purpose is to provide a common FDD control device.

A feature of the present invention for achieving the above object is that in the FDD control apparatus of the personal computer, the authorized addresses SA4 to SA9, the data SD0 and SD1, the write control signal IOW #, and the address enable signal. A PAL 10 for outputting control signals MODESEL A and MODESEL B corresponding to the 2HD type 3.5-inch floppy diskettes to the three-mode FDD side according to the AEN and the reset signal RSTDRV #; The PAL 10 includes: a first inverter IN1 for inverting the address enable signal AEN; A second inverter IN2 for inverting the reset signal RSTDRV; A third inverter (IN3) for inverting the address SA7; A fourth inverter (IN4) for inverting the address SA5; The address enable signal / AEN inverted by the first inverter IN1, the write control signal IOW #, the reset signal / RSTDRV inverted by the second inverter IN2, and the address ( SA9, the address SA8, the address inverted by the third inverter IN3, / SA7, the address SA6, the address inverted by the fourth inverter IN4, / SA5, and An AND gate GT for outputting a pin enable signal PORTEN # generated by ANDing the address SA4; A first three-state buffer TB1 for turning on / off the input of the data SD0 according to a pin enable signal PORTEN # applied to the control terminal from the AND gate GT; A fifth inverter IN5 for inverting data SD0 applied through the first three state buffer TB1 and outputting the inverted data SD0 as the control signal MODESEL A; A second three state buffer TB2 for turning on / off the input of the data SD1 according to a pin enable signal PORTEN # applied to the control terminal from the AND gate GT; And a sixth inverter IN6 for inverting data SD1 applied through the second three state buffer TB2 and outputting the inverted data SD1 as the control signal MODESEL B.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The FDD control apparatus according to the present invention includes a PAL (Programmable Array Logic) 10 and a connector 20 as shown in FIG. The PAL 10 has a plurality of pins as shown in FIG. 3, the addresses SA4 to SA9 are input to the pins P2 to P7, and the data SD0 and SD1 are input to the pins P8 and P9. The write control signal IOW # is input to the pin P12, the address enable signal AEN is input to the pin P13, the pins P10 and P11 are grounded GND, and the pins P14 and P15. ) Outputs control signals MODESEL A and MODESEL B, a reset signal RSTDRV is input to pin P18, and pin P19 outputs a pin enable signal PORTEN # to pin P1. The power supply Vcc (+ 5V) is input to the pin P20. The PAL 10 controls the control signals MODESEL A and MODESEL B according to the addresses SA4 to SA9, the data SD0 and SD1, the write control signal IOW # and the address enable signal AEN that are applied at the time of power input. Outputs

The reset signal RSTDRV is a signal input to prevent a malfunction of the PAL 10.

When the PAL 10 outputs the control signals MODESEL A and MODESEL B according to the input signal, the PAL 10 first outputs the pin enable signal PORTEN # through the pin P19 and inputs it to the pin P1. The control signals MODESEL A and MODESEL B are output via (P14, P15). The PAL 10 outputs the pin enable signal PORTEN # and the control signals MODESEL A and MOBESEL B based on the following logical expression.

PORTEN # = / AENIOW # · / RSTDRV · SA9 · SA8 · / SA7 · SA6 · ISA5 · SA4

MODESEL A = / SD0

MODESEL B = / SD1

The control signals MODESEL A and MODESEL B output from the PAL 10 are applied to the 3 mode FDD through the connector 20 to which the 3 mode FDD is connected, thereby driving the 3 mode FDD corresponding to each floppy diskette type. do. By applying the control signals MODESEL A and MODESEL B output from the PAL 10 to different three mode FDDs, two three mode FDDs are controlled.

On the other hand, the PAL 10 that outputs the pin enable signal PORTEN # and the control signals MODESEL A and MODESEL B based on the above logic expression, is shown in FIG. (IN1 to 1N6), first and second three state buffers TB1 and TB2, and an AND gate GT. The first inverter IN1 inverts the applied address enable signal AEN and outputs it to the AND gate GT side, and the second inverter IN2 inverts the applied reset signal RSTDRV to the AND gate GT. The third inverter IN3 inverts the authorized address SA7 and outputs the signal to the AND gate GT. The fourth inverter IN4 inverts the applied address SA5 and the AND gate. Output to (GT) side. The AND gate G7 includes the inverted address enable signal / AEN, the write control signal IOW #, the inverted reset signal / RSTDRV, the address SA9, the address SA8, and the inverted address / SA7. ), The address SA6, the inverted address / SA5, and the pin enable signal PORTEN # generated by the AND of the address SA4, the control terminal of the first and second three state buffers TB1 and TB2. To apply. The first three state buffer TB1 turns on / off the input of the data SD0 according to the pin enable signal PORTEN # applied from the AND gate GT to the control terminal, and the fifth inverter IN5 is turned on. The data SD0 applied through the one-state buffer TB1 is inverted and output as the control signal MODESEL A. In addition, the second three-state buffer TB2 turns on / off the input of the data SD1 according to the pin enable signal PORTEN # applied to the control terminal from the AND gate GT, and the sixth inverter IN6. Inverts the data SD1 applied through the second three state buffer TB2 and outputs the inverted data SD1 as a control signal MODESEL B.

This FDD control device operates as follows.

The 3-mode FDD can record and read information on both 2HD (1.44Mbyte, 1.2Mbyte) and 2DD (720kbyte) type floppy diskettes.For the 2HD type (1.44Mbyte, 1.2Mbyte), the external control It recognizes according to the signal, and the division for 2DD type (720kbyte) is recognized by itself, not by external control signal. Therefore, the three-mode FDD is controlled according to one of the control signals MODESEL A and MODESEL B applied from the PAL 10, so that information can be recorded and read for both 2HD type and 2DD type floppy diskettes.

That is, the PAL 10 can output the control signals MODESEL A and MODESEL B in two states, a high level and a low level. When using a 1.44 Mbyte type floppy diskette, the PAL 10 can output the control signals MODESEL A and MODESEL. When B) is output at high level and a 1.2Mbyte type floppy disk is used, the control signals (MODESEL A, MODESEL B) are output at low level so that 2HD types (1.44Mbyte, 1.2Mbyte) can be distinguished. Control mode FDD. In addition, the 3 mode FDD determines itself as a 2DD type (720 kbyte) regardless of the control signals MODESEL A and MODESEL B, and operates accordingly. Therefore, the PAL 10 can control two three-mode FDDs corresponding to the floppy diskette type by outputting the control signals MODESEL A and MODESEL B. FIG.

As described above, the present invention does not require the use of a keyboard controller to control the three-mode FDD using the PAL, so that you do not have to assign an output pin for FDD control to the keyboard controller can use the corresponding output pin of the keyboard controller for other purposes, of course. It can be applied to all systems regardless of the type of system.

Claims (1)

In the FDD control apparatus of the personal computer, 2HD according to the authorized addresses SA4 to SA9, data SD0 and SD1, write control signal IOW #, address enable signal AEN and reset signal RSTDRV #. A PAL 10 for outputting control signals MODESEL A and MODESEL B corresponding to a 3.5-inch floppy diskette of the type to the three-mode FDD side; The PAL 10 includes: a first inverter IN1 for inverting the address enable signal AEN, a second inverter IN2 for inverting the reset signal RSTDRV; A third inverter (IN3) for inverting the address SA7; A fourth inverter (IN4) for inverting the address SA5; The address enable signal / AEN inverted by the first inverter IM1, the write control signal IOW #, the reset signal / RSTDRV inverted by the second inverter IN2, and the address ( SA9, the address SA8, the address inverted by the third inverter IN3, / SA7, the address SA6, the address inverted by the fourth inverter IN4, / SA5, and An AND gate GT for outputting a pin enable signal PORTEN # generated by ANDing the address SA4; A first three-state buffer TB1 for turning on / off the input of the data SD0 according to a pin enable signal PORTEN # applied to the control terminal from the AND gate GT; A fifth inverter IN5 for inverting data SD0 applied through the first three state buffer TB1 and outputting the inverted data SD0 as the control signal MODESEL A; A second three state buffer TB2 for turning on / off the input of the data SD1 according to a pin enable signal PORTEN # applied to the control terminal from the AND gate GT; And a sixth inverter (IN6) for inverting data (SD1) applied through the second three state buffer (TB2) and outputting the inverted data (SD1) as the control signal (MODESEL B).