KR0174509B1 - Apparatus for controlling access mode of memory and method - Google Patents

Abstract

The present invention relates to a memory access mode control apparatus and method for controlling a memory access mode so that a single memory and a digital signal processing period can be interfaced with various address access modes. The present invention relates to a memory provided from a digital signal processor. A first register for storing a start address for the first address; A second register for storing an end address for a memory provided from a digital signal processor; First address transfer means for selectively outputting a start address provided from the first register and a current address for the memory provided from the digital signal processor; A first current address providing unit for storing a current address or a start address transmitted from the first address transmitting means, and providing an address incremented by a predetermined unit from the stored address as a current address of the memory; When the address output from the first current address providing unit and the end address output from the second register are the same, the transmission for controlling the transfer operation of the address transmitting unit to transmit the start address to the first current address providing unit. It is configured to include a control means.

Description

Memory access mode control device and method

The present invention relates to an apparatus and method for controlling a memory access mode, and more particularly, to an apparatus and method for controlling a memory access mode that can support various address access modes for a memory in processing an interface between a digital signal processor and a memory. It is about.

The interface block between the digital signal processor and the memory, which plays the same control role as the conventional central controller, is designed to provide an address of a specific access mode to one memory. Therefore, when interfacing between the digital signal processor and the memory using various address access modes, each of the interface blocks for generating an address corresponding to the access mode to be used must be provided. Since a large number of memory having a suitable structure must be provided, the cost of the system is increased.

Accordingly, an object of the present invention is to provide a memory access mode control apparatus and method for controlling a memory access mode so as to interface a single memory with a digital signal processing period in various address access modes.

In order to achieve the above object, a memory access mode control apparatus according to the present invention includes a first register for storing a start address for a memory provided from a digital signal processor; A second register for storing an end address for a memory provided from a digital signal processor; First address transfer means for selectively outputting a start address provided from the first register and a current address for the memory provided from the digital signal processor; A first current address providing unit for storing a current address or a start address transmitted from the first address transmitting means, and providing an address incremented by a predetermined unit from the stored address as a current address of the memory; When the address output from the first current address providing unit and the end address output from the second register are the same, the transmission for controlling the transfer operation of the address transmitting unit to transmit the start address to the first current address providing unit. It characterized in that it comprises a control means.

In order to achieve the above object, a memory access mode control method according to the present invention is provided in an interface block between a digital signal processor and a memory and provides a memory access mode control method for providing various types of memory addresses. Setting an access mode; Setting variable values necessary for the memory access mode set in the access mode setting step; And a first current address providing step of modifying a current address value provided from the digital signal processor according to the set variable value to provide a current address of the memory.

1 is a block diagram of a memory access mode control apparatus according to the present invention;

Explanation of symbols for main parts of the drawings

100: data bus 101: start address register (STA)

102: end address register (ENA)

103: first multiplexer 104: first current address register (CRA0)

105: Comparator 106: Second Multiplexer

107: Second current address register (CRA1)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a memory access mode control apparatus according to the present invention, wherein a digital signal processor (hereinafter referred to as DSP) and a memory access mode control apparatus 100, which serve as a central controller, are not shown. A data bus 101 for transferring data between the data buses, a start address register 102 for storing the start address data from a DSP not shown through the data bus 101, and storing the data. When the end address data is transmitted from the DSP (not shown) via the bus 101, an end address register (ENA) 103 for storing the start address and the data bus output from the start address register 102 are provided. From the first multiplexer 104 and the first multiplexer 104 for selectively outputting the current address transmitted via 101. A first current address register (CRA0) 105 and an end address register which store an output signal as a current address and provide a value which is up counted from a stored value to a current address of a memory not shown. Compares the address output from the first current address register 105 with the comparator 106 for providing the selection control signal of the first multiplexer 104, and stores the current address applied via the data bus 101; And output from the second current address register 107, the first current address register 104, and the second current address register 107, which provide a value up-counted from a stored value to a current address of a memory, not shown. Memory is controlled by an address access mode control signal provided by a digital signal processor (not shown). It consists of a second multiplexer 106 for selectively outputting.

The memory access mode controller configured as described above supports two address access modes, one of which determines a start address and an end address, and increases by one or two or more in the determined start address and end address. In the case of providing an address in the form of an address, and in the case of providing an address in an increment of one or two or other multiples up to a predetermined final address.

In order to provide an address as described above, the memory access control apparatus 100 of FIG. 1 operates as follows.

First, when a mode for providing an address, such as the former, is set, the DSP transmits a start address, an end address, and a current address through the data bus 101, and transmits the same through the control bus (not shown). An address access mode control signal indicating the provision of an address is output.

The start address provided via the data bus 101 is transferred to and stored in the start address register 102. The start address register 102 transfers the stored address value to the (I1) input terminal of the first multiplexer 104.

The first multiplexer 104 selectively outputs a start address applied to the (I1) input terminal and a current address applied to the (I2) input terminal through the data bus 101, initially presently applied through the (I2) input terminal. Select and output the address signal. The signal output from the first multiplexer 104 is transmitted to the first current address register 105.

The first current address register 105 is configured as a loadable up counter, and stores the current address when the current address is transmitted from the first multiplexer 104, as described above, and stores the upcount in a predetermined unit from the stored value. To the comparator 105 and the second multiplexer 106, respectively. In this case, the up count unit may be set to be counted by 1, 2, or other multiples to provide various types of addresses to the memory. Such a setting may be made by a DSP not shown or may be set in advance at design time.

The comparator 106 detects whether the value output from the first current address register 105 and the value output from the end address register 103 have the same value to perform the above-described selection operation of the first multiplexer 104. To control. That is, the value output from the first current address register 105 and the value output from the end address register 103 are compared, and the result is transmitted to the selection terminal S of the first multiplexer 104. In this case, when the current address and the end address are the same, the comparator 106 provides a comparison result to the first multiplexer 104 so that the first multiplexer 104 selects and outputs a start address applied through the (I1) input terminal. .

Accordingly, the first multiplexer 104 indicates that the output signal of the comparator 106 applied to the selection terminal S has the same value as that of the end address as outputted from the first current address register 103 as described above. In this case, the start address applied through the (I1) input terminal is transmitted to the first current address register 105, and the first current address register 105 performs a predetermined unit up count from the start address.

When the second multiplexer 107 is operated in the former manner, the second multiplexer 107 selects an output signal of the first current address register 105 applied to the input terminal (I1) by an address access mode control signal applied to the selection terminal S and stores the memory. Output by address signal.

On the other hand, in the address access mode in which the address is provided while increasing the address by one, two, or other multiples up to the set final address without using the start address and end address registers as in the latter, the second multiplexer 107 is in the mode. The format control signal is operated to transmit a signal applied through the input terminal (I2), and the second current address register 108 accesses an address applied through the data bus 101.

The second current address register 108 is composed of the same loadable upcounter as the first current address register 105 described above, and the second current address register 108 is counted up by a predetermined unit with the current address accessed as an initial value of the second multiplexer 107. (I2) Transmit to input. In this case, the maximum count value corresponding to the up count unit and the last address of the second current address register 108 may be set by the DSP or may be set during system design.

Since the second multiplexer 107 selects and transmits a signal applied through the (I2) input terminal according to the address access mode control signal as described above, the second current address register 108 applied to the (I2) input terminal. Transfers the output signal to the memory address signal.

In addition, the access mode control method according to the present invention for the two types of memory access mode as described above is performed as follows.

First, the access mode to be used currently is set among the two types of memory access modes described above, and then the set access mode specifies the start address and the end address as described above, and increases the address by a predetermined multiple within the specified range. If you want to provide the address, set the start address, end address, current address, and address increment unit. Here, the memory access mode is further divided by the address increment unit. That is, the memory access mode can be set differently depending on whether the address increment unit is set to 1, 2, or other multiples.

Then, the set current address is provided as the first address of the memory, and then the current address increased in increments is continuously transferred to the address of the memory. During the address transfer, when the increased current address is the same as the end address, the process of providing the start address as the current address and increasing the address in the above-mentioned predetermined unit again and providing the address to the memory not shown is repeated.

In the above-described method, when the current address as described above is increased in a predetermined unit and provided as a memory address signal, the increment unit and the current address are set, the set current address is provided as the initial address of the memory, and then in increment units. The address that is incremented each time is provided as a memory address. At this time, the final address can be set, and the above-described incrementing process is continued until the final address is reached, and when the final address is reached, the address providing operation can be stopped, and the loop address method is used again for the first time. It may be configured to repeat the process of returning to the current address value of and incrementing the address in a predetermined incremental unit and providing the address to the memory. In this case, the memory address access mode may be provided in various ways depending on how the increment is set.

As described above, the present invention implements an apparatus and method capable of providing various address access modes in a single memory with a simple structure, thereby enabling efficient memory management, and providing various address access modes. There is an effect that can prevent the rise in system prices.

Claims (14)

A memory access mode control apparatus provided in an interface block between a digital signal processor and a memory to provide various types of memory addresses, the apparatus comprising: storing a current address transmitted from the digital signal processor, and storing the current address in a predetermined unit from the stored current address; And a current address providing unit for providing an incremented address to the current address of the memory. The memory access mode control apparatus as claimed in claim 1, wherein the current address providing unit sets a final address value that can be reached by the increase in consideration of a memory condition. The apparatus of claim 1 or 2, wherein the address increment amount and the final address value of the predetermined unit are provided by the digital signal processor. The loop of claim 2, wherein the current address providing unit provides the final address value to the memory, and then returns to the current address value provided from the digital signal processor and increases the predetermined address in the predetermined unit to provide an address of the memory. And a memory access mode control device configured to perform an address access mode. A memory access mode control apparatus provided in an interface block between a digital signal processor and a memory to provide various types of memory addresses, comprising: a first register for storing a start address for the memory provided from the digital signal processor; A second register for storing an end address for the memory provided from the digital signal processor; First address transfer means for selectively outputting the start address provided from the first register and a current address for the memory provided from the digital signal processor; A first current address providing unit for storing the current address or start address transmitted from the first address transmitting means, and providing an address incremented by a predetermined unit from the stored address as a current address of the memory; When the address output from the first current address providing unit and the end address output from the second register are the same, the address transmission unit transmits the address transfer unit to transmit the start address to the first current address providing unit. And a transmission control means for controlling the operation. The method of claim 5, wherein the address transmitting means selects an input signal so that the current address is transmitted to the first current address providing unit when the current address is transmitted from the digital signal processor. And a multiplexer configured to select an input signal so that the start address is transmitted to the first current address providing unit when the end address is the same as that of the end address. The comparator according to claim 5 or 6, wherein the transmission control means compares the end address with the current address and detects whether the transmission address has the same value, and provides the detected result as a signal for controlling the transmission operation. Memory access mode control device, characterized in that made. The memory access mode control apparatus of claim 5, wherein the memory access mode controller is further configured to store a current address transmitted from the digital signal processor and to provide, as a current address of the memory, an address incremented by a predetermined unit from the stored current address. A current address provider; And a second address for selectively transmitting an address transmitted from the first current address provider and an address transmitted from the second current address provider to the memory by an address access mode control signal provided by the digital signal processor. Memory access mode control apparatus further comprising a transmission means. 10. The apparatus of claim 8, wherein the second current address providing unit sets a final address value that can be reached by the increase in consideration of a memory condition. 10. The apparatus of claim 8 or 9, wherein the address increment amount and the final address value of the predetermined unit are provided by the digital signal processor. 10. The method of claim 9, wherein the second current address providing unit provides the address of the memory while providing the final address value to the memory and then returning the current address value provided from the digital signal processor to increase the predetermined address. And a loop address access mode. A memory access mode control method provided in an interface block between a digital signal processor and a memory to provide various types of memory addresses, the method comprising: setting a memory access mode to be used at present; Setting variable values necessary for the memory access mode set in the access mode setting step; And a first current address providing step of modifying a current address value provided from the digital signal processor according to a set variable value to provide a current address of the memory. The digital display device of claim 12, wherein the providing of the first current address is performed when the memory access mode set in the access mode setting step is a mode in which addresses are provided in increments of a predetermined unit within a start address and an end address range. Storing a start address provided by the signal processor; Storing an end address provided by the digital signal processor; Storing a current address provided by the digital signal processor; A second current address providing step of providing an address incremented by a predetermined unit from the stored current address to a current address of the memory; When the address provided in the second current address providing step has the same value as the end address, storing the start address as a current address and providing the memory to the memory; And a third current address providing step of providing a current address of the memory while increasing from the start address in the predetermined unit. The digital signal of claim 12, wherein the providing of the first current address is performed when the memory access mode set in the access mode setting step is a mode in which the current address provided by the digital signal processor is increased by a predetermined unit. Transmitting from the current address transmitted from the processor to the address of the memory, the address increasing in a predetermined unit set in the variable setting step; If the address increased by the predetermined unit reaches the final address set in consideration of the condition of the memory in the variable setting step, returning to the current address provided from the digital signal processor and repeating the transmission step. Memory access mode control method characterized in that performed by.