KR0173915B1 - Apparatus and method of encoding the bit stream in video codec - Google Patents

Abstract

The present invention relates to a bit string encoding apparatus and a method thereof in a video codec. In the case of a numeric string receiving quantized data from a quantizer 2, the present invention encodes numeric data to output encoded data and a length value, and then a character string. In the case of performing the encoding by storing the least significant bit in the position of the most significant bit, the PLA unit 10 which outputs the most significant bit (MSB), the encoded data and the length value, and the sign (+/-) from the quantizer 2 ) Data received, header information is received from the header determiner 3, and in the case of a string, the flip-flop 20 and the PLA unit 10 are encoded by receiving the most significant bit from the PLA unit 10 and outputting it. Shift register 30 for receiving data and shifting the input data and outputting the length value from the PLA unit 10 and counting the length value of the multiplexer control signal according to the length value. The output data of the shift register 30 is multiplexed and output by the multiplexing controller 40 and the control signal of the multiplexing controller 40, and the flip-flop is controlled by the control signal of the multiplexing controller 40. It consists of a multiplexer 50 that outputs the data stored in 20), stores it in a sign (+/-) bit flip-flop, fixes it, outputs all the remaining bits, and outputs the data of the flip-flop at the end. In addition, even in the case of character data rather than numeric data, the coder is encoded in the same hardware by different coders, thereby reducing the amount of hardware.

Description

Bitstream Coding Apparatus and Method in Video Codec

1 is a block diagram of a video codec to which the present invention is applied.

2 is an overall configuration diagram of a bit string encoding apparatus according to an embodiment of the present invention.

3 is a block diagram of a PLA unit according to an embodiment of the present invention.

4 is an overall flowchart according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: PLA part 20: flip-flop

30: shift register 40: multiplex controller

50: multiplexer

The present invention relates to a bit string encoding apparatus and a method in a video codec.

In general, in a video codec, an encoding apparatus refers to a device for converting a quantized discrete cosine transform (DCT) coefficient into a bit string that may be transmitted to a counterpart video codec through a modulator / demodulator. Such an encoding apparatus adopts a variable length code in order to reduce the bit string as much as possible. There are two major bitstream hatchings in a video codec. One is to encode numbers with positive and negative signs (+/-), and the other is to encode options that indicate the type of block and whether each block is coded separately. The big difference between these two encodings is that the number is encoded by the absolute value minus the sign (+/-), which determines the remaining bits of the entire code data except for the last bit. None of these options correspond to the sign (+/-), so there is no such bit. However, since the coded (+/-) bit cannot be written at the beginning when encoding a number due to the characteristic of variable length coding, conventionally, the coded (+/-) bit is additionally added to the end of the variable data that is variably changed. Method was used. In the conventional method as described above, since the positions of sign (+/-) bits are very diverse, it is very complicated when implemented in hardware, and the amount of hardware is increased.

In order to solve the problems of the prior art as described above, the present invention stores in a (+/-) bit flip-flop to fix it, outputs all the remaining bits, and then outputs the data of the flip-flop and encodes it. The present invention also provides a bit stream encoding apparatus and method for a video codec capable of reducing the amount of hardware by encoding only the coder in the case of character data rather than numeric data.

In order to achieve the above object, the present invention receives quantization data from a quantizer, encodes numeric data in the case of a numeric string, outputs encoded data and a length value, and stores the least significant bit in the most significant bit position in the case of a string. After performing the encoding, the PLA (Programmed Logic Array, PLA) means for outputting the most significant bit (MSB), the coded data and the length value, the sign (+ /-) data from the quantizer, the header determiner A flip-flop means for receiving header information from the PLA means and receiving a most significant bit from the PLA means, a shift register means for receiving encoded data from the PLA means and shifting and outputting the data, and a length from the PLA means. Input the value and count the length value and output the multiplexer control signal according to the length value. And multiplexing means for multiplexing and outputting output data of the shift register means by a multiplexing control means and a control signal of the multiplexing control means, and outputting data stored in the flip-flop means by a control signal of the multiplexing control means. It is characterized by.

In the bit rate encoding method applied to the video codec, when data is input from the quantizer, the most significant bit of the string in which the sign (+/-) data and the least significant bit are stored in the position of the most significant bit is separately stored in the flip-flop means. A first step of performing encoding and outputting encoded data and a length value to reduce the length value and outputting the encoded data and then determining whether the length value is 1; In the first step, if the length value is not 1, the coded data is output while the length value is continuously decreased; if the length value is 1, the data stored in the flip-flop means is output; step; And repeating the encoding process by returning to an initial state if not the last macroblock in the second step. If the last macroblock, the header information is inputted to the flip-flop means from the header determiner, and the header information is inserted and outputted last. It characterized in that it comprises a third step.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a block diagram of a video codec to which the present invention is applied. In the drawing, code 1 represents a discrete cosine converter, code 2 represents a quantizer, code 3 represents a header determiner, and code 4 represents an encoder of the present invention.

Referring to the operation of the present invention, the discrete cosine converter 1 converts the input data to discrete cosine and outputs it to the quantizer 2. The quantizer 2 quantizes the discrete cosine transformed analog signal and outputs a digital signal to the encoder 4. The header determiner 3 outputs fixed length header information to the protector 4 to indicate a state in which encoding is performed for each coding block. The encoder 4 receives an output of the header determiner 3 and an output of the quantizer 2 and outputs the encoded bit string.

2 is an overall configuration diagram of a bit string encoding apparatus according to an embodiment of the present invention, in which 10 is a PLA unit, 20 is a flip-flop, 30 is a shift register, 40 is a multiplexing controller, and 50 is a Each multiplexer is shown.

The present invention receives the quantization data from the quantizer 2, encodes the numeric data in the case of the numeric string, outputs the encoded data and the length value, and stores the least significant bit in the position of the most significant bit in the case of the string, thereby performing encoding. After performing the most significant bit (MSB), the coded data and the PLA unit 10 for outputting the length value, the sign (+ /-) data is input from the quantizer 2, the header information from the header determiner (3) In the case of receiving a character string, a flip-flop 20 which receives the most significant bit from the PLA unit 10 and outputs it, and a shift register which receives encoded data from the PLA unit 10 and shifts the input data and outputs the shift register ( 30), the multiplexing controller 40 for receiving the length value from the PLA unit 10 and counting the length value and outputting a multiplexer control signal according to the length value, and the control scene of the multiplexing controller 40 By comprises a multiplexer (50) for outputting data stored in the flip-flop 20 by the control signal from the multiplexing controller 40 outputs the multiplexing output data of the shift register 30, and.

First, referring to the encoding process for the numeric data, sign (+/-) data input from the quantizer 2 is stored in the flip-flop 20, and the remaining quantized digital data is input to the PLA unit 10. The PLA unit 10 encodes the input quantized data and outputs the encoded data to the shift register 30. In addition, the PLA unit 10 outputs the length value of the input quantization data to the multiplexing controller 40. The shift register 30 outputs bit by bit to the multiplexer 50 while shifting data input by bit. The multiplexing controller 40 outputs a control signal to the multiplexer 50 so that the data stored in the shift register 30 can be outputted if the length value is decreased and counted while the length value is not 1, and the length value is 1, The control signal is output to the multiplexer 50 so that the sign (+/-) data stored in the flip-flop 20 can be output. The multiplexer 50 outputs data stored in the shift register 30 by the control of the multiplexing controller 40 and then outputs sign (+/−) data stored in the flip-flop 20 at the end of the bit string. Inserting header information at the end of the coding block while storing the fixed length header information inputted from the header determiner 3 in the flip-flop 20 at the time when encoding of one block is completed through the above operation. Outputs to complete the encoding of one block.

Next, since encoding (+/-) data does not exist unlike numeric data, the encoding process for the character string stores the least significant bit of the bit string input from the PLA unit 10 at the most significant bit position and flips the most significant bit. 20) and performs encoding through the same control operation as that of encoding numeric data.

3 is a block diagram of the PLA unit 10 according to an embodiment of the present invention, the PLA unit 10 receives the quantized data of the numeric data from the quantizer 2 and encodes it to the shift register 30 The first length PLA unit 12 and the quantizer 2 that receive the quantized data from the numeric bit string PLA unit 11 and the quantizer 2, calculate a length value, and output the calculated quantization data to the multiplexing controller 40. Character string string receiving the quantized data of the character string from the string), storing the least significant bit at the position of the most significant bit, outputting the data stored in the most significant bit to the flip-flop 20, and outputting the encoded data to the shift register 30. The PLA unit 13 and the second length PLA unit 14 which receives the quantization data from the quantizer 2, calculates a length value, and outputs the length value to the multiplexing controller 40.

4 is an overall flowchart according to an embodiment of the present invention.

When data is input from the quantizer 2 (100), the most significant bit of the string in which the sign (+/-) data and the least significant bit are stored in the position of the most significant bit is stored in the flip-flop 20 (200). The PLA unit 10 outputs the encoded data and the length value (300), outputs the encoded data while reducing the length value (400), and determines whether the length value is 1 (500). If the length value is not 1, the coded data is output while the length value is continuously decreased (400). If the length value is 1, the data stored in the flip-flop 20 is outputted (600). Determine (700). If not the last macro block, the process returns to the initial state and repeats the encoding process (100 to 700). If the last macro block, the header information is input from the header determiner 3 to the flip-flop 20 (800). Insert and output (900) and end.

The present invention constructed and operated as described above stores and stores it in a sign (+/-) bit flip-flop, outputs all the remaining bits, and then outputs and encodes data of the flip-flop at the end. In the case of character data, only the coder is differently encoded by using the same hardware, thereby reducing the amount of hardware.

Claims (3)

The quantizer 2 receives quantized data and encodes the numeric data in the case of the numeric string, outputs the encoded data and the length value, and in the case of the string, stores the least significant bit in the most significant bit position before performing encoding. PLA (Programmed Logic Array, PLA) means for outputting the bit (MSB), the coded data and the length value (10); A flip-flop that receives sign (+/-) data from the quantizer 2, receives header information from the header determiner 3, and receives a most significant bit from the PLA unit 10 in the case of a string. Means 20; Shift register means (30) which receives encoded data from the PLA unit (10) and shifts and outputs the input data; Multiplexing control means (40) for receiving the length value from the PLA unit (10) and counting the length value and outputting a multiplexer control signal according to the length value; And outputting the output data of the shift register 30 by multiplexing the control signal of the multiplexing control means 40 and storing the data in the flip-flop means 20 by the control signal of the multiplexing control means 40. And a multiplexing means (50) for outputting the bit stream encoding apparatus of the video codec. The apparatus of claim 1, wherein the PLA means (10) comprises: numeric bit string PLA means (11) for receiving quantized data of numeric data from the quantizer (2), encoding the encoded quantized data, and outputting the encoded data to the shift register means (30); First length PLA means (12) for receiving quantization data from the quantizer (2), calculating a length value, and outputting the calculated length value to the multiplexing control means (40); Receives the quantized data of the character string from the quantizer 2, stores the least significant bit at the position of the most significant bit, outputs the data stored in the most significant bit to the flip-flop means 20, and outputs the encoded data to the shift register means 30. A character bit string PLA means 13 outputting the same; And second length PLA means 14 for receiving quantization data from the quantizer 2 and calculating a length value and outputting the quantized data to the multiplexing control means 40. Device. In the bit rate encoding method applied to the video codec, when data is input from the quantizer 2, the most significant bit of the string in which the sign (+/-) data and the least significant bit are stored in the position of the most significant bit is flip-flop (20). A first step (100 to 500) of separately storing the data in a coded manner, outputting the encoded data and the length value, outputting the encoded data while reducing the length value, and determining whether the length value is 1; In the first step (100 to 500), if the length value is not 1, the encoded data is output while the length value is continuously decreased, and if the length value is 1, the data stored in the flip-flop 20 is output, and the last of one coding block is output. Determining whether it is a macro block (step 600, 700); And returning to the initial state if the last macroblock is not the last macroblock in the second step (600, 700), and if the last macroblock, the header information is received from the header determiner (3) into the flip-flop (20). And a third step (800, 900) of inserting and outputting at the end and ending the output.