KR0172249B1 - Method for forming a contact of a semiconductor device - Google Patents
Method for forming a contact of a semiconductor device Download PDFInfo
- Publication number
- KR0172249B1 KR0172249B1 KR1019950031254A KR19950031254A KR0172249B1 KR 0172249 B1 KR0172249 B1 KR 0172249B1 KR 1019950031254 A KR1019950031254 A KR 1019950031254A KR 19950031254 A KR19950031254 A KR 19950031254A KR 0172249 B1 KR0172249 B1 KR 0172249B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- pattern
- polysilicon
- contact hole
- oxide film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 description 24
- 239000004020 conductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 미세한 콘택홀을 형성하기 위하여 다결정실리콘 패턴을 형성하여 하드 마스크로 사용하고, 상기 다결정실리콘패턴의 상부 및 측벽에 부피 팽창된 산화막을 형성하여 이 산화막을 콘택홀 마스크로 사용하므로써, 미세 콘택홀을 형성하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In order to form a fine contact hole, a polysilicon pattern is formed and used as a hard mask, and a volume-expanded oxide film is formed on upper and sidewalls of the polysilicon pattern. By using an oxide film as a contact hole mask, fine contact holes are formed.
Description
제1도 내지 제3도는 본 발명에 의해 다결정실리콘 박막의 산화막에 의한 자기정합 콘택을 형성하는 단면도.1 to 3 are cross-sectional views for forming a self-aligned contact by an oxide film of a polysilicon thin film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2,2' : 절연막1 semiconductor substrate 2,2 'insulating film
3 : 전도체 4 : 다결정실리콘 콘택패턴3: conductor 4: polysilicon contact pattern
5 : 산화막 6, 7 : 콘택홀5: oxide film 6, 7: contact hole
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 콘택홀 마스크로 다결정실리콘 패턴을 이용하고, 이 다결정실리콘 패턴의 일정두께를 산화시켜 형성된 산화막을 마스크로 이용하여 미세한 크기의 콘택홀을 형성할 수 있는 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a contact hole having a small size is formed by using a polysilicon pattern as a contact hole mask and an oxide film formed by oxidizing a predetermined thickness of the polysilicon pattern as a mask. The contact hole formation method of the element which can be made is related.
일반적으로, 기존의 콘택홀 형성방법은 두꺼운 절연층의 상부에 포토레지스트층을 두껍게 도포한 후 노광 및 현상공정으로 포토레지스트패턴을 형성하고, 이것을 마스크로 사용하여 하부에 있는 절연층을 식각하므로써, 콘택홀을 형성한다.In general, the conventional method for forming a contact hole is by forming a photoresist pattern thickly on top of a thick insulating layer, and then forming a photoresist pattern by an exposure and developing process, and using the mask as an mask to etch the insulating layer underneath. A contact hole is formed.
그런, 포토레지스트패턴을 이용하여 0.5㎛이하의 콘택홀을 형성하는데 있어서, 포토레지스트가 두꺼워지면 노광 및 현상공정에서 해상도가 저하되어 미세 콘택홀을 형성하는 마스크로 사용하는 것은 어려워진다.In forming a contact hole of 0.5 mu m or less by using such a photoresist pattern, when the photoresist becomes thick, it becomes difficult to use it as a mask for forming a fine contact hole because the resolution decreases in the exposure and development processes.
또한, 상기 포토레지스트패턴의 문제점을 보완하기 위해 산화막 스페이서를 이용하는데 건식식각으로 산화막을 부분식각할때 조절이 어려운 단점이 있다.In addition, in order to compensate for the problem of the photoresist pattern, there is a disadvantage that it is difficult to control when partially etching the oxide film by dry etching.
따라서, 본 발명은 상기한 문제점을 해결하기 위하여 다결정실리콘 패턴을 하드마스크로 이용하여 이에 따른 포토레지스트의 두께를 줄이고, 상기 다결정실리콘 패턴의 일정두께를 산화시켜 부피가 팽창한 산화막을 형성하고, 이 산화막을 콘택홀 마스크로 이용하므로써, 미세한 콘택홀을 형성하는 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention reduces the thickness of the photoresist by using a polysilicon pattern as a hard mask in order to solve the above problems, and oxidizes a predetermined thickness of the polysilicon pattern to form an expanded oxide film. It is an object of the present invention to provide a method for forming a fine contact hole by using an oxide film as a contact hole mask.
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택홀 형성방법은 실리콘기판의 상부에 절연막을 증착하는 단계와, 상기 절연막 상부에 다결정실리콘을 증착하는 단계와, 상기 다결정실리콘층의 상부에 콘택마스크용 감광막 패턴을 형성하는 단계와, 상기 감광막패턴을 사용하여 다결정실리콘층을 식각하여 다결정실리콘 패턴을 형성하는 단계와, 상기 다결정실리콘 패턴의 일정두께를 산화시켜 다결정실리콘 패턴의 상부와 측벽에 산화막을 형성하는 단계와, 상기 산화막을 마스크로 이용하여 노출된 하부의 절연막을 식각하여 반도체기판이 노출된 콘택홀을 형성하는 단계를 포함하는 것을 특징으로 한다. 이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 하자.A method of forming a contact hole in a semiconductor device of the present invention for achieving the above object comprises the steps of depositing an insulating film on top of a silicon substrate, depositing polycrystalline silicon on the insulating film, and a contact mask on the polycrystalline silicon layer Forming a photoresist film pattern, etching the polysilicon layer using the photoresist pattern to form a polysilicon pattern, and oxidizing a predetermined thickness of the polysilicon pattern to form an oxide film on the top and sidewalls of the polysilicon pattern. And forming a contact hole through which the semiconductor substrate is exposed by etching the exposed lower insulating layer by using the oxide layer as a mask. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도 내지 제3도는 본 발명의 실시예에 의해 반도체소자의 콘택홀 형성 단계를 도시한 단면도이다. 제1도는 실리콘기판(1)의 상부에 제1절연막(2)을 증착하고, 상기 제1절연막(2)의 상부에 전도체(3)를 형성하고, 그 상부에 제2절연막(2`)을 평탄하게 형성하고, 전체 구조의 상부에 화학기상증착법으로 1000내지 2000Å두께의 다결정실리콘층을 증착하고, 상기 다결정실리콘층의 상부에 강광막을 도포하고, 콘택마스크를 이용한 노광 및 현상 공정으로 감광막패턴(10)을 형성하고, 상기 감광막패턴(10)을 마스크로 사용하여 다결정실리콘층을 식각하여 다결정실리콘패턴(4)을 형성한 단면도이다. 참고로, 상기 전도체(3)는 생략되어도 관계없다.1 to 3 are cross-sectional views illustrating a step of forming a contact hole in a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a first insulating film 2 deposited on the silicon substrate 1, a conductor 3 formed on the first insulating film 2, and a second insulating film 2 ′ formed thereon. It is formed flat, a polysilicon layer having a thickness of 1000 to 2000 kPa is deposited on the top of the entire structure by chemical vapor deposition, a strong light film is coated on the polysilicon layer, and a photoresist pattern is formed by an exposure and development process using a contact mask. 10) and a polysilicon layer 4 is etched using the photosensitive film pattern 10 as a mask to form a polysilicon pattern 4. For reference, the conductor 3 may be omitted.
제2도는 상기 감광막패턴(10)을 제거하고, 800 내지 900℃온도에서 상기 다결정실리콘 패턴(4)의 일정두께를 산화시켜 상기 다결정실리콘패턴(4)의 상부와 측면에 500 내지 2000Å정도의 산화막(5)을 형성한 단면도이다. 이때, 남아있는 다결정실리콘패턴(4)의 두께는 750내지 1500Å이다.FIG. 2 illustrates that the photoresist film pattern 10 is removed, and a predetermined thickness of the polysilicon pattern 4 is oxidized at a temperature of 800 to 900 ° C. to form an oxide film having a thickness of about 500 to 2000 μs on the top and side surfaces of the polysilicon pattern 4. It is sectional drawing which formed (5). At this time, the thickness of the remaining polysilicon pattern 4 is 750-1500 Å.
제3도는 상기 산화막(5)을 콘택홀 마스크로 사용하고 하부에 있는 노출된 제2절연막(2`)과 제1절연막(2)를 순차적으로 이방성식각하여 반도체기판(1)이 노출되는 제1콘택홀(6)과, 전도체(3)가 노출되는 제2콘택트홀(7)을 형성한 다음, 상기 산화막(5)과 다결정실리콘패턴(4)을 제거한 단면도이다. 참고로, 콘택트홀 형성할 때 등방성식각을 일정시간 행한 후 이방성식식각을 진행해도 된다.FIG. 3 illustrates a first substrate in which the semiconductor substrate 1 is exposed by anisotropically etching the second insulating film 2 ′ and the first insulating film 2 ′ under the oxide film 5 as a contact hole mask. After forming the contact hole 6 and the second contact hole 7 through which the conductor 3 is exposed, the cross-sectional view of the oxide film 5 and the polysilicon pattern 4 is removed. For reference, when forming a contact hole, anisotropic etching may be performed after performing isotropic etching for a predetermined time.
상술한 바와 같이 본 발명의 반도체소자의 콘택홀 형성 방법은 미세콘택을 형성하기 위하여, 다결정실리콘패턴을 하드마스크로 사용하므로써 감광막 두께를 얇게 형성할 수 있으며, 상기 다결정실리콘 패턴의 일정두께를 산화시켜 부피 팽창된 산화막을 형성하여 콘택트에서 콘택홀의 크기가 감소되어 미세한 크기의 콘택트를 형성할 수 있다는 이점을 제공한다.As described above, in the method of forming a contact hole in the semiconductor device of the present invention, in order to form a micro contact, the thickness of the photoresist film can be made thin by using a polysilicon pattern as a hard mask, and a predetermined thickness of the polysilicon pattern is oxidized. Forming a volume-expanded oxide film provides the advantage that the size of the contact hole in the contact can be reduced to form a contact of fine size.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031254A KR0172249B1 (en) | 1995-09-21 | 1995-09-21 | Method for forming a contact of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031254A KR0172249B1 (en) | 1995-09-21 | 1995-09-21 | Method for forming a contact of a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970018103A KR970018103A (en) | 1997-04-30 |
| KR0172249B1 true KR0172249B1 (en) | 1999-03-30 |
Family
ID=19427548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950031254A KR0172249B1 (en) | 1995-09-21 | 1995-09-21 | Method for forming a contact of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172249B1 (en) |
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1995
- 1995-09-21 KR KR1019950031254A patent/KR0172249B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970018103A (en) | 1997-04-30 |
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