KR0167899B1 - Data segment sync. detection circuit of hdtv system - Google Patents

Abstract

In the data segment synchronization detection circuit, a hard limiter 400 is added between the four-symbol corrector 305 and the adder 307 to obtain an output value of two bits of three levels for the input of four bits, When the 1-segment delay element is converted into ASIC, the number of gates required is 6 bits × 832 × 7 bits = 34,944 gates, which is a reduction of about 12,000 gates compared to the conventional technology. In addition, since bit resolution is reduced, It is effective.

Description

Data segment synchronization detection circuit of high-grade television system

Figure 1 also shows the data format of the US GA-VSB high-definition television system.

Figure 2 also shows the data segment sync signal format.

FIG. 3 is a circuit diagram of a data segment sync detection circuit of a conventional high-definition television system.

FIG. 4 is a circuit diagram of a data segment sync detection circuit of a high-definition television system of the GA-VSB according to an embodiment of the present invention.

5 is a specific circuit diagram of the hard limiter 400 of FIG.

The present invention relates to a data segment synchronization detection circuit of a high-definition television (HDTV) system, and more particularly to a data segment synchronization detection circuit of a high-definition television system capable of reducing complexity and simplifying implementation in ASIC.

Generally, in a high definition television system, a telecommunication broadcasting station inserts a synchronization signal at the head of a signal transmitted in horizontal line units, and the receiver, receiving the transmission signal, detects a synchronization signal in the received transmission signal, After synchronizing with the signal, it processes the received signal. In the high-resolution television, the transmission data of the horizontal line are configured differently according to the method. FIG. 1 is a block diagram of a data segment of a high-resolution digital television (US GA) high definition television, wherein one data frame is composed of 626 line segments, and each segment consists of 828 symbol data and 4 symbol data segment synchronization signals 832 symbols are composed of one data segment. The one data segment corresponds to one horizontal line of the NTSC system. As in the second diagram (2B), the sync signal of the data segment consists of 4 symbols (4 symbols) indicating the start of each data segment as shown in the second figure (2A). In this case, the sync signal of the data segment has a constant pattern with four symbols having signal levels of +5, -5, -5 and +5, and the remaining data segment signals have random signal levels.

Therefore, in the apparatus for receiving the transmission signal of the GA scheme, the synchronization signal of the data segment is detected in the first four symbol periods of each data segment, and then the timing recovery and the received data segment signals are solved . Therefore, this greatly affects the performance of the GA-VSB system. An apparatus and method for generating a segment sync signal from data received as described above are disclosed in Korean Patent Application No. 1995-15218, 30746.

3, only the MSB is taken in the separator 303 among the output 8 bits of the matched filter (not shown), and the second signal is converted into the reference signal And receives it from the four-symbol corrector 305 to perform a predetermined correction. However, since only the MSB sign bit is used in the 4-symbol corrector 305 as described above, 4 is output only when the sign of the input signal is (+), (-), (-), -4, -2, 0, 2 are output. The output of the 4-symbol corrector 305 is added to and accumulated in the adder 307 with the output of the 1-segment delay 309, which is output at the same position of the previous segment. The output of the adder 307 is input to a maximum value detector 311.

The maximum value detector 311 observes the accumulated correction output for 832 symbols (one segment), determines the position at which the largest value appears as the segment synchronization position, and inputs the information to the synchronization generator 313. The synchronization generator 313 is adapted to generate a synchronization pulse at the position. However, since the output of the 4-symbol corrector 305 is 4 bits, an adder and an 832 symbol delay element for accumulating the 4-symbol corrector 305 are required as shown in FIG. 3, which has a bit resolution of at least 8 bits. However, when the ASIC is implemented with 832 symbol delay elements, it requires 8 bits × 832 × 7 gates. This requires too many gates compared to the desired function.

Accordingly, it is an object of the present invention to provide a method and a circuit which can reduce the bit resolution of an element without using a hard limiter in the output of the corrector, thereby reducing the number of gates in the ASIC implementation.

In order to accomplish the above object, a hard limiter is added to an output terminal of a 4-symbol corrector to generate a segment sync signal capable of reducing the number of gates.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram according to an embodiment of the present invention. The third difference is that a hard limiter 400 is added between the 4-symbol corrector 305 and the adder 307 to generate a 3- So as to obtain an output value of 2 bits.

FIG. 5 is a specific circuit diagram of the hard limiter 400 of FIG. 4, in which a separator 501 for separating the MSB from the output 4 bits of the 4-symbol corrector 305 and a comparator (A = B) The first comparator 505 compares the output value of the 4-symbol corrector 305 with the 4-bit value of the level 3 and determines whether the value of the 4-symbol value is larger than the value of the level 3 B) a second comparator 507, a combiner 503 for combining the output of the first comparator 505 and the output of the second comparator 507, 00), 0 (10), and 1 (11).

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 4 to 5, wherein the MSB of 8 bits output from the matched filter is separated from the separator 303. Then, the MSB is corrected by the 4-symbol corrector 305 in a predetermined manner. Since the correction technique is the same as the conventional technique, a detailed description thereof will be omitted. The 4 bits corrected by the 4-symbol corrector 305 are applied to the hard limiter 400 as shown in Table 1 below. The hard limiter 400 receives the 4 bits of the 4-symbol corrector 305 and separates the MSB from the separator 501 as shown in FIG.

The MSB is applied to the first comparator 503 and the output of the 4-symbol corrector 305 to the second comparator 507. In this case, the first comparator 505 compares the input of the MSB with the level 0, and when the input is less than 0, the input of the first comparator 500 becomes 1, so that the output of the first comparator 500 becomes zero. However, the second comparator 507 compares the output 4 bits of the 4-bit symbol corrector 305 with the level 3. Since the input is less than 0, the output of the second comparator 507 is zero. Accordingly, the output of the combiner 503 becomes 00, and the multiplexer 507 selects and outputs -1. However, if the input is between 0 and 3, the output of the first comparator 505 is 1, the output of the second comparator 507 is 0, and the multiplexer 507 outputs 0 corresponding to the input 10 Likewise, when the input is 3 or more, the input of the multiplexer 507 becomes 11, and the multiplexer 507 selectively outputs 1.

As described above, the 2-bit value is outputted, and the result is input to the accumulator composed of the adder and the 1-segment delay. As a result, even if SNR = OdB, it is confirmed that correct segment synchronization occurs when the accumulated correction result of the segment synchronous position is 8 or more I could. That is, the accumulated result of 6 bits is enough. Therefore, when the 1-segment delay device is converted to ASIC, the number of gates required is about 6,000 × 832 × 7 bits = 34,944 gates, which is about 12,000 gates compared to the conventional technology. In addition, the bit resolution is reduced, which reduces the complexity of other operators.

Claims (2)

In the data segment synchronization detection circuit, a hard limiter 400 is added between the 4-symbol corrector 305 and the adder 307 to obtain 2-bit output values of 3-level values for 4-bit inputs Wherein the data segment synchronization detection circuit comprises: 2. The apparatus of claim 1, wherein the hard limiter (400) comprises: a separator (501) for separating the MSB from the output 4 bits of the 4-symbol corrector (305) A comparator 505 compares the output value of the 4-symbol corrector 305 with the 4-bit value of the output 4 bits and the level 3 to determine whether the 4-symbol value is larger than the value of the level 3 B) a second comparator 507, a combiner 503 for combining the output of the first comparator 505 and the output of the second comparator 507, 00), 0 (10), and 1 (11).