KR0164966B1 - The multistage interconnection network with the folded structure and loop-back function - Google Patents

Abstract

The present invention is an improvement of the structure of a conventional interconnection network, and is a multi-stage interconnection with improved performance to improve the interconnection between switches in the intermediate stage of a conventional multistage interconnection network and inefficiencies in local communication. It's about the network. Specifically, first, the switch network of the highest level is connected to each other in the basic Bennet network by the folded structure to secure the multipath. Second, the multistage interconnection network of the present invention improves the communication delay problem between adjacent nodes by adding a loop-back function to the switch node of the first stage. This looping function enables direct communication with neighbor nodes without having to go through the entire stage when communicating with neighbor nodes. Therefore, unlike the original multilevel interconnection network, it is possible to prevent unnecessary network delay increase in local communication between adjacent nodes. In the mid-stage, cost-performance considerations allow system designers to use shuffle or straight boards. Straight line connections can reduce costs, and when shuffled connections are used, multipaths can be obtained at intermediate stages, improving overall system performance. The dual implementation of the first stage and the last stage (top-level stage) can also improve the performance of the entire interconnect network system by compensating for the conventional non-recoverable failure in this node switch.

Description

Multilevel interconnection network with folded structure and loopback

1 is a diagram illustrating a structure in which processor nodes are connected by a multistage interconnection network. FIG. 1 (a) illustrates a structure in which each processor node includes a single processor, and FIG. 1 (b) illustrates each processor node. Figure illustrates a structure that includes a processor, cache, memory, and I / O devices.

2 (a) illustrates a network having a unidirectional link, and FIG. 2 (b) illustrates a network having a bidirectional link of the present invention.

3 illustrates a prior art multistage interconnection network.

4 (a) illustrates an improved multistage interconnection network of the present invention in which the connection between the intermediate stages is a straight line connection, and FIG. 4 (b) illustrates a multistage interconnection network in which the connection between the intermediate stages is a shuffle connection.

5 illustrates a connection pattern of a switching node for use in the improved multistage interconnection network of the present invention.

Figure 6 is a block diagram detailing the switch node of the improved first stage of the present invention.

7 is a block diagram illustrating a network traversal path of data in a conventional multistage interconnection network.

8 is a block diagram illustrating a network traversal path of data in an improved multistage interconnection network of the present invention.

9 is a block diagram describing routing tag information for routing.

10 is a block diagram of a multilevel interconnection network with redundant steps for error tolerance.

* Explanation of symbols for main parts of the drawings

100: bidirectional link 200: crossbar switch

300: first stage switching board 400: shuffle backplane

500: linear connection switching board 600: transmitter

1000: processor node 2000: switch node

3000: Network controller 4000: Multilevel interconnection network

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to an interconnection technology that connects processor nodes in a large parallel processing computer system. In particular, a multistage interconnection network provides communication paths between processor nodes. Network (MIN) is a multi-level interconnect network that minimizes communication delay time and overcomes this by setting up a different communication path in the event of a switch node failure.

The interconnection network structure connecting multiple processor nodes is one of the very important system design parameters in which the performance of the overall system depends on the topology. That is, the performance of the interconnection network in the data communication path between the processors is relatively stagnant, while very high speed processors appear one after another. The communication delay problem of this interconnect network is a factor that determines the performance of the whole system.

The massively parallel processing system can be roughly divided into a tightly coupled system and a loosely coupled system. The structure to which the interconnection network of the present invention is applied is a weakly coupled type using a distributed shared memory. The general structure is shown schematically in FIG. 1 as a structure in which a plurality of processor nodes owning a system, i.e., distributed shared memory, are interconnected via an interconnection network.

In FIG. 1, the processor node 1000 is a tightly coupled structure within each node, and a weakly coupled structure between the processor nodes 1000. It can be supported by SMP (Symmetric Multi-Processor modules) structure.

Each processor node 1000 may be a board having only one processor as shown in FIG. 1 (a) or one or more processors or local memory as shown in FIG. 1 (b). (local memory), cache (cache), I / O device (I / O device), etc., may be composed of a fully symmetric processing module attached to the interconnect network 4000 through its input / output bus 100 have.

The interconnection network structure 4000 used in such a system is slightly different depending on the connection resources, but here, the structure of the interconnection network 4000 is largely classified into a structure having a static interconnection and a dynamic interconnection. First, a static network uses a direct link that, once configured, is fixed during the execution of a program. This type of interconnect network is a computer that has a predictable or feasible communication pattern with static conncetion. It is suitable for configuring the system. Phases having such characteristics include a ring, a tree, a mesh, a torus, a hypercube, and the like. On the other hand, the dynamic connection network is composed of a plurality of switch channels, which are dynamically configured according to the communication needs of the user program. Topologies with these characteristics include shared buses, crossbars, and multilevel interconnections (MINs). The shared bus architecture is easy to implement, but the limitations of the bus bandwidth make it difficult to scale the system. Crossbar connections guarantee high system performance, but the cost of interconnection networks is too high, making them unsuitable for larger systems.

Multilevel interconnection networks, on the other hand, add cost to the switch at each stage but offer high bandwidth, making them suitable for scaling to large systems. This multistage interconnection network has advantages and disadvantages. Advantages include the ease of expansion of the modular configuration, and disadvantages include that network latency increases in proportion to the number of steps in the network.

However, in the construction of future high-capacity computer systems, some special applications may require a more static phase, but, thanks to the rapid development of optical technology and electronics, large-scale, multi-level interconnects or crossbar networks have become large, general-purpose parallels. The prevailing view is that it will be more economical and easier to construct a dynamic phase in processing computer systems. Such a multi-level interconnection network may have a unidirectional link or a bidirectional link. The bidirectional interconnect network 4000 may include a unidirectional interconnect network 4000 having a unidirectional link, and a second bidirectional interconnect network 4000 having a bidirectional link. To illustrate. In second (a) and (b), processor node 1000 is represented by circles (0,1,2, ... n-2, n-1), interconnect network 4000 is a block diagram, and links are It is shown by the arrow. Although the bidirectional link 100 is disadvantageous in terms of cost, it can be seen that it is a suitable method for connecting several independent processor nodes 1000 due to the simplicity of the communication path and the reduction of communication delay time.

FIG. 3 is a diagram illustrating a multi-level interconnection network (MIN) of the prior art, and a Banyan network is used as a phase of the interconnection network 4000. A Benin network with N inputs and N outputs is interconnected through n stages of switch nodes 2000 of size bxb. Where n = log _b N and the stages are numbered from 0 to n-1. In such a Benin network, there is only one path between any input and output pair. And routing in the network is a self-routing method using a destination tag. These Venetian networks include delta networks, omega networks, and baseline networks, which are topological equivalences. Such a Benin network has only one path between input / output pairs, so if an error occurs in a switch node or link on the path, a fatal result is obtained.

Accordingly, an object of the present invention is to provide a connection network that secures multipath between input / output pairs in a Benin network.

Another object of the present invention is to enable local communication in transmission from adjacent networks to adjacent loads in a switch.

According to the present invention for achieving the above object, in the multi-stage interconnection network, the above-described Bennetian network is used as a basic phase, but a part of its phase is changed to secure multipath between arbitrary pairs of axial force. The change in phase is to ensure that the top level is a folded structure to ensure overlapping paths. By using the folded structure at the top level, it is possible to secure multiple paths to each processor node, and thus data can be transferred through another redundant path even in case of a switch node failure. have.

According to the present invention for achieving the above object, in a multi-stage interconnection network to have a loop-back function at the first stage, a neighbor node connected to the same switch node at the first stage (local node) Communication with neighboring nodes, instead of going to a higher-level stage. This communication is called local communication, and the above-described local communication has a much shorter network delay time than in a general multilevel interconnection network. Without this capability, even local nodes connected to the same switch node in the first stage must traverse to the upper level stage of the multistage interconnection network. To this end, when a communication request occurs in each processor node, the switch node first determines whether the communication is a local communication with the local node through the destination node address included in the header of the transport packet. Then, if the destination node is a local node connected to the same switch as the source node, direct local communication is performed using the first stage loop-back function; otherwise, it is global through the entire network as in the conventional multistage interconnection network. Communicate. As a result, according to the present invention, when local communication exists, network delay time can be improved more effectively than existing multilevel interconnection networks. On the other hand, if there is no local communication at all, it shows the same performance as the conventional multi-stage interconnection network. However, in general, since a large number of local communications exist, on average, the multistage interconnection network of the present invention has a significant performance improvement effect compared to the conventional multistage interconnection network.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

4, the improved multi-stage interconnection network of the present invention, in which the connection between the intermediate stages is a straight line 500 (FIG. 4 (a)) and the improvement of the present invention in the form of a shuffle connection 500 in the connection between the intermediate stages Multilevel interconnection network (FIG. 4 (b)) is illustrated.

As shown, it can be seen that the top stage is folded, that is, the switch node of the top stage is connected to other switches of the same top stage. As described above, the use of the collapsed structure at the top stage increases the number of paths from the switch nodes included in this stage to each processor node, resulting in link conflicts due to excessive message traffic in high-capacity parallel processing computers. It is possible to secure multipaths to effectively deal with the lack of link resources. This multipath has the advantage of being able to send messages through different paths in case of message collision on the link of the highest switch node. In addition, when an error occurs in one switch node, data can be transmitted through another path, thus having considerable error tolerance. Routing at the top switch node first determines if the link on the path (currently above and below the switch node) or the input buffer connected to that link is in use. If in use, routing continues to select any link that is connected to another neighboring switch node that is not in use. The reason for selecting any link connected to the neighbor switch node is that the interconnection network structure of the present invention has a topology connection that can reach its destination regardless of which link is selected. Another reason for this random selection is to avoid overloading any particular link.

4 (a) is a structure in which the intermediate stage has a connection of the straight form 500. This structure eliminates the need for a shuffle connection 400 that is used as a backplane in the realization of phase and simplicity in actual implementation by making the connection between the intermediate switch nodes 2000 in a straight line. However, although there is such a cost advantage, this structure is a system in the case of a failure of a link existing between pairs of switch nodes 2000 interconnected at an intermediate stage or a failure of one of the two switch nodes 2000 pairs. It is a factor that degrades the performance. Therefore, in order to solve this connection problem, the intermediate stage can also be configured to have a shuffle connection. This configuration is shown in FIG. 4 (b) and requires an additional shuffle backplane, but by ensuring redundant paths in the intermediate stage, one switch node 2000 or link can be sufficiently tolerated, thus providing a Maximum performance is still maintained.

The shuffle link used in the present invention uses the following function. Assuming that the entire network is interconnected through n stages of switch nodes 2000 of size bxb with N inputs and N outputs, the number of stages is n = log _b N. For 0≤ⅰ≤n, the input ports b _n-1 .... b ₁ .... b ₀ are connected to the following output ports by the shuffle function S.

S (b _n-1 b _n-2 ..b ₁ b ₀ ) = b _n-2 b _n-3 ..b ₁ b ₀ b _n-1

However, the connection between stages does not always use only shuffle functions. Generally, even if only a few switches in the middle or a part of the connection pattern can be changed, other phases of the homogeneous shape can be made, so the connection pattern having the functional homomorphism with the Bennetian network is included in the scope of the present invention.

Referring to FIG. 5, the connection pattern of the switch node 2000 for use in the improved multistage interconnection network of the present invention is illustrated. In FIG. 5, the 8 x 8 switch node 2000 is illustrated as an example. Of course, the size of this switch node is a system design parameter that can vary depending on the needs of the system designer.

First, FIG. 5 (a) illustrates an omnidirectional connection pattern (a direction from a lower level to a higher level, or a direction from left to right). An input link may be connected to any output port among eight outlets. have. Next, FIG. 5 (b) is a pattern used for data transmission opposite to the previous direction in a reverse connection pattern (a direction descending from an upper level to a lower level or a direction from right to left). 5 (c) is a pattern used only in the switch 2000 of the first stage configured according to the present invention, it is possible to connect from one input to any other input port (in this case, an output port). This loop-back connection ensures efficient local communications.

6 is a block diagram showing in detail the switch node of the improved first stage of the present invention. In FIG. 6, the structure of the switch node 2000 of the first stage is changed to a structure capable of performing a loop-back function which is not present in the conventional switch node 2000. This loop-back function can be achieved by doubling the size of a conventional switch node 2000. In the first stage, the form of routing is local routing, which is communication to the processor node 1000 connected to the same switch node 2000, and global, which is communication to the processor node 1000 on the other switch node 2000. There is global routing, and the switch node 2000 of the first stage should have the ability to distinguish between local routing and global routing. Therefore, there is a routing controller within the first switch node 2000 that can distinguish between local routing and global routing, and a path selector responsible for path selection using signals of the routing controller. And a routing table, a bidirectional FIFO buffer (First in First Out buffer), and the like. In addition to the above functions, the control logic section handles various message routing-related control signals (e.g., request line and grant line), and a back channel to the previous stage. ), A function to send a response signal (ack) should be added. On the other hand, all the switch nodes 2000, including the switch node of the first stage has a self-routing function that can route itself by only the information of the destination included in the header of the message or packet, the switch node 2000 Self-timed interface between other components eliminates the need for a global clock signal, which is especially important for medium to large systems with multiple boards. .

There are two methods for designing a bidirectional switch node 2000 having a loop-back function. The size of the crossbar 200 of the same size is doubled in the dust switch node 2000, and a transmitter / receiver module composed of a transmitter 600 and a receiver 700 is provided on the input side and the output side, respectively. This can be done at the same time, making it possible to have bidirectional and loop-back functions. The crossbar circuit 200 located at the center plays an important role of the crossbar 200 in resolving collisions when a request for connecting the data signals coming from the individual receivers 700 to the transmitters 600 that the receivers 700 require, respectively. to be. Once the header of the message arrives at the receiver 700, the output transmitter 600 is determined by the header. The receiver 700 decodes the output transmitter 600 according to the destination information of the message header and sends and receives a handshaking signal with the transmitter 600 to confirm the connection with the output transmitter 600 and to transmit the data in a timely manner. do. Such a switch configuration method is a switch node design method using a crossbar 200 method.

Another method is to use priority MUX (priority) in the output control logic as a circuit that replaces the role of the crossbar circuit 200 as shown in Figure 6 (b). Each switch uses two identical nodes of actual size (if the size of the switch node 2000 is 8 x 8, the actual implementation will be 16 x 16), one forward-to-bottom communication It is used as a path, and the other is used as a reverse communication path from top to bottom. As a result, bi-directional communication is possible with this configuration, and the first stage needs to have a demultiplexer 10 on the path from bottom to top after the switch stage of the first stage to add the loop-back function. The multiplexer 11 must be placed on the path from the top to the bottom. In the conventional multi-stage interconnection network, there is a problem that the network must be traversed to the highest stage even when communicating with neighboring processor nodes 1000. In the present invention, the demultiplexer 10 is placed after the first stage to separate the routing form of the message. If the communication of the message is local communication, the demultiplexer 10 is used to connect to the switch node 2000 having the same pair of lower paths through the switch node 2000 of the first stage, without continuing to traverse from the current level to the higher path. Direct communication with the processor node 1000 may be provided. In addition, when the communication with the processor node 1000 connected to the other switch node 2000 is performed global routing, the message in the demultiplexer 10 is globally routed when communicating with the node 1000. Continues to advance to the upper level, traversing the network in a self-routing way to the appropriate destination node through the backplane's shuffle connection to reach its destination.

The path selection method is as follows. The switch node 2000 of the first stage obtains the address of the destination node from the message when a communication request occurs in the processor node 1000 connected to the switch and a message is transmitted. The address of the destination node is examined to determine whether the destination node is a local node (node connected to the same switch node 2000 as the source node) or a global node (node other than the local node). If the destination node is found to be a local node, the local node uses the loop-back function in the switch node 2000 of the first stage, and if the destination node is identified as the global node, global communication is performed around the entire network. At this time, the 1-bit selection variable of the demultiplexer 10 uses information of the message header indicating whether local communication or global communication. This loop-back function enables local communication in the first stage, which prevents network traversal that causes only unnecessary traffic in the network, thereby improving the multi-level mutual use of the present invention under the support of an application or an operating system whose locality is sufficiently guaranteed. The performance of the network can be secured with a minimum of hardware and can minimize network delay problems.

7 shows a routing process in a conventional multistage interconnection network. In this case it can be seen that in case of local communication, the whole network is traversed.

FIG. 7 illustrates a method for circuit-connecting the switch board 2000, the processor node 1000, and the shuffle backplane. The message is sent after the line is formed through the connection as shown in the figure.

8 shows a traversal path of a message of a multilevel interconnection network of the present invention. In the case of local communication using network components, it can be seen that the communication path traversing the network is very short.

9 is a block diagram describing routing tag information for routing. The switch node 2000 for routing is, for example, 8 × 8 and supports circuit switched. In the same way as the conventional MIN switching board, the input comes into eight transceivers 600 and 700, and the output comes out of eight transceivers 600 and 700. Each transceiver module 600, 700 sends control packets and data packets from one downlink direction through one 9-bit omnidirectional channel and receives an acknowledgment signal (ACK) through one 1-bit reverse channel. Each switch node 2000 may be connected to any output port from any input port as in the crossbar 200 connection state. The 9-bit omni-directional channel entering the input port contains 8-bit data and 1-bit parity bits. When a message is sent from one processor node 1000 to another processor node 1000, the following procedure is performed. Go through. First, a control packet requesting a circuit setup is sent from the originating node to the destination node. This control packet contains 17-bit destination information. It is delivered within. Each switch node 2000 of the proposed MIN receives a control packet in a buffer and analyzes routing information. The top four bits of routing information are six routing schemes (six routing schemes: shuffle, exchange, unicast (one-to-one), multicast (many-to-many), broadcast (one-to-all), personalized communicat ion (one-to-many), one of which is described in detail in Kai Hwang Advanced Computer Architecture: Paralleism, Scalability, Programmablity, McGraw-hill, 1993. The other part of the routing information is a 1-bit that distinguishes the local / global communication and the other part is used to determine the output transceiver module to be connected. This is done by referencing the routing table. The routing table is an array of 8 x 3 size, which changes the routing information to the corresponding output port. Since each switch node 2000 is 8 x 8 size, the output port can be determined by 3-bit at each switch stage. Once the output port is determined, the connection is attempted there, but the success of the connection is determined by the use of the output port. The device that makes this decision is a path selector with an arbitration function that can accept eight inputs. The path selector detects the connection request from the eight input ports and selects one of them to connect. At this time, multicast has priority over monocast, and the already determined connection state cannot be preempted. When the circuit is successfully formed through all intermediate switches, the control device of the receiving node sends a response signal to the calling node using the reverse channel. When the originating node receives the first response, the line is completely formed and can start sending messages.

FIG. 10 is a block diagram of an interconnection network having redundant steps for error tolerance in relation to the processor node 1000. The switching module of the part where the network operation can be fatal when only a single hardware switch node 2000 is used. This is a duplicate implementation of.

Claims (9)

In a multistage interconnection network providing a mutual communication path between a plurality of processor nodes coupled to its first stage as a multistage interconnection network, each switch belonging to the highest stage of the multistage interconnection network. Multi-level interconnection network, characterized in that nodes are each connected in a folded structure to provide redundant communication paths between the plurality of processors. 2. The multistage interconnection network of claim 1, wherein each of the plurality of processors has a processor, a cache, a memory, an input / output device and an internal bus interconnecting them. A multistage interconnection network, wherein in a multistage interconnection network providing an interconnection path between a plurality of processor nodes coupled to its first stage, each switch node belonging to the first stage of the multistage interconnection network is coupled to the switch node. Upon receiving a communication request originating from the established processor node, determines whether the communication request is a communication request for another processor node coupled to the switch node, and forwards the communication request to a higher stage of the multistage interconnection network. And means for establishing a communication path between the two processors by communicating directly to the other processor node. The multilevel interconnection network of claim 3, wherein each of the plurality of processors includes a processor, a cache, a memory input / output device, and an internal bus interconnecting them. 4. The apparatus of claim 3, wherein the communication path setting means comprises: first crossbar connecting means for delivering the communication request to the upper stage; And a second crossbar connecting means for conveying said communication request to said other processor. 4. The communication path setting means according to claim 3, wherein the communication path setting means comprises a transmit switch node, a demultiplexer, a multiplexer, and a receive switch node, wherein the demultiplexer is configured such that the communication request is coupled to the switch node. According to a result of the determination of whether the request is for a processor node, a connection is selectively established between the transmitting switch node and the upper stage or the demultiplexer, and the multiplexer sets the communication request to the switch node. And selectively establishing a connection between the upper stage or the multiplexer and the switch node according to a determination result of whether or not a communication request for the other processor node is combined. 7. The multistage interconnection network of claim 5 or 6, wherein the intermediate stages of the multistage interconnection network are connected in a straight line. 7. The multistage interconnection network of claim 5 or 6, wherein the intermediate stages of the multistage interconnection network are shuffled. A multilevel interconnection network, wherein a multilevel interconnection network provides an interconnection path between a plurality of processor nodes coupled to its first stage, wherein each switch node belonging to the top stage of the multilevel interconnection network is folded. Coupled to provide redundant communication paths between the plurality of processors; Each switch node belonging to the first stage of the multistage interconnection network receives a communication request originating from a processor node coupled to the switch node, the communication request being directed to another processor node coupled to the switch node. If the communication request is a communication request for another processor node coupled to the switch node, the communication request is forwarded directly to the other processor node instead of the upper stage of the multi-stage interconnection network. And a means for establishing a communication path between the two processors.