KR0164512B1 - The system regulator used in ntsc and pal - Google Patents

Abstract

The present invention discloses an NTSC / PAL cooperative system controller. The system controller for inputting a composite synchronization signal and a predetermined direct current value and outputting a switching signal or a direct current value in accordance with the PAL mode or the NTSC mode. Mode selection means for outputting the first signal in the PAL mode, outputting the second signal in the NTSC mode, PAL signal generating means for outputting the arm signal by inputting the second signal, and NTSC signal by inputting the first signal NTSC signal generating means for outputting, switching signal generating means for outputting a switching signal of a first level when the arm signal is input in response to the composite synchronization signal, and a second level if the arm signal is not input, and a switching pulse when the arm signal is input. And a signal selecting means for outputting a DC value when an NTSC signal is inputted, and the input 1H switch pulse is stably input from the emitter coupling logic and is accurately controlled by the selector to operate the system controller. System control is possible.

Description

NTSC / PAL system controller

1 is a block diagram of a system regulator according to the present invention.

FIG. 2 is a circuit diagram of one preferred embodiment of the present invention of the system regulator shown in FIG.

3A to 3E are timing diagrams of signals output from each of the input and output and switching signal generators shown in FIG.

The present invention relates to a system using both NTSC and PAL, in particular, in the video signal processing of the NTSC / PAL system combined, NTSC / PAL system for modulating the color phase (color phase) for each method A system regulator.

In video signal processing, the difference between the NTSC method and the PAL (phase alternative live) method developed in accordance with the recommendations of the National Tellevision System Committe (NTSC) is in the form of the transmitted signal. . In the NTSC system, the luminance signal Y, the first color difference signal R-Y, and the second color difference signal B-Y are simultaneously transmitted. However, in the PAL method

Send a signal.

In NTSC, the phase difference between the first color difference signal and the second color difference signal is 90 ° and the burst phase is 180 °. However, in the PAL method, the phase difference between the first color difference signal and the second color difference signal is 180 ° per 1H pulse. The burst phase is ± 135 ° per 1H pulse.

Conventional RGB encoders are implemented only by PAL or NTSC, so switching pulses for changing phases are required for each method. Therefore, no system control was needed to control the switching pulse.

However, when the PAL and NTSC schemes are used in combination, a system regulation function is required, and a conventional system regulator for this inputs a 1H switching pulse implemented using charge and discharge of a resistor and a capacitor. However, the voltage that is charged or discharged on the capacitor

Is greatly influenced by the value of the capacitor, and the value of the capacitor changes in the process of removing the actual capacitor. Therefore, the pulse input to the regulator is very unstable, which causes problems in system control. The purpose of the present invention, when used in both NTSC / PAL method to solve the conventional problems as described above, NTSC / PAL method combined system capable of generating a stable and accurate switching pulse to modulate the color phase according to each method To provide a regulator.

In order to achieve the above object, the composite synchronization signal according to the present invention and a predetermined DC value are inputted, and a switching signal or the DC value is output in accordance with the PAL mode or the NTS mode. The PAL / NTSC combined system controller includes mode selection means for outputting a first signal in the PAL mode and outputting a second signal in the NTSC mode, and a PAL signal for outputting an arm signal by inputting the second signal. A generating means, an NTSC signal generating means for inputting said first signal to output an NTSC signal, and said switching signal of a first level if said arm signal is input in response to said composite synchronization signal and a second level if not inputting said switching signal; Switching signal generating means for outputting, and signal selection means for outputting the switching pulse when the arm signal is input, and outputs the DC value when the NTSC signal is input. Do.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the system regulator according to the present invention will be described as follows.

1 is a block diagram of a system controller according to the present invention, a mode selector 10, a PAL signal generator 12, an NTSC signal generator 14, a switching signal generator 16 and a signal selector 18 It consists of.

The mode selector 10 shown in FIG. 1 selects a first signal in the PAL method and a second signal in the NTSC method, and outputs the second signal to the PAL signal generator 12 or the NTSC signal generator 14. do.

The PAL signal generator 12 outputs a signal of the first level to the switching signal generator 16 when the first signal is input, and selects an arm signal having a second level when the second signal is input. Output to section 18. The NTSC signal generator 14 outputs the NTSC signal of the second level to the signal selector 18 when the first signal is input, and selects the signal of the first level when the second signal is input. Output to section 18.

The switching signal generator 16 is the second level when the arm signal is input from the PAL signal generator 12 in response to the complex synchronization signal input through the input terminal IN1, and the switching signal of the first level when the arm signal is not input. Is generated and output to the signal selector 18. The signal selector 18 inputs a predetermined DC value to the input terminal IN2 and a switching signal from the switching signal generator 16 to output a switching signal when a PAL signal is input, and outputs a predetermined DC value when an NTSC signal is input. Output through terminal OUT.

FIG. 2 is a circuit diagram of a preferred embodiment of the system regulator shown in FIG. 1 according to the present invention, which constitutes a D flip-flop 17 and a PAL signal generator 12 implementing the mode selector 10. FIG. Sixth to tenth parts of the first to fifth transistors Q1, Q2, Q3, Q4 and Q5, the first to fifth resistors R1, R2, R3, R4 and R5, and the NTSC signal generator 14. 11th to 16th transistors Q11 and constituting the transistors Q6, Q7, Q8, Q9 and Q10, the sixth to tenth resistors R6, R7, R8, R9 and R10, and the signal selector 18. Q12, Q13, Q14, Q15 and Q16, the eleventh and twelfth resistors R11 and R12, and the switch 10 for implementing the mode selector 10.

The switching signal generator 16 is implemented by a D flip-flop 17 which clocks the composite synchronization reference signal, sets it to the arm signal, and inputs the inverted output thereof to output the switching signal.

The PAL signal generator 12 has a base connected to the output of the mode selector 10 and is connected between a supply power supply Vcc and a ground, and a collector and a supply power supply of the first transistor Q1. A second transistor (Q2) having a base and a collector connected to the base, a base connected to the base of the second transistor (Q2), a third transistor (Q3) connected between the power supply and the ground, a base and a collector connected to each other, and The fourth transistor Q4 connected between the second transistor Q2 and ground, the first resistor R1 connected between the base of the first transistor Q1 and the ground, and between the fourth transistor Q4 and ground. A third resistor R3 connected between the second resistor R2, a third transistor Q3, and the ground, a fourth resistor R4 connected between the second transistor Q2, and a power supply; Base and signal connected between the transistor Q3 and the third resistor R3 and connected to the set terminal of the D flip-flop 17 It is composed of taekbu 18 and the fifth transistor (Q5), and a fifth transistor connected between a fifth resistor (Q5) and ground (R5) having the emitter grounded and the collector is connected are preferred.

The NTSC signal generator 14 has a base connected to the output of the mode selector 10 and a base connected to a power supply and ground, a sixth transistor Q6, a collector of a sixth transistor Q6, and a base connected to a power supply. And a seventh transistor Q7 having a collector, a base connected to the base of the seventh transistor Q7, an eighth transistor Q8 connected between a power supply and a ground, and a seventh transistor having a base and a collector connected to each other. A ninth transistor Q9 connected between Q7 and ground, a sixth resistor R6 connected between the base and ground of the sixth transistor Q6, and a ninth transistor Q9 connected between the ground and the ground; 7 resistor (R7), 8th resistor (R8) connected between the eighth transistor (Q8) and ground, 9th resistor (R9), 8th transistor (Q8) connected between the WP7 transistor (Q7) and the power supply. And a base connected between the eighth resistor R8 and a collector connected to the signal selector 18 It is preferably already composed of the tenth transistor (Q10), and a tenth transistor (Q10) and a tenth resistor (R10) connected between a ground having an emitter.

The signal selector 18 includes an eleventh transistor Q11 having a collector coupled to each other, and an emitter connected to a base and a power supply, an emitter and a signal connected to a base and a power supply connected to the base of the eleventh transistor Q11. A twelfth transistor Q12 having a collector connected to the output of the unit 18, a thirteenth transistor Q13 having a base connected to a direct current value, and connected between a collector of the eleventh transistor Q11 and the tenth transistor Q10; And a fourteenth transistor having an emitter coupled to the thirteenth transistor Q13 and having a base and a collector connected to the twelfth transistor Q12 and connected between the output of the NTSC signal generator 14 and the twelfth transistor Q12. (Q14), the fifteenth transistor (Q15), the fifteenth transistor (Q15) and the emitter having a base coupled to the base of the fourteenth transistor (Q14) and an emitter connected to the collector of the fifth transistor (Q5) Coupled, eleventh transistor The sixteenth transistor Q16 connected between the base of the transmitter Q11 and the collector of the fifth transistor Q5, the eleventh resistor R11 and the twelfth transistor connected between the eleventh transistor Q11 and the power supply. Q12) and the twelfth resistor R12 connected between the power supply.

3A to 3E are timing diagrams of signals output from the input and output and the switching signal generator 16 shown in FIG.

3a or 3a is a composite synchronization signal, 3b is a signal input to the input terminal IN1, 3c is a signal output from the switching source generator 16, 3d is a signal output to the output terminal OUT in the NTSC mode, 3e or Each timing diagram of a signal output to OUT in the PAL mode is shown.

Based on a synchronization signal including equalization pulses, 63.5 kHz for NTSC, and 64 kHz for PAL, a color carrier clock of 3.579545 kHz for NTSC and 4.433 618 kHz for PAL is counted. A 1H pulse (complex synchronization reference signal) shown in FIG. Is generated and input to the clock terminal of the D flip-flop 17. The D flip-flop 17 is set when a high level signal is input to the set terminal, and is reset when a low level signal is input.

When the switch of the mode selector 10 shown in FIG. 2 selects the supply signal Vcc as the first signal, the system controller according to the present invention operates in the NTSC mode, and operates in the PAL mode when grounded.

First, in the NTSC mode, since the first transistor Q1 is turned on and the collector voltage of the second transistor Q2 is grounded, the second, third, four, five, fifteen, and sixteen transistors Q2, Q3, Q4, Q5, Q15 and Q16) are turned off. Thus, a low level PAL signal is output. A high level NTSC signal is output. Therefore, a predetermined direct current value connected to the base terminal of the thirteenth transistor Q13 is output to the output terminal OUT.

In the PAL mode, the sixth transistor Q6 is turned on so that the collector voltage of the seventh transistor Q7 is grounded. 8. 9. 10. 13 and 14 transistors Q7, Q8, Q9, Q10, Q13 and Q14 are turned off. so. A high level PAL signal is output, and a low level NTSC signal is output. Therefore, a switching signal connected to the base terminal of the sixteenth transistor Q16 is output to the output terminal OUT.

As described above, the NTSC / PAL combined system controller according to the present invention has an effect that the 1H switch pulse input is stably input from the emitter coupling logic and can be accurately adjusted by the mode selection means for operating the system controller.

Claims (5)

In the PAL / NTSC combined system controller that inputs a composite synchronization signal and a predetermined DC value, and outputs a switching signal or the DC value in accordance with the arm (PAL) mode or the NTS (NTSC) mode. Mode selection means for outputting a first signal in the PAL mode and a second signal in the NTSC mode; PAL signal generating means for inputting the second signal and outputting an arm signal; NTSC signal generating means for inputting the first signal and outputting an NTSC signal; Switching signal generating means for outputting the switching signal in a first level when the arm signal is input in response to the complex synchronization signal, and in a second level when the arm signal is not input; And a signal selection means for outputting the switching pulse when the arm signal is input and outputting the direct current value when the NTSC signal is input. 2. The apparatus of claim 1, wherein the switching signal generating means includes a D flip-flop that clocks the composite synchronization reference signal, is set to the arm signal, and inputs an inverted output thereof to output the switching signal. NTSC / PAL system controller. 3. The apparatus of claim 2, wherein the PAL signal generating means comprises: a first transistor having a base connected to the output of the mode selecting means and connected between a supply power source and a ground; A second transistor having a base and a collector connected to the collector and the power supply of the first transistor; A third transistor having a base connected to the base of the second transistor and connected between the power supply and ground; A fourth transistor having a base and a collector connected to each other and connected between the second transistor and ground; A first resistor connected between the base of the first transistor and a ground; A second resistor connected between the fourth transistor and ground; A third resistor connected between the third transistor and ground; A fourth resistor connected between the second transistor and the power supply; A fifth transistor having a base connected between the third transistor and the third resistor and a set terminal of the D flip-flop, a collector connected to the signal selecting means, and an emitter grounded; And a fifth resistor connected between the fifth transistor and the ground. 2. The apparatus of claim 1, wherein the NTSC signal generating means comprises: a sixth transistor having a base connected to the output of the mode selecting means and connected between a supply power source and a ground; A seventh transistor having a base and a collector connected to the collector and the power supply of the sixth transistor; An eighth transistor having a base connected to the base of the seventh transistor and connected between the power supply and ground; A ninth transistor having a base and a collector connected to each other and connected between the seventh transistor and ground; A sixth resistor connected between the base of the sixth transistor and a ground; A seventh resistor connected between the ninth transistor and ground; An eighth resistor connected between the eighth transistor and ground; A ninth resistor connected between the seventh transistor and the power supply; A tenth transistor having a base connected between the eighth transistor and the eighth resistor, a collector connected to the signal selecting means, and an emitter grounded; And a tenth resistor connected between the tenth transistor and the ground. 5. The apparatus of claim 4, wherein the signal selecting means comprises: an eleventh transistor having a collector coupled to each other, and an emitter connected to a base and a power supply; A twelfth transistor having a base connected to the base of the eleventh transistor, an emitter connected to a supply power supply, and a collector connected to an output of the signal selection means; A thirteenth transistor having a base connected to the DC value and connected between the eleventh transistor and the collector of the tenth transistor; A fourteenth transistor coupled to the thirteenth transistor and having a base and a collector connected to the twelfth transistor, and connected between an output of the NTSC signal generating means and the twelfth transistor; A fifteenth transistor having a base coupled to the base of the fourteenth transistor and an emitter connected to the collector of the fifth transistor; An sixteenth transistor coupled to the fifteenth transistor and coupled between the base of the eleventh transistor and the collector of the fifth transistor; An eleventh resistor connected between the eleventh transistor and a power supply; And a twelfth resistor connected between the twelfth transistor and the power supply.