KR0162767B1 - Parallel processing apparatus for multi-channel data processing of serial communication lines - Google Patents

Abstract

The present invention relates to a parallel processing apparatus for multi-channel data processing of a serial communication path, and in particular, the data processed at a high speed by an internal upper processor to an external pulse code modulation (PCM) path, and vice versa. In order for a processor to process data received in the PCM path at high speed, a number of dedicated processors not only share the functions of the upper processor but also perform communication functions in the PCM path. In addition, the arbitration processor performs a communication function between the host processor and the dedicated processor, and the arbitration processor and the dedicated processor according to an asynchronous serial communication protocol (EIA-232 commonly referred to as RS-232) for maintenance functions such as debugging. The present invention relates to a parallel processing apparatus for processing multi-channel data of a serial communication path (PCM path, asynchronous serial communication path such as EIA-232) that communicates with an external terminal (dummy terminal or personal computer).

Description

Parallel Processing Unit for Multi-channel Data Processing of Serial Communication Path

1 is a block diagram of a parallel processing apparatus for multi-channel data processing of a serial communication path according to the prior art.

2 is a block diagram of a parallel processing apparatus for processing multi-channel data in a serial communication path of the present invention.

3 is an exemplary view of an arbitration and state management unit in FIG.

4 is a serial communication path of the arbitration processor unit and the dedicated processor unit in FIG.

FIG. 5 is a diagram illustrating one embodiment of a dedicated processor unit in FIG. 2; FIG.

6 is an exemplary view of a clock generator used in FIG.

7 is an exemplary view of an RS-232 matching unit in FIG. 2.

The present invention relates to a parallel processing apparatus for multi-channel data processing of a serial communication path, and in particular, the data processed at a high speed by an internal upper processor to an external pulse code modulation (PCM) path, and vice versa In order for a processor to process data received in the PCM path at high speed, a plurality of dedicated processors not only share the functions of the upper processor but also perform communication functions in the PCM path, and an arbitration processor is dedicated processor with the higher processor. The present invention relates to a parallel processing apparatus for processing multi-channel data in a serial communication path in which an arbitration processor and dedicated processors perform asynchronous serial communication with an external PC (Personal Coumputer) to perform a communication function and to maintain a debugging function. .

The serial communication path refers to the PCM path, which is a synchronous serial communication path, and the EIA-232 (commonly called RS-232) path, which is an asynchronous serial communication path.

In addition, the upper processor integrates an external bus and sends the input packet data to the dedicated processor through the arbitration processor, and the dedicated processor processes the packet data with a predetermined algorithm and loads the packet data in a predetermined time slot (TS) of the PCM path. send.

At the same time, the upper processor processes the PCM data received in the predetermined TS of the PCM path with the algorithm and then sends the PCM data to the upper processor through the arbitration processor.

For example, an arbitration processor controls the data flow between one higher processor and multiple dedicated processors.

Mobile communication networks differ from existing fixed telephone networks in that they use wireless channels instead of subscriber lines and subscribers move.

Since the radio frequency used by a mobile communication network is limited, a large area is divided into small areas called cells, and a specific frequency used in one cell is repeatedly used in another cell.

Thus, wireless communication is established between a base station and a mobile station (mobile station or subscriber) by having a base station in one or more cells, so that a call can be continued without interruption even when moving between cells during a call. To do this, we need a special service called handoff. In order to implement such a handoff service, a selection function for selecting voice data from two or more cells is required.

In order to be advantageous in terms of frequency utilization efficiency of the wireless channel, the 64Kbps (Kilo-bits / second) Pulse Code Modulation (PCM) coding method used in fixed telephone networks is not applied to the coding of voice signals of a mobile communication network. A coding method of a transmission rate (for example, about 8 kilobits per second or less) is applied.

However, since the encoding schemes are different in this way, a mobile subscriber and a fixed subscriber (refering to a conventional general telephone user) need a function of transcoding (transcoding).

The multi-channel data of the conventional structure (application number 1994-36357, application date: December 23, 1994, name: P. C. M. path) for the convenience of maintenance while simultaneously implementing the selecting function and the transcoding function A structure different from the parallel processing apparatus (hereinafter, referred to as an existing structure) is required.

As shown in FIG. 1, the main function block of the conventional structure is that the upper processor unit 1 of this structure is implemented by a general-purpose microprocessor (for example, Motorola MC68030) widely used in a communication processing device, so that the debugging environment is relatively low. Although well-known, the microprocessor used in the arbitration processor unit 2 and the dedicated processor unit 3 is implemented as a special purpose digital signal processing processor, so that the debugging environment is not as good as that of the upper processor unit 1.

In other words, since the arbitration processor unit 1 and the dedicated processor unit 3 are hardly supported by maintenance tools such as debugging other than the program development emulator, the arbitration processor unit 1 and the dedicated processor unit 3 may be generated during the integrated test of the mobile communication network. There is a very difficult problem in identifying and correcting abnormal phenomena.

Accordingly, an object of the present invention is a structure having an RS-232 matching unit to solve the above problems, the multi-channel data of the serial communication path to facilitate the maintenance while simultaneously implementing the selecting function and the transcoding function It is to provide a parallel processing apparatus for the treatment.

Technical features of the present invention for achieving the above object, the two types of processors each independently perform a high load function while at the same time smooth communication with each other and combined with an external next-order processor and an external time switch to provide a communication function For the convenience of development, the PCM matching means for transmitting and receiving with an external time switch for monitoring and controlling the communication state, and receiving the clocks for PCM data communication from the PCM matching means for the clocks used by the dedicated processor means and the arbitration processor means. It is used to generate and send to each of the used clock generation means, and transmits and receives packet data with the external next higher processor, and analyzes the packet data to find the dedicated processor data or status-related data and send it to the upper communication means, received from the upper communication means Using dedicated processor data Assemble the packet data, perform the related functions when analyzing or assembling the packet data, and receive the arbitration processor operation signal from the arbitration processor state management means and send the state related data to the upper communication means to control the arbitration processor means. Main processor means for performing mainly, upper communication means for transferring dedicated processor data operation maintenance data between the upper processor means and the arbitration processor means, and arbitration and state management means mainly for transferring the dedicated processor data upward or downward. Access the upper communication means and lower communication means, and control the arbitration and state management means for arbitrating the serial communication signal line to transfer the program to be executed by the dedicated processor means to the dedicated processor means, Operational Maintenance Data An arbitration processor means for reading the operation state data of the dedicated processor means from the arbitration and state management means and sending it to the upper communication means, receiving the PCM data communication clocks from the use clock generation means, and transmitting and receiving the PCM data to the PCM matching means; And a lower communication means for transferring dedicated processor data between the state management means and the arbitration processor means, and the upper and lower communication means selected by the higher communication means or the lower communication means under the control of the arbitration processor means. Mediation and status management means for allowing access to the lower communication means by the dedicated processor means under the control of the arbitration processor means, and for arbitrating serial communication between the arbitration processor means and the dedicated processor means; Special features of arbitration processor means; By processing the arbitration processor state management means for receiving the signal from the arbitration and state management means and whether the normal status presence signal of the arbitration processor means to the upper processor means, and mainly processing the dedicated processor data received from the arbitration and state management means in accordance with the prescribed method The PCM data is made into PCM data by means of the clock signal received from the use clock means, and is sent to the PCM matching means assigned to each dedicated processor.In contrast, the PCM data received from the PCM matching means is processed according to a predetermined method. RS-232 matching means for synchronous serial communication with dedicated processor means, and an asynchronous serial communication with an external terminal, and the arbitration processor means and dedicated processor means are sent through the arbitration and state management means. With It is characterized by.

As described above, the present invention loads data processed at a high speed by an internal upper processor to an external pulse code modulation (PCM) path, and on the contrary, the upper processor processes a plurality of data in order to process data received at the PCM path at high speed. The dedicated processor of not only shares the functions of the upper processor but also performs a communication function through the PCM path.

In addition, the arbitration processor performs a communication function between the host processor and the dedicated processor, and the arbitration processor and the dedicated processor according to the asynchronous serial communication protocol (commonly referred to as EIA-232 RS-232) for maintenance functions such as debugging. The present invention relates to a parallel processing apparatus for processing multi-channel data of a serial communication path (PCM path, asynchronous serial communication path such as EIA-232) that communicates with an external terminal (dummy terminal or personal computer).

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a schematic overall configuration according to the present invention, the upper processor unit 11 unpacketizes the packet data transmitted by the external next higher processor through the external bus, and the contents corresponding to the self are directly carried out. Dedicated processor unit 13 (hereinafter, referred to as dedicated processor data) is sent to the arbitration processor unit 14 through the upper communication unit 12, and the mediation processor 14 sends the higher communication unit 12 in the opposite direction. Receives the dedicated processor data sent through the packet data to create or perform their own judgment (such as state management), and receives a signal from the arbitration processor state management unit 15 directly reset signal to the arbitration processor unit 14 Gives.

The arbitration processor unit 14 sends the state of the dedicated processor unit 13 read from the arbitration and state management unit 16 to the upper processor unit 11 through the upper communication unit 12, or sends the dedicated processor unit 13 to. Access the arbitration processor address bus and data bus to the arbitration and status management unit 16 to arbitrate access to the lower communication unit 17 to communicate with the arbitration processor unit 14. Send and receive serial data to and from the dedicated processor unit 13 through the state management unit 16, and when the arbitration and state management unit 16 collects and sends individual interrupt signals sent by the dedicated processor of the dedicated processor unit 13, the arbitration processor unit 14 directly receives the integrated interrupt signal, and exchanges dedicated processor data with the dedicated processor unit 13 through the lower communication unit 17 and the arbitration and state management unit 16.

In addition, asynchronous serial communication is performed with the RS-232 matching unit 18.

The arbitration processor state management unit 15 transmits to the upper processor unit 11 a normal state presence signal of the arbitration processor unit 14 generated by receiving a specific signal of the arbitration processor unit 14 from the arbitration and state management unit 16.

The arbitration and state management unit 16 selects the upper communication unit 12 or the lower communication unit 17 under the control of the arbitration processor unit 14, so that the arbitration processor unit 14 selects the upper and lower communication units 12 and 17. To access the sub-communication unit 17 under the control of the arbitration processor unit 14, and to access the lower communication unit 17. The arbitration processor unit 14 and the dedicated processor unit 13 To allow serial communication.

In addition, the RS-232 matching unit 18 is activated or deactivated under the control of the arbitration processor unit 14 because the serial ports of the processors of the arbitration processor unit 14 and the dedicated processor unit 13 have two ports. It is used for one purpose, because it should be used for only one use at any given time.

In other words, whether the serial port is used for communication between the arbitration processor unit 14 and the dedicated processor unit 13 or for communication between external terminals, the control signal of the arbitration and state management unit 16 and the arbitration processor unit 14 Serial communication data is determined.

The dedicated processor unit 13 processes the dedicated processor data received from the arbitration and state management unit 16 according to a predetermined method, converts the dedicated processor data into PCM data, and sends the data to the PCM matching unit 19 through the serial port. The PCM data received through the serial port from 19) is processed according to a predetermined method, and is made into dedicated processor data and sent to the arbitration and state management unit 16.

In addition, the serial data of the arbitration processor unit 14 through the arbitration and state management unit 16 through the other serial port (program when booting, other general data) can be transmitted and received or the RS-232 matching unit ( 18) Send and receive data of an external terminal.

The PCM matching unit 19 allows the external time switch and the dedicated processor unit 13 to transmit and receive PCM data, and sends it to the generation unit 20 using the PCM data communication clocks received from the external time switch.

The use clock generation unit 20 uses the PCM data communication clocks received from the PCM matching unit 19 or local clock generator clocks to make clocks that the dedicated processor unit 13 and the arbitration processor unit 14 can use. It sends to each, and generates a clock for the asynchronous serial communication based on the local generator clock to the RS-232 matching unit 18.

Transmit PCM related clocks in case of configuring test equipment in combination with external subscriber board.

The RS-232 matching unit 18 performs analog asynchronous serial communication with an external terminal (PC or dummy terminal), and performs synchronous serial communication with the arbitration processor unit 14 and the dedicated processor unit 13.

3 is an embodiment of the arbitration and state management unit 16, which is implemented as an electrically programmable logic device (EPLD), and has an address bus (CAB ^{15 to 0} ) and a data bus (CDB ^{15 to 0} ). It is connected to the control signal of the arbitration processor and the serial communication signal of the arbitration processor.

And the arbitration and state management unit 16 is connected to the lower communication unit 17 by the data bus (DDB ^{7 ~ 0} ), the address bus (DAB ^{10 ~ 0} ), the lower communication control signal, the upper communication unit 12 and the upper communication control Signal (chip selection signal, busy signal), and the dedicated processor unit 13 is connected to the address bus (DAB_0 15,8, ^{5 ~ 0} , DAB_1 15,8, ^{5 ~ 0} ) and data bus (DDB_0 ^{7). ~ 0, DDB_1 7 ~ 0)} , the first and second co-processor is connected to communication control signal line.

In this case, the control signal line for the first and second dedicated processor communication is one of two pairs of serial ports of a parallel memory data memory strobe, a ready signal, and a dedicated processor, and is synchronized with the RS-232 matching unit 18. It is connected by serial signal.

At this time, the serial signal is a pair of serial signals, one is a serial signal for the arbitration processor, the other is a serial signal connected to one of the first and second dedicated processors.

Here, the arbitration processor establishes both paths ((1)-(2)-(3) paths in Fig. 4) for serial communication with the first and second dedicated processors, or RS-232 matching for operation status input and output. It is decided whether to set the sub-path ((1)-(4) or (3)-(4) path of FIG. 4).

At this time, when the arbitration processor and the dedicated processor communicate serially, the communication path between the arbitration and state management unit and the RS-232 matching unit 18 is disconnected, and when the arbitration processor and the dedicated processor want to communicate with the external terminal, respectively, RS-232 The matching unit 18 communication path is set.

At this time, the arbitration processor maintains a dedicated RS-232 communication path ((1)-(4) path of FIG. 4), and the dedicated processor RS-232 communication path is only one dedicated processor RS-232 under the control of the arbitration processor. The communication path ((3)-(5) path in FIG. 4) can be used.

FIG. 5 is an exemplary view of the dedicated processor unit 13, and may include a plurality of dedicated processors. Here, an example of using two dedicated processors will be described.

The first dedicated processor includes an arbitration and status management unit, an address bus (DAB_0 15,8, ^{5 ~ 0} ), a data bus (DDB_0 ^{7 ~ 0} ), a control signal line (data strobe, read / write signal) for the first dedicated processor communication, 1 dedicated processor is connected to the serial communication signal line (transmit, receive), and receives the serial communication signals (HCLK, HFS_0) from the use of the clock generation, and at the same time connected to the PCM matching unit and PCM data transmission and reception lines (HDX, HDR). A PCM data transceiver can be used by an arbitration processor and a dedicated processor, but can only send and receive PCM data in its own timeslot.

In other words, one of the two serial ports of the dedicated processor is used for PCM data communication, the other is used for arbitration processor communication or external terminal communication, and the clocks for serial communication all use HCLK.

Similarly, the second dedicated processor is connected to the arbitration and status management unit and the signal lines DAB_1 15, ⁸ , ^{5 to 0} , DDB_1 ^{7 to 0} , the second dedicated processor control signal line, and the first dedicated processor serial communication signal line. From 20, serial communication signals HCLK and HFS_1 are received.

FIG. 6 is an exemplary view of the clock generator 20, which is implemented as an EPLD (Electrically Programmable Logic Device), a switch, a clock generator, a differential signal transmitter, and the like by a local clock generator 22. 21 or use the local clocks (CLK, FS) received from the PCM matching unit 19 or the PCM data communication clocks HCLK, HFS_0, HFS_C, CLK_TEST, It is determined whether to supply FS_TEST).

RS-232 sends HCLK for synchronous serial communication and 9600 Hz CLK_232 for asynchronous serial communication.

As the differential signal transmitter 23, 75174, 96174 and the like are used.

7 is an exemplary view of the RS-232 matching unit 18, which is implemented as an EPLD and an analog matching element, receives clocks CLK_232 and HCLK from the clock generator 20, and provides an arbitration and state management unit ( 16) Send and receive synchronous serial communication call of doubling processor and dedicated processor, send and receive 'external terminal-mediation' and intermediary processor analog serial communication signal, and send and receive 'external terminal-only' and dedicated processor analog serial communication signal do.

The main configuration block of the present invention is composed of the upper processor unit, upper and lower communication unit, arbitration processor unit, dedicated processor unit, PCM matching unit, arbitration processor state management unit, use clock generation unit, arbitration and state management unit, etc. The functional block may be implemented as a general-purpose microprocessor, a dedicated processor, an EPLD, a GAL, a TTL gate, a memory device, a communication integrated circuit, a crystal oscillator, a passive device, or the like.

The present invention as described above has the following effects.

First, when the load of function performance is very high ( ^30-40 MIPS (mega-instructions per second)), two types of different functions are performed simultaneously, and each function has a relatively small amount of data (e.g., 8 Kbps). (Kilo-bits per second), the two functions can be implemented economically at the same time.

Second, there is an effect of asynchronous serial communication for the maintenance function.

Claims (1)

When two types of processors perform each function with high load independently and at the same time, they can communicate smoothly with each other and monitor and control the communication status for convenience of development when it is combined with an external next-order processor and an external time switch. PCM matching means for transmitting and receiving to and from an external time switch, and a clock generation means for receiving the PCM data communication clocks from the PCM matching means and generating clocks used by the dedicated processor means and the arbitration processor means and sending them to each other; While transmitting and receiving packet data with the processor, the packet data is analyzed and the dedicated processor data or state related data is found and sent to the upper communication means, the packet data is assembled using the dedicated processor data received from the upper communication means, and the packet data Analyze or tune And a higher processor means for performing related functions and mainly sending the state related data for controlling the arbitration processor means to the upper communication means by receiving the arbitration processor operation signal from the arbitration processor state management means. The upper communication means for transferring the dedicated processor data and the operation maintenance data between each other and the arbitration processor means, and the upper communication means and the lower communication means by controlling the arbitration and state management means mainly for transmitting the dedicated processor data upward or downward. Control the arbitration and state management means for arbitrating serial communication signal lines to transfer the program to be executed by the dedicated processor means to the dedicated processor means, and according to the operation maintenance data from the upper communication means. Dedicated processor means Arbitration processor means for reading and sending the operating state data of the PCM data to the upper communication means, receiving clocks for PCM data communication from the use clock generation means, and transmitting and receiving PCM data to the PCM matching means, between the arbitration and state management means and the arbitration processor means. The lower communication means for transferring the dedicated processor data to each other and the upper communication means or the lower communication means are selected according to the control of the arbitration processor means so that the arbitration processor means can access the upper and lower communication means. Arbitration and status management means for allowing dedicated processor means to access subordinate communication means under control of the means, and for arbitrating serial communication between the arbitration processor means and the dedicated processor means; When received from the state management means Arbitration processor state management means for sending the normal status existence signal of the Kindle arbitration processor means to the upper processor means, and the dedicated processor data received from the arbitration and state management means is processed into a PCM data by processing according to a predetermined method, and the clock received from the use clock means. Dedicated PCs are sent to the PCM matching unit in the time slots assigned to each dedicated processor, and, on the contrary, PCM data received from the PCM matching unit is processed according to the specified method, and made into dedicated processor data and sent to the arbitration and state management means. A serial communication path comprising: an RS-232 matching means for synchronous serial communication with a processor means, and an analog asynchronous serial communication with an external terminal, and with the arbitration processor means and a dedicated processor means with an arbitration and state management means. Multichannel de Parallel processing apparatus for processing emitter.