KR0162346B1 - Two screen receiver of a wide tv - Google Patents

Abstract

The present invention relates to a wide-screen two-screen display device, which conventionally uses a field memory or a frame memory for both an image signal input portion and an output portion, and the field memory is expensive, causing a considerable material cost increase. There is a problem of reducing the deterioration of the vertical resolution caused by the deduction at 2: 1 in the two-screen configuration.

Accordingly, the present invention to solve the above problem is to screen the aspect ratio converter (hereinafter referred to as ARC) function to effectively zoom (ZOOMING) to reduce the number of field memory to simplify the hardware.

Description

Widescreen TV Display

1 is a block diagram of a conventional widescreen TV.

2 is a block diagram of a widescreen TV having a wide aspect ratio conversion (ARC) function of the present invention.

3 is a detailed configuration diagram of a screen aspect ratio conversion (ARC) unit in FIG. 2;

4 is a timing diagram of an output signal at 4/3 and 3/2 zooming in FIG.

5 is a detailed circuit of the coefficient control unit in FIG.

6 is a detailed circuit diagram of a scanning line interpolation unit in FIG.

FIG. 7 is an explanatory diagram showing a process example at the time of scanning line interpolation in FIG.

(a) is explanatory drawing at the time of 4/3 zooming,

(b) is explanatory drawing at the time of 3/2 zooming.

8 is a block diagram of a widescreen TV of a widescreen TV having an independent aspect ratio conversion (ARC) function of the present invention.

9 is a block diagram of a widescreen TV having a common aspect ratio conversion (ARC) function of the present invention.

10 is a detailed configuration diagram of a screen aspect ratio conversion unit in FIG. 9;

11 is a detail of the line counter in FIGS. 3 and 10. FIG.

FIG. 12 is a diagram illustrating an internal configuration of a scan line interpolation unit using the interpolation coefficients of the radix field and the even field when the video signal is interlaced.

(a) is the explanatory diagram for 4: 3 interpolation

(b) is the process explanatory diagram in 3: 2 interpolation.

13 is a process explanatory diagram at the time of interpolation of the interlaced scanning signal.

* Explanation of symbols for main parts of the drawings

300: scan line processing unit 400: first field memory

500: second field memory 600: multiplexer

700: monostable multivibrator 801,802,804,805: field memory

807: luminance signal multiplexer 808: color signal multiplexer

The present invention relates to an optical device that can simultaneously perform an aspect ratio converter (ARC) function and a double window (Double Window) function, and simultaneously simplify hardware configuration by reducing the number of field memories. The present invention relates to a widescreen two-screen display device for efficiently processing a zooming function of a screen to simplify hardware configuration and to reduce deterioration of image quality in a two-screen configuration.

As a block diagram of a conventional widescreen two-screen display device, as shown in FIG. 1, a horizontal synchronous signal (H-SYNC) and a vertical synchronous signal (H-SYNC) are input by receiving a first image signal input through an input terminal. V-SYNC) and the synchronous separator 6 for outputting the separated synchronous signal, and the write of 910f _H during one period of the horizontal synchronous signal H-SYNC separated from the synchronous separator 6; A clock generator 8 generating the clock WR and a frequency of the light clock WR generated by the clock generator 8 are multiplied by 2 times 1820f _H and outputted as the light clock RD. A double flip-flop 9, a flip-flop 7 for outputting a read / write signal R / W in which a clock is synchronized with the horizontal synchronization signal of the synchronization separator 6, and a second screen for displaying two screens. First and second analog (A) / digital (D) converters 11 and 21 for converting the first video signal and the second video signal into digital video data, respectively, and outputting the same. In order to match the aspect ratio of the screen, the digital image signals input through the first and second analog / digital converters 11 and 21 are sequentially stored in each field, and the stored image data are output one line per horizontal scanning period. First and second field memories 12 and 22 and first and third line memories 13 and 23 for storing image data stored in the first and second field memories 12 and 22 every line. And second and fourth line memories 14 and 24 which receive previous image data stored in the first and third line memories 13 and 23 and store every line, and the first and third lines. First and second receivers 16 and 26, which receive and multiply a predetermined coefficient value (1-k) to image data input line by line from the memory 13, 23, and the second and fourth line memories ( 14 and 24, the second and fourth multipliers 15 and 25 multiplying the input image data by one line from the 24 and the first and third multipliers 16 and 26, respectively. Obtained current First and second summers 17 and 27 for summing the video data and the previous video data obtained from the second and fourth multipliers 15 and 15 to output the first and second video signals with interpolated scan lines; The first image signal is received with the horizontal synchronization H-SYNC and the vertical synchronization V-SYNC separated by the synchronization separator 6 with respect to the second image signal having the scan line interpolated through the second summer 27. Scan lines are projected by the first and second summers 17 and 27 according to the third field memory 29 and the read / write signal R / W of the flip-flop 7 to match the synchronization of 5 and 6 line memories 18 and 28 which are synchronized to the light clock WR and the read clock RD with respect to the first and second video signals, and are stored every line to make the two video signals into two screens. ), and a clock lead (RD) to 910f divided by _H, and the divided output of the T flip-flop receives input and selection generating and outputting a selection signal for selecting the display signal generating section 40, the selection signal to A selection unit 19 for selecting the fifth line memory 18 or the sixth line memory 28 according to the selection signal generated by the unit 40, and the fifth and sixth units by the selection unit 19; The frame memory 20 for storing the output of the line memories 18 and 28 in units of frames so that two screens can be configured, and the upper and lower portions of the horizontal synchronization H-SUNC when forming two screens are 1 /. In order to count the remaining 6 bits and put them in the blanks, the scan line counter 32 which outputs the counted value to the frame memory 20 and the address value of the write clock WR are counted and the address counter (33), a squarer (34) for doubling the output of the address counter (33), and an address signal for the screen configuration of the frame memory (20) through the address counter (33) or normal output again. An address signal generator (3) for selecting and outputting any one of the outputs 5) and one of the first and second video signals whose scan lines are converted by the first and second summers 17 and 27 or the two screens of the frame memory 20 to select the digital / analog converter 37. The screen selector 36 is configured to output the data.

Looking at the prior art configured in this way in detail as follows.

In the conventional TV receiver having a 16: 9 aspect ratio of a conventional screen, a scan player conversion for viewing lines in a zoom mode of 4: 3 is first performed by first and second video signals for displaying two screens. When the signals are input to the first and second analog / digital converters 11 and 21, respectively, the video signals are converted into digital data so as to fit the aspect ratio of the screen to the first and third field memories 12 and 22. Digital image data of 3 is sequentially stored in every field, that is, skipped and stored one by three lines.

The reason is that one scanning line is increased every three horizontal lines, and the number of main runner lines is four-thirds. Therefore, the horizontal scanning lines are continuously delayed by one line every four lines to the field memory.

In this case, when the synchronization separator 6 separates the horizontal synchronization H-SYNC and the vertical synchronization V-SYNC from the input first video signal, the synchronization separation unit 6 outputs the horizontal synchronization signal once every horizontal scanning period. The lines are supplied from the first and second field memories 12 and 22 to the first and third line memories 13 and 23, respectively.

Then, the first and third line memories 13 and 23 sequentially store digital image data input by skipping one line every three lines from the first and second field memories 12 and 22, and The stored image data is 4 lines again and output to the second and fourth line memories 14 and 24 and the first and second worshipers 16 and 26, respectively.

Accordingly, the second and fourth line memories 14 and 24 delay the input digital image data by one line and output the delayed lines to the third and fourth multipliers 15 and 25.

Accordingly, the first and second multipliers 16 and 26 and the third and fourth multipliers 15 and 25 may include the first and third line memories 13 and 23 and the second and fourth line memories 14 ( The digital video data inputted from 24) is multiplied by the predetermined coefficient values (1-k) and k, respectively, and the result of the multiplication is output to the first and second summers 17 and 27.

The summers 17 and 27 add image data input from the first and second multipliers 16 and 26 and the third and fourth summers 15 and 25, and the new scan lines obtained by the addition are interpolated. The first image data is output to the fifth line memory 18 and the second image data is output to the third field memory 29.

In this case, the image data output from the first and second line memories 13 and 14 may be interpolated by interpolating scan lines while changing weights in four types as the interpolation coefficients (1-k) and (k) change. Make it up

That is, if the interpolation coefficient (K) is 1, 1-K becomes 0. If the interpolation coefficient (K) is 1/4, 1 / 2,1, 1-k changes to 3/4, 1 / 2,0, respectively. Accordingly, since the sum of the coefficients multiplied by the first and third multipliers 16 and 26 to the output image data of the first and second line memories 13 and 14 is always 1, there is no change in the image data.

On the other hand, the reason why the second image data having the scan line interpolated is not directly stored in the sixth line memory 28 but passed through the third field memory 29 is to match the first image data with the horizontal synchronization.

That is, the second image data is stored in the third field memory 29 in accordance with the horizontal synchronization H-SYNC and the vertical synchronization V-SYNC separated by the synchronization separator 6.

The two image data in which the horizontal synchronization H-SYNC and the vertical synchronization V-SYNC coincide are stored one line each in the fifth and sixth line memories 18 and 28 to make two screens.

At this time, the read clock RD and the write clock WR input to the fifth and sixth line memories 18 and 28 are clocks for receiving the horizontal sync H-SYNC separated by the synchronization separator 6. The generator 8 generates a clock having a frequency of 910f _H during the horizontal scanning period, which is called a light clock WR.

The multiplier 9 is input to the light clock WR to output a clock having a 1820f _H frequency obtained by multiplying the frequency of the light clock as the read clock RD.

Therefore, the light clock WR input to the fifth and sixth line memories 18 and 28 is 910f _H , whereas the lead clock RD is 1820f _{H which} is multiplied by two times the light clock WR. The horizontal image signal is read out in one horizontal period, and the mode selection by the light clock WR and the read clock RD causes the fifth and sixth line memories 18 and 28 to change in the same manner.

In the same manner as described above, while the fifth and sixth line memories 18 and 28 are in the read mode, the input data is ignored, so that the total number of lines is zoomed (525 × 4/3). This becomes half of 525 × 4/3 × 1/2 = 525 × 2/3, which is (9 × 2/3 =) 6 toward the vertical side of the 16: 9 screen.

In other words, the display of two 4: 3 screens on a 16: 9 screen is the same as the result of decrementing the shot player 2: 1 on the zoomed screen.

When the divider 30 divides the input lead clock RD to 910 and outputs it to the flip-flop 31, the tip-flop 31 is a selection signal for selecting a screen synchronized with the input signal. It is output to the selector 19.

Accordingly, the selector 19 alternately selects the outputs of the fifth line memory 18 and the sixth line memory 28 in response to the selection signal, and outputs the selected image data to the frame memory 20. In this case, the frame memory 20 constitutes two screens.

Here, the write and read speeds of the frame memory 20 are the same as those of the write clocks of the 910f _H fifth and sixth line memories 18 and 28, and when the output of the address counter 33 is read twice, each screen is read. The number of pixels on the horizontal scan line is halved again to 455, and when it is combined with two screens, it becomes 910, so that one normal horizontal scan line is formed.

When the two screens of the scan line counter 32 are configured, the upper and lower portions of the horizontal synchronization H-SYNC are left by 1/6, respectively, so that they are counted and left blank.

Accordingly, when the screen selector 36 selects one of the interpolated first video signal, the two-screen video signal, and the interpolated second video signal, and outputs it to the digital / analog converter 37 as necessary, The digital / analog converter 37 converts the analog video signal to be displayed on the screen.

However, in the conventional technology as described above, in the field memory or frame memory should be provided at both the video signal input portion and the output portion, there is a problem of causing a considerable material cost increase due to the use of expensive field memory. There is a problem of reducing the deterioration of the vertical resolution caused by decrementing to 2: 1 in the two-screen configuration.

Accordingly, an object of the present invention to solve the above problems is to screen the aspect ratio (Aspect Ratio Converter, hereinafter referred to as ARC) function to effectively zoom (ZOOMING) to reduce the number of field memory to simplify the hardware One broad object is to provide a two-screen display device.

It is another object of the present invention to provide a widescreen two-screen display device for simplifying a hardware configuration while simultaneously performing a screen aspect ratio conversion (ARC) function and a two-screen function.

In the wide screen display device of the present invention for achieving the above object, as shown in FIG. 2, the screen aspect ratio is obtained by receiving a first video signal for displaying the two screens and performing zooming. A first screen aspect ratio converter 100 for adjusting, a second screen aspect ratio converter 200 for receiving a second video signal for displaying two screens and performing a zooming process to adjust the screen aspect ratio, and the first image A scan line processing unit 300 for generating and outputting a read clock RD and a screen selection signal MUX SEL for reading image data from the field memory with the horizontal synchronization H-SYNC of the signal; First and second field memories 400 and 500 respectively storing image data whose aspect ratio is converted from the second screen aspect ratio changing unit 100 and 200, and a read clock generated from the scan line processing unit 300. Line speed by (RD) speed and screen selection signal (MUX SEL) The first and second field memories 400 and 500 alternately output a selected two-screen digital video signal.

The widescreen two-screen display device configuration having the independent screen aspect ratio conversion (ARC) function of the present invention receives and stores the luminance signal of the first video signal for displaying the two screens as shown in FIG. A first half field memory 801, a second half field memory for receiving and storing color signals of the first image signal, and the first and second half field memories 801 and 802; 3) the aspect ratio conversion unit 803 for processing the zooming by reading the image data, generating and outputting the zoomed signal and the selection signal MUX SEL, and the second image signal for displaying the two screens. A third half field memory 804 for receiving and storing a luminance signal, a fourth half field memory 805 for receiving and storing a color signal of the second video signal, and the third and fourth 1 / 2) Image data is read from the field memory and zoomed in. The zoomed signal and the select signal (MUX SEL) are generated and output. The luminance signals of the third and fourth screen aspect ratio converters 803 and 806 are multiplexed for each line in accordance with a selection signal input from the four screen aspect ratio converter 806 and the three screen aspect ratio converter 803. And a luminance signal multiplexer 807, and a color signal multiplexer 808 for multiplexing the color signals of the third and fourth screen aspect ratio converters 803 (8060) every line.

As shown in FIG. 10, the screen aspect ratio converting section includes one line for the clock generator 100a for generating the clock CLK by the horizontal synchronization H-SYNC and the image data input from the field memory. A line memory 100b for storing the data, and a scan line interpolation unit 100c for interpolating the scanning lines of the image data transmitted from the line memory 100b according to the coefficient selection signal and outputting the interpolated digital image data; A coefficient for receiving the horizontal synchronizing signal (H-SYNC) and the vertical synchronizing signal (V-SYNC) to generate and output a line reset signal (LRST) to the line memory (100b) and a coefficient selection signal to the scan line interpolation unit (100C). A write enable signal for field memory control by combining the control unit 100d and a signal for generating and outputting a read enable signal RE and a write enable signal WE by receiving the horizontal synchronization signal H-SYNC. And the lead enable signal Comprising of arithmetic unit 100f to generate and output.

A write enable signal of the field memory is generated by performing an AND operation on the two screen write enable signal 2WE generated by the operation unit 100d and the write enable signal WE generated by the line counter 100e. The first AND gate AD1 and the line block field read enable signal LBF-RE of the coefficient controller 100d and the read enable signal RE of the line counter 100e. And a second enable gate AD2 which generates a write enable signal of the field memory and outputs it to the field memory.

As shown in FIG. 11, the line counter 100e includes a 9-bit counter 100a that counts pulses of the input synchronization signal H-SYNC by 9 bits, and an input clock pulse CLK. 10-bit counter (100b) for counting each 10-bit, and letter box that the upper and lower portions of the two screens are cut off at the time of 4/3 or 3/2 zooming in accordance with the count output of the 9-bit counter (100a) Left and right side panel removal section for detecting left and right side panel removal section in which the left and right sides of the screen are cut at 3/2 zooming in accordance with the count output of the upper and lower letterbox section detection unit 110c for detecting a portion and the 10-bit counter 110b. Disable the light enable signal to prevent the video signal from being written during the section detected by the detector 110d and the upper and lower letterbox section detection section 110c and the left and right side panel removal section detection section 110d according to the 3/2 zooming selection signal. Signal control unit 110e ).

The upper and lower letter box section detecting unit 110c detects a letter box section in which the upper and lower portions of the screen are cut when displaying two screens, and the upper and lower letter box section detecting unit 110c 'for disabling the lead enable signal when detecting the section. 4/3 zooming letterbox section detection unit 110c for detecting letterbox sections in which the upper and lower sections are cut at 4/3 zooming, and 3 / letterbox sections detecting upper and lower sections at 3/2 zooming. It consists of a two zooming upper and lower letter box section detection unit (110c ').

The signal controller 110e includes an inverting bottom 110e1 for inverting the state of the 3/2 zooming selection signal, an output signal of the inverter 110e1, and a 4/3 zooming in the up and down letterbox section detection unit 110c. The first and second gates 100e2 for receiving the output signal of the upper and lower letterbox section detection unit 110c and performing a logical multiplication and outputting the corresponding signal, and the 3/2 zooming selection signal and the left and right side panel removal section detection units 110d. A second and gate 110e3 for receiving the output signal and the output signal of the 3/2 zooming upper and lower letter box section detecting unit 110c 'in the upper and lower letter box section detecting section 110c and performing a logical multiplication to output a signal generated; The OR signal 110 is configured by performing OR on the output signals of the first and second AND gates 110e2 and 110e3 to generate and output the write disable signal WE.

The present invention also provides a widescreen two-screen display device having a common aspect ratio conversion function. As shown in FIG. 9, the first and second line memories 901 for storing the luminance signal and the color signal of the first image signal for displaying two screens, respectively, to reduce the horizontal width of the image to 1/2. 902, fifth and sixth half field memories 903 and 904 for storing the luminance signal and the color signal of the second video signal, respectively, and the first line memory 901 and the fifth half field. The multiplexing unit 905 for multiplexing the luminance signals of the memory 903 and the second line memory 902 and the sixth half field memory 904 perform multiplexing on the color signals. A seventh and eighth half field memories 907 and 908 for storing the signals multiplexed by the color signal multiplexer 906 and the luminance and color signal multiplexers 905 and 906, respectively; The luminance signal and the color signal are read from the seventh and eighth half field memories 907 and 908 to output a zoomed signal, and a screen selection signal is generated. And it constitutes a color signal multiplex unit 905, 906, a fifth screen aspect ratio converting unit 909 for outputting a.

The operation and effect of the present invention configured as described above will be described in detail as follows.

In FIG. 2, a first image signal and a second image signal for displaying two screens are input from the first and second screen aspect ratio converters 100 and 200, respectively, subjected to zooming, and then output. The data is stored in the first and second field memories 400 and 500, respectively.

Here, when it is assumed that the aspect ratio is 4: 3, the first and second image aspect ratio converters 100 and 200 perform 4/3 zooming on the first and second image signals, respectively, and output the same.

At this time, the clock generator 300a of the scan line processing unit 300 generates the first clock CLK1 of 910f _H as the secondary exhaust 300b in accordance with the horizontal synchronization signal H-SYNC of the first image signal. .

The multiplier 300b multiplies the first clock twice, and provides the multiplied clock CLK4 to the first and second field memories 400 and 500 using the read clock RD.

When reading image data from the first and second field memories 400 and 500, two image data are alternately read every line, and two image signals must be loaded on one horizontal scan line to read the image data. To double the clock CLK1 generated from the clock generator 300a of the scan line processor 300 so that the output of the first and second field memories 400 and 500 is selected and read by the multiplexer 600. .

In this case, the screen selection signal MUX SEL of the multiplexer 600 divides the first clock CLK1 output from the clock generator 300a of the scan line processor 300 to be 455 or at a multiplier 300b. The output clock CLK4 is divided into a 910 divider 300c so as to be 910 to be equal to the period of the horizontal synchronization signal H-SYNC, but the duty DUTY is 50%.

Alternatively, if the image data is stored in the field memory including the horizontal sync section, only one horizontal sync is read for the left and right screens, so the duty ratio is appropriate depending on the time ratio when the stored video data includes and does not contain horizontal sync. The monostable multivibrator 700 may be used to adjust the duty of the horizontal synchronization H-SYNC of the first image signal to be used as the screen selection signal MUX SEL of the multiplexer 600.

The field read reset signal FRR and the read enable signal RE generated by the first screen aspect ratio converter 100 are adjusted to synchronize the first video signal with the second video signal. Commonly supplied to the first and second field memories 400 and 500.

As described above, when the first and second video signals for displaying the two screens are input, the first and second screen aspect ratio converters 100 and 200 perform 4/3 zooming to convert the aspect ratios of the screens. 2, when stored in the field memory (400, 500), to adjust the read clock (RD) of the first and second field memory (400, 500) with the horizontal synchronization (H-SYNC) of the first video signal Adjust to double the light clock.

Then, the multiplexer 600 alternately reads two video signals stored in the first and second field memories 400 and 500 for each line by the screen selection signal MUX SEL and alternates them on a horizontal scan line. Two video signals are loaded on the screen. This signal becomes a two-screen digital video signal.

In this case, the selection signal of the multiplexer 600 divides the clock multiplied by the multiplier 300b of the scan line processor 300 into 910 or divides the clock of the clock generator 300A into 455 or uses the first signal. When the image data including the horizontal synchronizing section is stored in the 1,2 field memories 400 and 500, the mono-stable multivibrator 700 receives the horizontal synchronizing of the first image signal and stores the duty of the horizontal synchronizing. Adjust the image data according to the time ratio when the horizontal synchronization is included or not included.

Then, the configuration of the first and second screen aspect ratio converters 100 and 200 is the same as in FIG. 3, and the operation of zooming to convert the screen aspect ratio is described below with reference to FIG. .

First, the clock generator 103 generates the first clock CLK1 according to the period of the horizontal synchronization H-SYNC of the input image signal, and provides the first clock CLK1 to the aspect ratio converter 112.

Then, the 3/2 multiplier 104 multiplies the aspect ratio converter 112 by 3/2 with respect to the first clock CLK1 and outputs it to the clock selector 106, and the 4/3 multiplier 105 outputs the first multiplier. The multiplier multiplies the clock CLK1 by four thirds and outputs the same to the clock selector 106.

At this time, a clock through the clock generator 103, that is, a clock not multiplied by CLK1, is input to another input terminal of the clock selector 106.

Accordingly, by the assumptions made above, the clock selector 106 selects an output to the 4/3 multiplier 105 and provides it to the first and second line memories 101 and 102 and the field memory 110, respectively.

As a result, the first line memory 101 increases the speed by 4/3 zoomed by receiving the input digital video signal.

In the second line memory 102 that receives the output data of the first line memory 101, the clock provided from the clock selector 106 is used as the write clock WR and the read clock RD. Since the read speed is the same, the output is delayed by one line.

The scan line interpolation unit 109, which receives the current data of the first line memory 101 and the data previous to the second line memory 102, performs scan line interpolation, and the interpolation ratio is 3/3 zooming. Four scan lines are made of three scan lines, and three scan lines are made of two scan lines in the case of 3/2 zooming.

As described above, the clock selector 106 selects the third clock CLK3 that is the output of the 3/2 multiplier 104 or the second clock CLK2 that is the output of the 4/3 multiplier 105. The video signals input to the one-line memory 101 are A, B, DC, D, E, F... … As shown in FIG. 4, the image data output through the first line memory 101 and the second line memory 102 and the data output through the field memory 110 are as shown in FIG. 4.

At this time, the coefficient control unit 107 receives the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC, detects edges of the synchronizing signals, and performs a logical operation on the detected edge signals to perform the first operation. Selection for outputting a reset signal LRST (FRST) for resetting the line memory 101 and the field memory 110, respectively, and selecting the interpolation coefficient required by the scan line interpolation unit 109 appropriately for every scan line. Output the signal.

The reincounter 108 receives the horizontal synchronization signal (H-SYNC) and writes only the portion to be recorded in the field memory 110 to zoom the necessary portion of the entire screen. Since it is not necessary to record the cut-out portion in the field memory 110, the write enable signal WE for outputting the light is output, and the letter box LETTER is displayed at the upper and lower portions when displaying in two screens. A blank portion in the form of a box is generated. In this case, since the image data should not be read, a read enable signal RE for disabling read is output.

As described above, the image data of the scan line interpolation unit 109 is written to the field memory 110 at the speed of the write clock WR generated by the clock selector 106, and generated by the clock generator 103. By reading and outputting at the speed of one clock CLK1, the digital video signal interpolated with the scan line is output.

Referring to FIG. 3 for the 4/3 zooming operation described above, when the clock generator 103 generates the clock CLK1 according to the horizontal synchronization signal H-SYNC, the aspect ratio conversion is performed. 4/3 multiplier 105 of the unit 112 multiplies the clock CLK2 by 4/3 times, and 3/2 multiplier 104 multiplies the clock CLK3 by 3/2 times the clock selector 106. Occurs.

At this time, the clock selector 106 selects the clock CLK2 multiplied by the 4/3 multiplier 105 and outputs the clock CLK2 to the first line memory 101, the second line memory 102, and the field memory 110, respectively. do.

Then, the first line memory 101 uses the clock CLK2 provided from the clock selector 106 as the read clock RD, and the second line memory 102 uses the read clock RD and the light clock. WR is used together, and the field memory 110 is used as a write clock WR.

The first line memory 101 uses the clock CLK1 output from the clock generator 103 as the write clock WR.

Accordingly, the first line memory 101 writes the digital image signal input at the speed of the clock CLK1 generated by the clock generator 103, and writes the clock CLK2 selected by the clock selector 106. Are read at the speed of and output to the second line memory 102 and the scan line interpolation unit 109, respectively.

Since the second line memory 102, which has received the digital image signal from the first line memory 101, writes and reads to the second clock CLK2 from the clock selector 106, the first line memory The digital video signal provided from 101 is delayed by one line in the second line memory 102 and transferred to the scan line interpolation unit 109.

Then, the scan line interpolator 109 receives the current data provided from the first line memory 101 and previous data provided from the second line memory 102, and provides a coefficient selection signal provided from the coefficient controller 107. By doing this, three scan lines are formed into four scan lines and output to the field memory 110.

If the scan lines are displayed on the screen, 4/3 of the signals are displayed on the vertical side of the 4: 3 video signal and are displayed on the entire vertical side of the 16: 9 screen by scanning line interpolation.

In the above, the field memory 110 is the first field memory 400 or the second field memory 500 in FIG. 2.

The operation of the scan line interpolator 109 will now be described with reference to FIG. 6.

3, the first and second multiplexing units 601a of the image data selecting unit 601 display modern image data output from the first line memory 101 and previous image data passing through the second line memory 102. As shown in FIG. Multiplying unit 602 by selecting one of modern image data or previous image data according to the second selection control signal S1 generated by the coefficient control unit 107 in FIG. Will output

Then, the first to third multipliers 602a to 602c of the multiplier 602 are read out from the first multiplexer 601a of the image data selector 601 every line, and the coefficient value 1 is input to the image data. Multiply by / 4, 1/2, 3/8, and provide the value obtained by the multiplication by the line selector 603 to the third multiplexer 603a, and the fourth to sixth multipliers 602d to 602f provide the image. The image data selected for each line from the second multiplexer 601b of the data selector 601 is multiplied by a coefficient value of 3/4, 1/2, 5/8, and the value obtained by multiplying the image data is selected by the line selection. The fourth multiplexer 603b of the unit 603 is provided.

Accordingly, the first multiplexer 603a of the line selector 603 receives 2-bit image data input from the first multiplexer 601a of the image data selector 601 and the first to third multipliers 602a. 3 bit coefficients generated by the coefficient control unit 107 from the image data multiplied by 602c) and the image data of each bit multiplied by the fourth and sixth multipliers 602d and 602f, and its ground potential. Selected and outputted every line according to the selection signals S0, S1, and S2, and the fourth multiplexer 603b similarly includes the first and third multipliers 602a, 602b, and fourth to fourth multipliers 602. The image data multiplied by the sixth multipliers 603d to 603f and its 3-bit ground potential are selected for each line and output to the data summing unit 604.

The selection control signal is used as a selection signal of the third and fourth multiplexers 603a and 603b for processing 4/3 zooming and 3/2 zooming in common. The third selection control signal S2 is divided into four pairs of eight pairs of inputs input to the third and fourth multiplexers 603a and 603b, and the third selection signal S2 is a 3/2 zooming selection signal. If) is 0, select 4/3 zooming and if 1, select the input used for 3/2 zooming.

In the case of 4/3 zooming, as shown in FIG. 7A, the third multiplexer 603a of the line selector 603 interpolates through the first multiplexer 601a of the image data selector 601. When selecting and outputting image data multiplied by 1, the fourth multiplexer 603b selects 0 image data and outputs it to the data summing unit 604. Similarly, the third multiplexer 603a is a multiplier. When the first multiplier 602a of 602 selects the image data multiplied by the 1/4 interpolation coefficient, the fourth multiplexer 602b receives the image data multiplied by the 1/2 interpolation coefficient of the fifth multiplier 602e. It selects and outputs to the data summing part 604.

In addition, when the third multiplexer 603a selects image data of the second multiplier 602b and the fourth multiplier 602d, which are multiplied by 1/2 and 3/4 interpolation coefficients, the fourth multiplexer 603b selects 1/7. Image data of the fifth and first multipliers 602e and 602a, which are multiplied by 2, 1/4 interpolation coefficients, are selected and output to the data summing unit 604, respectively.

That is, two multiplier outputs are combined to make one generated line in FIG. 7 (a) (b). In this case, the interpolation coefficient displayed on the left is selected by the third multiplexer 603a of FIG. , The interpolation coefficient displayed on the right side is selected by the fourth multiplexer 603b of FIG.

The interpolation coefficients displayed on the left and right sides meet to form one interpolation line, which is performed by the data summing unit 604 of FIG.

Therefore, when the data summing unit 604 sums up the image data selected and output from the third and fourth multiplexers 603a and 603b of the line selector 603, three scan lines are made of four scan lines. Data, that is, image data in which the scan line is interpolated, is output.

As in the case of 4/3 zooming, the image data of the multiplier multiplied by the interpolation coefficient may be appropriately selected for the 3/2 zooming as shown in FIG. 7B.

The operation of the coefficient control unit 107 illustrated in FIG. 3 is described based on FIG. 5. When the horizontal synchronization signal H-SYNC is input, the first edge detector 501a of the edge detector 501 operates. When the edge of the start portion of the horizontal synchronization signal H-SYNC is detected and detected, the line reset signal LRST is generated to reset the first line memory 101 of FIG.

When the vertical synchronization signal V-SYNC is input to the coefficient control unit 107, the second edge detection unit 501b operates to detect an edge of the start of the vertical synchronization signal V-SYNC. The reset signal FRST is generated to reset the field memory 110 of FIG.

At this time, the first flip-flop 502a of the counting unit 502 receiving the horizontal synchronization signal H-SYNC counts the number of pulses of the horizontal synchronization signal and outputs it to the second flip-flop 502b (Q ₀ ). The second tip flip-flop (02b) receiving the output counts again and outputs Q _{1. In the} case of 4/3 zooming, the second tip flip-flop (02b) operates as a modulo-4 counter. Acts as a modulo-3 counter.

The signal Q ₀ output from the first flip-flop 502a is a second coefficient selection signal S1, and the signal Q ₁ output from the second tip flip-flop 502b is a third coefficient. The selection signal S2 is used, and the first coefficient selection signal S0 is a 3/2 zooming selection signal.

On the other hand, when the two-screen function selection signal is selected, the line blank field lead enable signal LB-RD is always enabled, and instead, the two-screen light enable signal 2WE is activated to scan the scan line every four lines or three. By omitting one for each line, the screen can be compressed vertically.

Here, 3/2 zooming should be done when the 3/2 zooming selection signal is high and 4/3 zooming when the low state is low.

When displaying in two screens, only one screen aspect ratio change IC may be used or two may be used depending on whether the horizontal scan line is multiplexed after the screen aspect ratio conversion (ARC) process or before the ARC process. have.

Here, a widescreen two-screen display device having an independent screen aspect ratio conversion (ARC) function, which is first subjected to screen aspect ratio conversion (ARC) multiplexing of horizontal scan lines, is shown in FIG. A widescreen two-screen display device having a common aspect ratio conversion function for multiplexing before performing ARC processing is as shown in FIG.

The configurations of the third, fourth, and fifth screen aspect ratio converters 803, 806, and 909 are the same, and the configuration thereof is as shown in FIG.

First, referring to FIG. 8, a widescreen two-screen display device having an independent screen aspect ratio conversion function is used. The luminance signal of the first video signal, the second video signal, and the second video signal for displaying the two screens is shown. When (Y) is input, the first and third 1/2 field memories 801 and 804 are received and stored sequentially, and the color signals U / V of the first and second video signals are input. The second and fourth 1/2 field memories 802 and 804 receive and store the received data.

Here, the color signal is a signal (U / V) in which the U signal and the V signal are multiplexed.

When the luminance signal and the color signal stored in the first and second 1/2 field memories 801 and 802 are simultaneously input to the third screen aspect ratio converter 803, the third screen aspect ratio converter 803 zooms. Processing is performed to convert the aspect ratio of the screen and output the image, and to generate and output the screen selection signal MUX SEL.

Similarly, the fourth screen aspect ratio converter 806 performs zooming on the signals output from the third and fourth half field memories 804 and 805 which respectively store the luminance signal and the color signal of the second video signal. To convert and output the aspect ratio of the screen, and to generate and output the screen selection signal MUX SEL.

According to the selection signal MUX SEL output from the third screen aspect ratio converter 803, the multiplexers 807 and 808 for luminance and color signals are respectively converted to the third and fourth screen aspect ratio converters 803 and 806. Multiplexing is performed on the luminance signal and the color signal outputted from the output signal.

Then, the multiplexers 807 and 808 for luminance and color signals are divided into left and right screens for each line to display two screens.

Similarly to FIG. 9, when the luminance signal Y of the first video signal and the second video signal is input, the first line memory 901 and the fifth 1/2 field memory 903 receive and store the same. When the color signals of the first video signal and the second video signal are input, the second line memory 902 and the sixth half field memory 804 receive and store them.

The reason why the memory for storing data with respect to the input of the first image signal is a line memory is to reduce the horizontal width of the image by 1/2.

Therefore, when writing the first image signal to the first and second line memories 901 and 902, the pixel enables the write enable signal by one pixel every two pixels, so that the amount of image data per horizontal period is 1 /. Reduce to two.

Similarly, when the second video signal is written to the fifth and sixth half field memories 903 and 904, one pixel is not written every two pixels so that when the left and right video data are multiplexed, Ensure peace minorities.

The luminance signal multiplexing unit 905 multiplexes the luminance signal of the first image signal and the second image signal stored in the first line memory 901 and the fifth 1/2 field memory 903. When stored in the 7 1/2 field memory 907, the color signal is stored in the 8 1/2 field memory 908 through the same process.

Therefore, the fifth screen aspect ratio converter 909 performs zooming on the video signals input from the seventh and eighth half field memories 907 and 908, and outputs two-screen signals.

Referring to FIG. 10 for the operation of the screen aspect ratio conversion unit 909 used in the above, the coefficient control unit 100d that has received the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC has already been made. The coefficient selection signal is output to the scan line interpolation section 100c by performing the operation as described in accordance with FIG. 5, the line reset signal LRST is output to the line memory 100b, and the line blank field read enable signal LBF-. RE) and two-screen write enable signal 2WE, respectively.

Accordingly, the line memory 100b stores one line when image data is input from the half field memories shown in FIGS. 8 and 9, and then ends the line memory when the line reset signal is input.

When the data stored by the line memory 100b is provided, the scan line interpolator 100c receives the output data of the 1/2 field memory and the output data of the line memory 100b, respectively, from the coefficient control unit 100d. A digital video signal obtained by interpolating the scanning lines is output by the coefficient selection signal outputted.

At this time, when the line counter 100e generates and outputs the write enable signal WE and the read enable signal RE, the first AND gate AD1 of the calculator 100f is set to 2 of the coefficient controller 100d. The write enable signal WE generated by performing a logical multiplication by receiving the screen write enable signal 2WE and the write enable signal of the line counter 100e is provided to the 1/2 field memory to perform write operation. The second enable gate AD2 receives the line block field read enable signal of the coefficient control unit 100f and the read enable signal of the line counter 100e and performs a logical multiplication to generate a read enable signal ( RE) is output to the 1/2 field memory to control the operation of the read.

The half field memory here corresponds to the seventh half field memory 907 or the eighth half field memory 908 in FIG.

If the same interpolation coefficient is used for the radix field and the even field when the video signal inputted to the scan line interpolation unit 100c is interlaced, the magnitude of the coefficient is 1/8. Since 4/3 zooming is applied, different coefficients are used as shown in (a) of FIG. 12, and at 3/2 zooming, different coefficients are used as shown in (b) of FIG.

Therefore, in the case of interlaced scanning as described above, when the composite video signal is input as shown in FIG. 13, it is inputted by the sync separator 706 to determine whether the radix field or the even field is selected. The video data interpolated by the scan line is output through the unit 601, the multiplier 602, the line selector 603, and the data adder 604, and the image data having the same configuration as shown in FIG. The selector 701, the multiplier 702, the line selector 703, and the data adder 704 output the interpolated image data.

The ninth multiplexer 705 then multiplexes the outputs of the data summing units 604 and 704 again and interpolates the scan lines for the interpolated scan.

The operation of the line counter 100e and the line counter in FIG. 2 is described based on FIG. 11. The pulse of the horizontal synchronization signal H-SYNC to which the 9-bit counter 110a is input is input. After receiving 9 bits and providing the upper and lower letter box section detecting unit 110, the upper and lower letter box section detecting section 110c of the upper and lower letter box section detecting section 110c 'is composed of two screens of upper and lower black letter boxes. The part detects the upper and lower dark letterbox sections so as not to read the image data, and disables the lead enable signal RE in the detected sections. Similarly, the 4/3 zooming upper and lower letterbox sections are detected. In the detection unit 110C, at 3/2 zooming, the 3/2 zooming upper and lower letter box section detection unit 110C 'detects the letter box section cut at zooming and outputs the detected sections.

Then, when the 10-bit counter 110b receives the input clock and counts 10 bits, and outputs the left and right side panel removal section detection unit 11d, the left and right side panel removal sections are cut off from the left and right at 3/2 zooming. Is detected and output.

Accordingly, when the 4/3 zooming up and down letterbox section detection unit 110C, the 3/2 zooming up and down letterbox section detection unit 110C ', and the left and right side panel removal section detection unit 110d output the detected sections, respectively, the signal is output. When the control unit 110e receives the logic operation using the inverter 110e1, the end gates 110e2, 110e3, and the oragate 110e4 according to the 3/2 zooming selection signal, the controller 110e receives 4/3 or 3/2 zooming. A signal for disabling the write enable signal WE is output so that the image data is not written in a portion where the top and bottom portions of the screen are cut off or a portion where the left and right screens are cut during 3/2 zooming.

As described in detail above, the present invention can simplify the configuration of hardware by reducing the number of field memories when displaying two screens using an aspect ratio converter function in an optical device having an aspect ratio of 16: 9. There is one effect.

Claims (7)

A first field memory for receiving and storing a luminance signal of a first video signal for displaying two screens, a second field memory for receiving and storing a color signal of a first video signal, and the first and second field memories A first field aspect ratio converter for generating and outputting a zoomed signal and a selection signal, and a third field for receiving and storing luminance signals of a second image signal for displaying two screens A memory, a fourth field memory for receiving and storing color signals of the second video signal, and a second field for reading video data from the third and fourth field memories, processing zooming, and outputting the zoomed signal. A luminance signal multiplexer for multiplexing and outputting a luminance signal of the first and second screen aspect ratio converters in each line according to a screen aspect ratio converter and a selection signal input from the first screen aspect ratio converter; A color signal multiplexer configured to multiplex and output the color signals of the first and second screen aspect ratio converters every line according to a selection signal input from the aspect ratio converter, so that an independent screen aspect ratio conversion method is used. 2-screen display. The display device as claimed in claim 1, wherein the screen aspect ratio converting section comprises: a clock generator for generating a clock by a horizontal synchronization signal (H-SYNC), a line memory for storing image data input from the field memory line by line, and the line memory; A scan line interpolation unit for interpolating the scan line according to the coefficient selection signal and outputting the interpolated digital image data, the horizontal sync signal (H-SYNC) and the vertical sync signal (V-SYNC). A coefficient control unit for receiving and generating a line reset signal for resetting the line memory, a coefficient selection signal for the scan line interpolation unit, a two-screen write enable signal, a line block field read enable signal, a field reset signal, and the like; A line counter that receives the input horizontal sync signal (H-SYNC) and generates and outputs a read enable signal and a write enable signal; A wide screen display device comprising: an operation unit configured to combine the signals generated from the coefficient controller and the line counter to generate and output a write enable signal and a read enable signal for writing or reading the field memory; . The write enable signal of claim 2, wherein the operation unit receives a two-screen write enable signal generated by the coefficient controller and a write enable signal generated by the line counter, and performs a logical multiplication to write the image data into the field memory. A read-out for reading image data from the field memory by performing a logical multiplication by receiving a first and gate generated and outputted, a line block field read enable signal output from the coefficient controller, and a read enable signal output from the line counter; And a second AND gate generating an enable signal and outputting the enable signal to the field memory. 3. The line counter of claim 2, wherein the line counter includes a 9-bit counter for counting pulses of an input horizontal synchronization signal (H-SYNC) by 9 bits, a 10-bit counter for counting input clock pulses by 10 bits, and the 9 bits. Up and down letter box section detection section for detecting letter box part that the upper and lower parts of two screens are cut off when displaying two screens in accordance with the counter's count output and 4/3 or 3/2 zooming, and according to the count output of the 10-bit counter. Left and right side panel removal section detection section for detecting left and right side panel removal section that cuts the left and right sides of the screen during 3/2 zooming, and the upper and lower letter box section detection section and the left and right side panel removal section detection section according to the 3/2 zooming selection signal. A two-screen wide screen comprising a signal control unit for disabling the write enable signal so as not to write an image signal during a predetermined period The market value. The upper and lower letter box section detecting unit of claim 4, wherein the upper and lower letter box section detecting sections detect a letter box section in which the upper and lower portions of the screen are cut off, and disable the read enable signal when detecting the section. 4/3 zooming upper and lower letterbox section detection section for detecting letterbox section where upper and lower sections are cut off at 4/3 zooming and 3/2 zooming upper and lower letterbox detecting letterbox section at upper and lower sections sectioned at 3/2 zooming An extensive two-screen display device comprising a section detection unit. The signal control unit of claim 4, wherein the signal control unit comprises: an inverter for inverting the state of the 3/2 zooming selection signal, and a signal output from the output signal of the inverter and the 4/3 zooming upper and lower letterbox section detecting unit of the upper and lower letterbox section detecting unit; A first and gate for receiving an AND and outputting a signal, and outputting the 3/2 zooming selection signal and the left and right side panel removal section detection unit and a 3/2 zooming upper and lower letterbox section detection unit A second and gate for outputting a signal generated by performing a logical multiplication on each of the signals output from and an oragate for generating and outputting a write disable signal by performing a logical sum of the output signals of the first and second gates. A widescreen two-screen display device, characterized in that configured. First and second line memories for storing the luminance signal and the color signal of the first image signal for displaying two screens, respectively, and reducing the horizontal width of the image to half, and the luminance signal and the color signal of the second image signal. A first and second field memories to be stored, a luminance signal multiplexing unit which performs multiplexing on luminance signals of the first line memory and the first field memory, and color signals of the second line memory and the second field memory, respectively. And a luminance signal and a color signal from the third and fourth field memories for storing the multiplexed signal for the multiplexing process for the multiplexing process for the color signal, the multiplexed signal through the luminance and the multiplexing unit for the color signal, and the third and fourth field memories. A common aspect ratio conversion (ARC) method is composed of a screen aspect ratio conversion unit which outputs a signal subjected to zooming processing and generates a selection signal and outputs it to the multiplexer for luminance and color signals. Two-screen display device of the wide TV, characterized in that to process.