KR0157503B1 - 16:9 image display apparatus in 4:3 scrren - Google Patents

Abstract

The present invention relates to a 16: 9 image display device in a 4: 3 screen in which a decoded 16: 9 image is deduced at a ratio of 5: 4 in the vertical direction and displayed on a 4: 3 monitor in a letter box form. When the forward-scanned video signal is input to the letterbox generator, the first adder adds the video signal of the current line and the previous line passing through the 1H delay part and outputs an average value. The first multiplexer under the control of the controller selectively outputs the output signal of the 1H delay unit or the first adder, and the first multiplexer selectively outputs the output signal of the 1H delay unit or the video signal of the current line. The second adder adds output signals of the two multiplexers and outputs an average value to the frame memory. When the parallel scan image signal is input, the third and fourth multiplexers and the third adder are further connected to the output terminal of the second adder. Therefore, it is possible to implement a letterbox generator that has a simple hardware structure and is fast.

Description

4: 3 Screen 16: 9 Video Display

FIG. 1A is a general video data encoding apparatus, and FIG. 1B is a block diagram showing an example of a video data decoding apparatus.

2A to 2C are exemplary diagrams for explaining quantization, zigzag scan, and (run, level) encoding of a transform coefficient.

3 is a variable-length encoding table for giving a code length to (run, level) symbols in Huffman encoding.

4A and 4B are screen state diagrams showing the letter box form when a 16: 9 image is displayed on a 4: 3 monitor.

5A and 5B are video signal state diagrams for explaining a method of implementing a 16: 9 letterbox on a conventional 4: 3 monitor.

FIG. 6 is a video signal state diagram for explaining a method of implementing a 16: 9 letterbox on a 4: 3 monitor proposed in the present invention, where a is a forward scan and b is a parallel scan.

7 is a block diagram of a letterbox generator in the forward scan proposed in the present invention.

8 is a block diagram of a letterbox generator in the case of a perforated scan proposed in the present invention.

* Explanation of symbols for main parts of the drawings

9, 16, 26: Frame memory 20: 1H delay part

21, 25, 29: adder 22: control unit

23, 24, 27, 28: multiplexer

The present invention relates to an apparatus for displaying a 16: 9 image on a monitor having an aspect ratio of 4: 3. Particularly, a filter for extracting a 16: 9 image in a vertical ratio of 5: 4 in a vertical ratio is used. The present invention relates to a 16: 9 video display device in a 4: 3 screen which simplifies the calculation process of the coefficients and makes the hardware easy to implement.

Recently, in systems such as HD-TV, digital DBS, HD-VCR, digital VTR, digital camcorder, multimedia, etc., video and audio are encoded into digital signals, transmitted or stored on a recording medium, and decoded and played back. have. Image data encoding apparatuses commonly use transform encoding, DPCM, vector quantization, variable length encoding, etc. to eliminate redundancy in video signals and reduce data volume. In particular, studies are being actively conducted to show a 16: 9 image in a 16: 9 letter box on a monitor having an aspect ratio of 4: 3 in an image data decoding apparatus.

FIG. 1A is a general video data encoding apparatus, and FIG. 1B is a block diagram showing an example of a video data decoding apparatus. In FIG. 1A, image data of a predetermined size block unit input to the encoding apparatus is applied to the subtractor 1, and the subtractor 1 subtracts the feedback data from the input data and outputs the error data. The N × N converter 2 connected to the output of the subtractor 1 converts the error data into data in the frequency domain to collect energy of the signal toward the low frequency side. The transform coefficients of the N × N converter 2 are applied to the quantizer 3 and quantized according to the quantization level signal Q fed back from the buffer 5 to adjust the bit rate. The variable length coding unit 4 further reduces the amount of data by variable length coding the quantized data using the statistical characteristics of the representative values. The variable length coded data is stored in the buffer 5 and transmitted at a constant speed, and the buffer 5 outputs the quantization level signal Q so that no overflow or underflow occurs.

The output data of the quantization unit 3 is applied to the N × N inverse transform unit 7 through the inverse quantizer 6 for inverse quantization and inverse transform processing. The image data of the N × N inverse transform unit 7 is applied to the adder 8 and added to the feedback data, and the frame memory 9 stores the output data of the adder 8 in units of frames to reconstruct the screen. On the other hand, since there are many similarities between the screen and the screen, if the motion is estimated and compensated using this motion vector, the difference signal becomes very small, thereby enabling data compression. The block image data input to the encoding apparatus is also applied to the synchronization unit 10, which calculates a motion vector by searching the frame memory 9 for the data of the pattern most similar to the input data. The motion vector is obtained for each block or macroblock and transmitted with the video signal encoded in the form of additional information. The compensator 11 reads block data corresponding to the motion vector of the sync driver 10 from the frame memory 9 and outputs the block data to the subtractor 1 and the adder 8.

When the image data encoded in the decoding apparatus in FIG. 1B is input, the variable length decoding unit 12 variably decodes the data to extend the image data. The output data of the variable length decoding unit 12 is applied to the inverse quantization unit 13 and inversely quantized into a transform coefficient of the frequency domain according to the quantization level signal Q transmitted from the encoding apparatus. The N × N inverse transform unit 14 connected to the output terminal of the inverse quantization unit 13 inverts the transform coefficients into image data of the spatial domain. The error data output from the N × N inverse converter 14 is applied to the adder 15, and the adder 15 adds the error data and the N × N block data output from the compensator 17 to the display device. Output The frame memory 16 is connected to the output terminal of the adder 15 to store the returned data in frame units, and the compensating unit 17 is connected to the output terminal of the frame memory 16. The eastern part 17 reads NxN block data corresponding to the motion vector transmitted from the encoding apparatus from the data stored in the frame memory 16, and applies it to the adder 15.

2 is an exemplary diagram for explaining quantization, zigzag scan, and (run, level) encoding of transform coefficients. FIG. 2A shows image samples as transform coefficients as shown in FIG. 2B when transformed by DCT or the like, and when the transform coefficient is quantized, most of the quantized coefficients are often zero. With this in mind, as shown in Fig. 2c, the (run, level) encoding is performed while zigzag scanning from the low frequency component to the highest frequency component. Where run is the number of zeros between the nonzero coefficients and level is the absolute value of the nonzero coefficients. For example, for an 8x8 block, a run can have a value from 0 to 63, and the level depends on a value that can come from the quantization output. Takes a value from 1 to 255 and the sign bit is separate. 3 shows a variable length encoding table that gives a code length to all possible (run, level) symbols in Huffman encoding. This table has a very high regular area (run / level area of 0/1 to 15/16) with 90-96% probability of occurrence of data, and an escape with very low probability of occurrence of data. ) Area (run / level area of 15/16 to 63/255). In the conventional Hoffman coding method, a signal having a high probability is represented by a short length code data according to a frequency occurrence probability of an input signal, and a signal having a low probability is represented by a long length code data. However, when there are many kinds of symbols and many symbols having very low probability, all of the long codewords for the lean symbols are complicated to encode / decode. Therefore, combining sparse symbols into simple fixed-length codes, such as escape sequences, reduces efficiency but greatly reduces complexity. The escape sequence is a total of 21 bits, consisting of an escape code (for example, 6 bits), 6 bits for representing a run, 8 bits for representing a level, and 1 bit for a sine.

4 shows a letterbox form when displaying an image having an aspect ratio of 16: 9 on a 4: 3 monitor. As shown in FIG. 4A, when the original digital image having the aspect ratio of 16: 9 is encoded and decoded at the receiving side, there is no problem if the monitor at the receiving side has the aspect ratio of 16: 9. However, in the case of a 4: 3 monitor, as shown in FIG. 4B, the letter box must be displayed so that the viewer can see the correct image. As such, in order to configure a 16: 9 letterbox on a 4: 3 monitor, a filter for vertically extracting a 16: 9 image is required.

5 is a state diagram of a video signal for explaining a method of implementing a 16: 9 letter box on a conventional 4: 3 monitor. In Figure 5a each number 1, 2, 3,... Is the line number of the original image, and in Fig. 5b, 1 ', 2', 3 ',... Is the line number of the image for letterbox display. 5 (a) and b (b), P (n) is an image signal value in n lines, A is an odd field, B is an even field, a line indicated by a black dot is an original line, and a line indicated by a white dot is interpolated ( Interpolation) line. Where the values at each line for letterbox [P (1 '), P (2'), P (3 '), P (4'), P (5 '), P (6')] The relative distance from the line [line 1, 2, 3, 4, 5, 6, 7, 8] is defined as follows.

P (71 '), P (8'),... Also may be defined in the same manner as in the above (1). However, this method is difficult to implement hardware coefficients [1/3, 2/3, 5/6, 1/6] of the filter for rounding, and even multiplication of many bits is required for accurate calculation even if the coefficients are implemented. There was a problem that became necessary.

The present invention is to solve the above-mentioned problems, an object of the present invention is to implement the filter coefficients by judging the image in the ratio of 5: 4 in the vertical direction when displaying a 16: 9 image on a 4: 3 monitor It is to provide a 4: 3 display within a 16: 3 video display device to simplify the operation process and reduce the inconvenience.

Another object of the present invention is to provide a 16: 9 image display device in a 4: 3 screen by implementing a filter for extracting using an adder to implement a letterbox generator having a simple hardware structure and a high speed.

A 16: 9 video display device in a 4: 3 screen of the present invention for achieving the above objects has a ratio of 5: 4 in the vertical direction of a decoded 16: 9 video data in front of a 4: 3 monitor. It is configured by connecting letterbox generators that output letterbox type image data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 6 to 8 as follows.

6 is a video signal state diagram for explaining a method of implementing a 16: 9 letterbox on a 4: 3 monitor according to the present invention. FIG. 6A is a case of Progressive Scan, and FIG. 6B is a case of Interlace Scan. 1, 2, 3,. Is the line number of the original image, and 1 ', 2', 3,... Is a line number of an image for displaying a letter box, and P (n) is an image signal value in n lines. Also, the line marked with black dots is the original line, and the line marked with white dots represents the interpolation line. In FIG. 6a, P (1 '), P (2'), P (3 '), and P (4') are defined as follows.

In FIG. 6B, P (1 '), P (2'), P (3 '), P (4'), P (5 '), P (6'), P (7 ') and P ( 8 ') is defined as:

As such, when the 16: 9 image is deduced at a ratio of 5: 4 in the vertical direction, the denominator of the filter coefficient is 4 or 8, and thus it can be implemented by a very simple operation. The proposed method of the present invention has a disadvantage in that a 16: 9 image cannot be faithfully displayed in a 4: 3 monitor on a 4: 3 monitor, but hardware is very simple. In particular, when the viewer does not know what the original image is, even if the aspect ratio is slightly changed, the viewer does not recognize it.

Figure 7 is a block diagram showing the configuration of the letterbox generator proposed in the present invention, showing an embodiment for the case of the forward scan. The letterbox generator of the present invention is connected to the output terminal of the decoding apparatus shown in FIG. 1B, and the 16: 9 image data output from the adder 15 is deduced in a ratio of 5: 4 in the vertical direction, and then the display apparatus ( 4: 3 monitor). Particularly, in the related art, a filter for extracting is implemented using a shift register (sequential logic), but in the present invention, a filter is implemented using an adder.

When the decoded video signal is input to the letterbox generator of the present invention, the signal is applied to the 1H delay unit 20, the first adder 21 and the second multiplexer 23, respectively. The 1H delay unit 20 delays the input image signal by 1H according to the pixel clock signal of the controller 22 and supplies it to the first adder 21 and the first and second multiplexers 23 and 24, respectively. The first adder 21 adds the input video signal y of the current line and the video signal x of the previous line that passed through the 1H delay unit 20 to obtain an average value of the two input signals [(x + y) / 2. ] Is output to the first multiplexer 23. On the other hand, the letter box generator of the present invention receives a horizontal synchronization signal (Hsync), vertical synchronization signal (Vsync) and the field control signal (Top / Bottom) control unit for controlling the switching operation, write / read operation of each block ( 22).

The first multiplexer 23 under the control of the controller 22 is one of an image signal x passed through the 1H delay unit 20 and an output signal [(x + y) / 2] of the first adder 21. Is selected and output to the second adder 25. Similarly, the second multiplexer 24 under the control of the control unit 22 selects one of the image signal x passed through the 1H delay unit 20 and the image signal y of the current line to add the second adder 25. Will output The second adder 25 adds signals output from the first and second multiplexers 23 and 24 to output the average value of the two input signals to the frame memory 26. The frame memory 26 performs a write or read operation in accordance with the control signals WR and ADDR of the control unit 22 to output data converted at a ratio of 5: 4 while an image is displayed in the letterbox portion.

It is assumed that the image data input from the decoding apparatus in the letterbox generator configured as described above is composed of m bits. If the input signal of the first adder 21 is x and y, x and y represent video signals of the previous line (the line delayed by 1 horizontal sync) and the current line, respectively. First, two input signals (x, y) are added while 0 is input to a carry in terminal (Cin) of the first adder 21. If the least significant bit (LSB) is ignored in the output signal of the first adder 21 and only m bits are taken, the result is the average value of the two input signals [(x + y) / 2]. The input signal of the second adder 25 is the signal [x or (x + y) / 2] selected by the first multiplexer 23 and the signal [x or y] selected by the second multiplexer 24.

Table 1 above shows the states of the control signals S1, S2, WR, and ADDR output from the controller 22. The states of the control signals are converted in the order a → b → c → d → a, and the first and second multiplexers 23 and 24 change according to the state transition point. After adding the two input signals, the second adder 25 ignores the least significant bit (LSB) in the output signal and takes only m bits. At this time, the input result was rounded by inputting 1 to the carry-in terminal Cin of the second adder 25. As a result, one bit shift (divided by two) is achieved by adding two items and ignoring the least significant bit. The frame memory 26 performs a write or read operation in accordance with the control signals WR and ADDR whose states are switched as shown in Table 1 above. Then, the image data converted in the ratio of 5: 4 in the letter box is displayed.

8 is a block diagram showing the configuration of the letterbox generator proposed in the present invention, and shows an embodiment of the case of a catapult scanner. In the embodiment of FIG. 8, each block has the same configuration as the apparatus of FIG. 7, and only adds the third and fourth multiplexers 27, 28 and the third adder 29 to the output of the second adder 25. This configuration is different from FIG. That is, the third and fourth multiplexers 27 and 28 connected to the output terminal of the second adder 25 are controlled by the controller 22. The third multiplexer 27 selects one of an image signal x passed through the 1H delay unit 20 and an output signal of the second adder 25 and outputs the same to the third adder 29. Similarly, the fourth multiplexer 28 selects one of the output signal of the second adder 25 and the image signal y of the current line and outputs it to the third adder 29. The third adder 29 adds signals output from the third and fourth multiplexers 27 and 28 and outputs an average value of the two input signals to the frame memory 26.

The letterbox generator configured as described above should be deduced by separating the top field and the bottom field in the case of the biaxially scanned image data. First, when 0 is input to the carry-in terminal Cin of the first adder 21, two input signals x and y are added to ignore the least significant bit LSB, and the average value of the two input signals [(x + y ) / 2] is obtained. The first multiplexer 23 selects one of x or (x + y) / 2 according to the control signal S1, and the second multiplexer 24 selects one of x or y according to the control signal S2. And output to the second adder 25.

Table 2 and Table 3 above show the states of the control signals S1 to S4, WR and ADDR output from the controller 22. Table 2 shows the same filter coefficients as the case of the top field. In addition, Table 3 shows a case where the bottom field is a filter coefficient different from the forward scan image data. The state of the control signals is converted in the order of a (e) → b (f) → c (g) → d (h) → a (e), and the second to fourth multiplexers 23, 24, 27, 28 ) Changes depending on the state transition point. The second adder 25 adds two input signals while the field control signal Top / Bottom is input to the carry-in terminal Cin, and then calculates an average value by ignoring the least significant bit LSB.

The third multiplexer 27 selects one of x or the output signal of the second adder 25 according to the control signal S3, and the fourth multiplexer 28 selects the second adder 25 according to the control signal S4. One of the output signal or y is selected and output to the third adder 29. The third adder 29 adds the output signals of the third and fourth multiplexers 27 and 28 while 1 is input to the carry-in terminal Cin, and outputs an m-bit video signal ignoring the least significant bit. . The frame memory 26 performs a write or read operation in accordance with the control signals WR and ADDR whose state is changed as shown in Table 2 in the top field and in Table 3 in the bottom field.

As described above, in the present invention, when the 16: 9 image is displayed on the 4: 3 monitor, the image is deduced at a ratio of 5: 4 in the vertical direction. The effect of reducing the hassle of. In particular, since the filter for extracting is configured using an adder, it is possible to implement a letterbox generator that has a simple hardware structure and is fast.

Claims (6)

An apparatus for receiving encoded 16: 9 image data and encoding the same and displaying the same on a 4: 3 monitor, wherein the decoded 16: 9 image data is placed in a vertical direction immediately before the 4: 3 monitor. A 16: 9 video display device in a 4: 3 screen, characterized in that it is configured by connecting a threshold box generator for outputting letter box type image data by deducting a ratio of 4. The apparatus of claim 1, wherein the letterbox generator comprises: a 1H delay unit for delaying the decoded image data by 1H according to the pixel clock signal of the controller in the case of progressively scanned image data; A first adder for adding the decoded image data of the current line and the image data of the previous line passing through the 1H delay unit and outputting an average value of two input signals; A control unit which receives the horizontal and vertical synchronization signals and the field control signal and controls the switching operation and the recording / reading operation of each block; A first multiplexer for selectively outputting image data passing through the 1H delay unit or an output signal of the first adder according to a control signal of the controller; A first multiplexer for selectively outputting image data passing through the 1H delay portion or image data of the current line according to a control signal of the controller; A second adder for adding the signals output from the first and second multiplexers to output an average value of the two input signals; And a frame memory for outputting data converted at a ratio of 5: 4 while displaying an image in the letter box by performing recording or reading operation of the image data output from the second adder according to the control signal of the controller. 16: 9 picture display on a 4: 3 screen. The input terminal of claim 1, wherein 0 is input to the carry-in terminal of the first adder, 1 is input to the carry-in terminal of the second adder, and the least significant bit is discarded from the output signals of the two adders. A 16: 9 video display device in a 4: 3 screen, characterized in that an average value is obtained. 3. The method of claim 2, wherein the letterbox generator outputs the image data or the second adder that has passed the 1H delay unit according to a control signal of the controller between the output terminal of the second adder and the input terminal of the frame memory when the image data is subjected to the parallel scan. A third multiplexer for selectively outputting a signal; A fourth multiplexer for selectively outputting an output signal of the second adder or image data of the current line according to a control signal of the controller; And a third adder for adding the signals output from the third and fourth multiplexers to output an average value of the two input signals to the frame memory. 5. The method of claim 4, wherein a 0 is input to the carry-in terminal of the first adder, a field control signal is input to the carry-in terminal of the second adder, and 1 is input to the carry-in terminal of the third adder. And the least significant bit in the output signal of the third adder and taking only the remaining bits to obtain an average value of the input signals. 5. The method of claim 4, wherein the control unit separates the top field and the bottom field when processing the progressively scanned image data, and controls the top field to have the same filter coefficient as that of the forward-scanned image data. In one case, the 16: 9 video display device in a 4: 3 screen, characterized in that the control is different from the forward scanning.