KR0156425B1 - Synchronous public network interfacing apparatus of atm exchange system - Google Patents

Abstract

The present invention is a part of a BISDN terminal adapter for efficiently matching an existing public network that is operated synchronously to an ATM switch that is operated asynchronously. In particular, the present invention effectively provides an E1 trunk of an existing public network through this. The present invention relates to a synchronous public network access device of an ATM exchange which enables services to be provided through an ATM exchange.

That is, according to the present invention, the unit of PCM data converted to ATM cell is composed of 12 bytes. Accordingly, the memory delay configured at the transmitter and the receiver is basically reduced to 4 ms, and at one time / slot to prevent jitter at the transmitter. Configure the device to transmit data to the network interface module from the time when two corresponding ATM cells are checked, and even if the arrival time of ATM cells is delayed due to congestion in the ATM switch, the existing network interface An object of the present invention is to enable reconstruction of PCM data reconstructed in a module without jitter.

Accordingly, it is very effective to accommodate not only ATM dedicated terminals but also conventionally used terminals by efficiently applying existing public telecommunication networks in configuring an ATM switch.

Description

Synchronous Public Network Interface of ATM Switching System

1 is a block diagram of a synchronous public network connection device of the ATM switch of the present invention.

2 is a detailed block diagram of the network interface module of FIG.

＊ Explanation of symbols on main parts of drawing

100: network interface module

200: IOPM (Input Output Processing Module)

210: ICCB (Input Cell Control Block)

220: OCCB (Onput Cell Control Block)

250,330: FIFO: First In First Out

300: VXT memory controller

310: VXT (Virtual Translation Table)

320: VXT control unit 101: CPU (Central Processing Unit)

102: ROM Array 103: RAM Array

104: signaling message control

105: network interface unit 106: clock generation unit

107: SIPO (Serial Input Parallel Output)

108: PCM memory address generator

109,110: PCM memory section 111: PCM memory section

112: transmission memory control signal generation unit

113: PISO (Parallel Input Serial Output)

114: ATM transmission memory section 115: PIPO for transmission

116: IOPM receiving interface unit 117: IOPM sending interface unit

The present invention is a part of a BISDN terminal adapter for efficiently matching an existing public network that is operated synchronously to an ATM switch that is operated asynchronously. In particular, the present invention effectively provides an E1 trunk of an existing public network through this. The present invention relates to a synchronous public network access device of an ATM exchange which enables services to be provided through an ATM exchange.

In general, subscriber data transmitted to an E1 trunk that provides service in a time division manner is divided into time / slots (T / S), so the size is different from that of an ATM cell. Therefore, in converting the data transmitted and received to match the ATM switch and the E1 trunk, the conversion operation should not affect the call quality.

In this case, the PCM data transmitted through the E1 trunk is operated in one frame unit, and 32 times / slots exist in one frame, and each time / slot accommodates one subscriber and is each 125㎲. Send 1 byte of data. Sending data at the same transmission rate is intended to prevent people from recognizing the gap with their ears when they listen.

On the other hand, in the ATM cell operating method, the ATM switch uses a method of performing switching using the header in a cell composed of a 5-byte header and a 48-byte payload of 53 bytes.

Accordingly, in order to access and operate an E1 trunk, which has a structure of transmitting data by 1 byte in units of 125 ms, generally, data transmitted in units of 125 ms is stored for a predetermined period (125 ms * 48). For this reason, 48 bytes of payload was configured for each time / slot, and then made into an ATM cell. However, this access method takes 6ms only at the receiving end to store 48 bytes of data in actual operation, and again requires 6ms to be stored again.

In addition, when dealing with congestion that may occur inside an ATM switch, it is difficult to predict the arrival time of actually transmitted data differently from an exchange using a conventional time division method, so that the ATM reconfigures an ATM cell. In the process of converting the PCM data of the E1 trunk, jittering occurs, which increases the possibility of difficulty in restoring data at the receiving end.

However, the conventional ATM exchanger is configured to configure the delay between the transmitting and receiving end within 10ms in order to reduce the return loss and echo (Echo) in the data transmitted and received, so the structure that takes 12ms basically above Will cause problems.

Accordingly, in order to solve the above problems, the present invention configures the unit of PCM data converted to ATM cells into 12 bytes, thereby reducing the memory delay configured at the transceiver end to 4 ms and operating the jitter at the transmitter end. In order to prevent this problem, a device is configured to transmit data to the network interface module from the time when two ATM cells corresponding to one time / slot are input. Even if this delay occurs, the purpose of the present invention is to allow reconstruction of PCM data reconstructed in an existing interface module without jitter.

In order to achieve the above object, the synchronous public network access device of the ATM switch of the present invention includes a network interface module connected to a synchronous public network, converting PCM data from a network into an ATM cell, and converting and transmitting data transmitted to the network into PCM data. ; An IOPM including an ICCB for converting an ATM cell output from the network interface module into an ATM cell form in an ATM switching module and transmitting the same to an ATM switching module, and an OCCB for processing the ATM cell output from the ATM switching module; A receiving pipo for storing ATM cells transmitted from an ATM switching module and sequentially outputting the same to the OCCB; When converting an ATM cell inputted from the ICCB into an ATM cell type within an ATM switching module, a cell header is modified with a VPI (Virtual Path Identifier) and a VCI (Virtual Channel VC Identifier) value. And a VXT that attaches an internal cell header, a VXT controller that addresses the data to be updated by the VXT, and a VXT controller that stores the modified data of the VXT generated by the call-up processing module in the ATM switch and sequentially. And a VXT memory controller including a receiving PIPO output to the VXT controller.

The network interface module includes: a CPU performing overall control operations, a ROM array storing a program for operating the CPU; A RAM array which stores a program for operating the CPU and stores a result of the CPU operation; A network interface unit for restoring the PCM data transmitted from the connected network and outputting the serial data, and configuring the data to be transmitted according to the electrical characteristics of the connected network and outputting the data to the network; Signaling of the PCM data restored by the network interface unit is inputted from the CPU and outputted as a signal cell of an ATM to a call-up processing controller in an ATM switch, and a signal signal transmitted from the call-up processing controller is analyzed to provide a common channel signal. A signaling message controller which transmits a signal message to data to be transmitted from the network interface unit to the network by transmitting the signal to the network interface unit; A clock generator which provides a synchronization signal to data inputted and outputted through the network interface unit and provides the same clock to the entire configuration; A SIPO for outputting serial PCM data of the time / slot restored in the network interface unit in units of 1 byte; 12 bytes are composed of PCM data output for each time / slot during the 12 frame periods in the SIPO, and the remaining 36 bytes are configured to store dummy data, and include an area for storing ATM header information. Two PCM memory sections comprising several time / slot memories; A counter constituting a memory address pointer configured therein is initialized by the recovery clock restored by the network interface unit, and a memory block of one of the two PCM memory units is determined, and the number of recovery clocks is counted for 12 frames. A PCM memory address generator for storing data by 12 bytes for each time / slot; When the common channel signal information analyzed by the CPU is used, information on which time / slot data is available is stored, and the header is accessed for valid time / slot of the PCM memory unit by using the same. A PCM memory controller for outputting; A transmission pipo for outputting data output from the PCM memory unit to the ICCB; An IOPM receiving interface unit for recording the information related to the transmitting PIPO and outputting information on the state to the ICCB; An IOPM transmission interface unit for storing information on a data transmission state in the OCCB; ATM address area of the memory is specified by using the header of the ATM cell transmitted from the OCCB, and after storing it, it is completely stored and when the next cycle of data arrives, the ATM immediately outputs previously stored data by time / slot. A transmission memory section; A transmission memory control signal generation unit operating by using a recovery clock generated by the network interface unit to output data stored in the ATM transmission memory unit for each time / slot; And a PISO for converting the data output from the ATM transmission memory unit into a serial unit and outputting the data to the network interface unit.

Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a synchronous public network connection device of the ATM switch of the present invention, and FIG. 2 is a block diagram of a network interface module in FIG.

The configuration of the present invention according to FIG. 1 includes a network interface module 100, an IOPM 200, a receiving PIPO 250, and a VXT memory controller 300.

The network interface module 100 is connected to a synchronous public network and converts PCM data from the network into an ATM cell, and data transmitted to the network is converted into PCM data and transmitted and received.

The IOPM 200 converts an ATM cell output from the network interface module 100 into an ATM cell form in an ATM switching module and transmits the same to the ATM switching module, and the ATM cell output from the ATM switching module. It includes an OCCB 220 to process.

The receiving PIPO 250 stores ATM cells transmitted from an ATM switching module and sequentially outputs them to the OCCB 220.

The VXT memory controller 300 modifies a cell header with VPI and VCI values and attaches an internal cell header when converting an ATM cell input from the ICCB 210 into an ATM cell form in an ATM switching module. And the VXT control unit 320 for addressing the data to be updated to the VXT 310, and the VXT control unit 320 to modify the VXT 310 generated by the call-up processing module in the ATM switch. It includes a receiving pipe 330 for storing and sequentially output to the VXT control unit 320.

The configuration of the network interface module 100 according to FIG. 2 includes a CPU 101, a ROM array 102, a RAM array 103, a network interface 105, a signaling message controller 304, Clock generator 106, SIOP 107, PCM memory unit 109 and 110, PCM memory address generator 108, PCM memory control unit 111, and transmission fipo 115 ), An IOPM reception interface unit 116, an IOPM transmission interface unit 117, an ATM transmission memory unit 114, a transmission memory control signal generation unit 112, and a PISO 113.

The CPU 101 controls the overall operation of the network interface module 100.

The ROM array 102 stores a program for the operation of the CPU 101.

The RAM array 103 stores the operation result of the CPU 101 while storing a program for the operation of the CPU 101.

The network interface 105 restores the PCM data transmitted from the connected network and outputs the serial data. The network interface unit 105 outputs the data to be transmitted according to the electrical characteristics of the connected network.

The serial message control unit 104 analyzes the signaling of the PCM data restored by the network interface unit 105 from the CPU 101, outputs the signal cell of the ATM to the call setup processing control unit in the ATM switch, and sets up the call setup. A signal cell transmitted from the processing control unit is analyzed, converted into a common channel signal, transmitted to the network interface unit 105, and a signal message is put on data to be transmitted to the network from the network interface unit 105.

The clock generator 106 provides a synchronization signal to data input and output through the network interface 105 and provides the same clock for the entire configuration.

The SIPO 107 outputs serial PCM data of the time / slot restored by the network interface unit 105 in units of 1 byte.

The PCM memory unit 109 and 110 are configured with 12 bytes of PCM data output for each time / slot during the 12 frame periods in the SIPO 107, and the remaining 36 bytes are configured to store dummy data. It consists of several time / slot memories including an area for storing ATM header information.

The PCM memory address generator 108 initializes a counter constituting a memory address pointer configured therein by a recovery clock restored by the network interface unit 105, and the two PCM memory units 109 and 110 are initialized. One memory block is determined, and the number of recovery clocks is counted so that 12 bytes of data are stored for each time / slot for 12 frames.

The PCM memory control unit 111 stores information on which time / slot data is available using the common channel signal information analyzed by the CPU 101, and uses the PCM memory unit 109 to store information on which time / slot data is available. The header is accessed for the valid time / slot of 110 and controlled to be output for valid data.

The transmission PIPO 115 outputs data output from the PCM memory units 109 and 110 to the ICCB 210.

The IOPM receiving interface unit 116 records information related to the transmission PIPO 115 and outputs information on the state to the ICCB 210.

The IOPM transmission interface unit 117 stores information about the data transmission state in the OCCB 220.

The ATM transmitting memory 114 designates the address area of the memory by using the header of the ATM cell transmitted from the OCCB 220, stores it and immediately stores it after it is completely stored and the next cycle of data arrives. Output previously saved data by time / slot.

The transmission memory control signal generator 112 operates using a recovery clock generated by the network interface 105 to output data stored in the ATM transmission memory 114 for each time / slot.

The PISO 113 converts the data output from the ATM transmission memory unit 114 into a serial unit and outputs the data to the network interface unit 105.

Operation of the present invention having the configuration as described above is as follows.

First, a process of configuring PCM data transmitted from a network into an ATM cell will be described.

The recovery clock restored by the network interface unit 105 initializes a counter constituting a memory address pointer configured in hardware in the PCM memory address generator 108. In this case, the recovery clock of the PCM memory address generator 108 may be initialized. Internally, a circuit for determining one memory block of the two PCM memory units 109 and 110 and a circuit for counting the number of recovery clocks are configured to store 12 bytes of data for each time / slot for 12 frame periods. Be sure to At this time, the address pointer and the SIPO 107 have a structure in which one byte of data is stored in a memory while one address is designated because of synchronization.

Header information to be assigned to each time / slot in each PCM memory section 109 (110) is modified by the VXT 310 in the ICCB 210 and used for switching inside the ATM switch. That is, when the common channel information transmitted through the trunk line of the access network is analyzed and stored in the signaling message controller 104, it is converted into an ATM signal cell and transmitted to the call setup processing module of the ATM switch. The call information is analyzed by the setup processing module and stored in the VXT 310. As such, when data is transmitted to the ICCB 210 through the transmission PIPO 115 and the IOPM receiving interface unit 116 using the information stored in the VXT 310, the header information is modified to switch inside the ATM switch. It is used for.

When the CPU 101 stores the information in the signaling message controller 104, the CPU 101 analyzes the common channel signal information to store information on which time / slot data is available and uses this information. Therefore, it is determined which data from the data stored in each PCM memory unit 109 (110) is converted into an ATM cell, which is useful for eliminating the burden of data that is not necessary for a limited ATM switch.

The PCM memory section 109 and 110 has a 48-byte address space for each network trunk time / slot, of which only 12 bytes are composed of useful PCM data. It is stored. Each memory has an area for storing ATM header information. Since this area has not been previously allocated, the software has a predetermined value in the ATM header area of the PCM memory unit 109 and 110 at the time of internal initialization. Writes to memory.

At this time, the control is performed by the PCM memory control unit 111 in the process of configuring the ATM cell using the data stored in the PCM memory unit 109, 110, wherein the internal configuration of the PCM memory control unit 111 is time / When the time / slot is valid using the information for determining the validity of the slot, the PCM memory unit 109 is operated by operating two internally configured pointers to access a header and a pointer to designate 48 bytes of PCM data. And a portion for causing data from 110 to be recorded in the transmission piezo 115. When the transmitting PIPO 115 transmits data output from the PCM memory unit 109 and 110, the IOP receiving interface unit 116 records the state information about the data and transmits the data to the ICCB 210. . At this time, the interface between the transmitting PIPO 115 and the IOPM receiving interface unit 116 and the ICCB 210 is controlled using the UTOPIA interface provision provided by ITU-T.

Meanwhile, a process of separating an ATM cell transmitted from an ATM switching module and restoring it to PCM data is as follows.

The storage of the ATM cell transmitted from the OCCB 220 using the UTOPIA interface is performed by designating a memory address area in the ATM transmitting memory unit 114 using the ATM header, wherein the information on the ATM header is addressed. In addition to the role of designating a, it is also used to operate an ATM cell counter existing in the transmission memory control signal generator 112. Here, the transmission memory control signal generator 112 prevents jittering that may occur during the restoration of the PCM data.

In this way, when the data is completely stored in one area of the ATM transmission memory section 114 and the data of the next cycle is confirmed, the transmission memory control signal generator 112 recovers the data provided by the network interface unit 105. The clock is used to operate the pointer inside it. Accordingly, data stored in the ATM transmission memory unit 114 is transmitted to the network interface unit 105 through the PISO 113 for each time / slot, wherein the data is transmitted to the time / slot of each network trunk line. It is allocated and transmitted, and a signal message is carried here. Here, the signal message carried in each time / slot by the network interface unit 105 becomes a common channel signal transmitted from the signal message control unit 104. In other words, the common channel signal is a signal obtained by analyzing the signal cells transmitted from the call-up processing module by the signal message control unit 104 and converting the signal cells into the common signal channel. At this time, the ATM transmission memory unit 114 is configured using a dual port RAM, so that the total delay can be configured within 10ms.

As described above, according to the present invention, it is very effective to accommodate not only an ATM dedicated terminal but also a conventionally used terminal by efficiently applying a conventional public network used in constructing an ATM switch.

Claims (2)

A synchronous public network access device of an ATM switch, comprising: a network interface module connected to a synchronous public network and converting PCM data from a network into an ATM cell, and converting and transmitting data transmitted to the network into PCM data; An IOPM including an ICCB for converting an ATM cell output from the network interface module into an ATM cell form in an ATM switching module and transmitting the same to an ATM switching module, and an OCCB for processing the ATM cell output from the ATM switching module; A receiving pipo for storing ATM cells transmitted from an ATM switching module and sequentially outputting the same to the OCCB; When converting an ATM cell inputted from the ICCB into an ATM cell type in an ATM switching module, a VXT attaches an inner cell header while modifying a cell header with VPI and VCI values, and specifies an address so that data is updated by the VXT. And a VXT memory control unit including a VXT control unit for receiving, and a receiving pipette for storing the modified data of the VXT generated by the call-up processing module in the ATM switch to the VXT control unit and sequentially outputting the modified data to the VXT control unit. A synchronous access network connection device of an ATM switch. The network interface module of claim 1, further comprising: a CPU for performing a total control operation; A ROM array for storing a program for operating the CPU; A RAM array which stores a program for operating the CPU and stores a result of the CPU operation; A network interface unit for restoring the PCM data transmitted from the connected network and outputting the serial data, and configuring the data to be transmitted according to the electrical characteristics of the connected network and outputting the data to the network; Signaling of the PCM data restored by the network interface unit is inputted from the CPU and outputted as a signal cell of an ATM to a call-up processing controller in an ATM switch, and a signal signal transmitted from the call-up processing controller is analyzed to provide a common channel signal. A signaling message controller which transmits a signal message to data to be transmitted from the network interface unit to the network by transmitting the signal to the network interface unit; A clock generator which provides a synchronization signal to data inputted and outputted through the network interface unit and provides the same clock to the entire configuration; A SIPO for outputting serial PCM data of the time / slot restored in the network interface unit in units of 1 byte; 12 bytes are composed of PCM data output for each time / slot during the 12 frame periods in the SIPO, and the remaining 36 bytes are configured to store dummy data, and include an area for storing ATM header information. Two PCM memory sections comprising several time / slot memories; A counter constituting a memory address pointer configured therein is initialized by the recovery clock restored by the network interface unit, and a memory block of one of the two PCM memory units is determined, and the number of recovery clocks is counted for 12 frames. A PCM memory address generator for storing data by 12 bytes for each time / slot; By using the common channel signal information analyzed by the CPU, information on which time / slot data is available is stored, and the header is accessed for valid time / slot of the PCM memory unit using the common channel signal information. A PCM memory controller for outputting; A transmission pipo for outputting data output from the PCM memory unit to the ICCB; An IOPM receiving interface for recording information related to the transmitting PIPO and outputting information on the state to the ICCB; An IOPM transmission interface unit for storing information on a data transmission state in the OCCB; ATM address area of the memory is specified by using the header of the ATM cell transmitted from the OCCB, and after storing it, it is completely stored and when the next cycle of data arrives, the ATM immediately outputs previously stored data by time / slot. A transmission memory section; A transmission memory control signal generation unit operating by using a recovery clock generated by the network interface unit to output data stored in the ATM transmission memory unit for each time / slot; And a PISO for converting data output from the ATM transmission memory unit into a serial unit and outputting the data to the network interface unit.