KR0155797B1 - Digital signal processor - Google Patents

Abstract

In the digital signal processing apparatus according to the present invention, the arithmetic operation unit, the multiplication operation unit, the logic operation unit, the shift operation unit, and the logarithm operation unit are designed to implement the CCITT G.721 ADPCM algorithm with a relatively small size, thereby reducing the price of the digital communication system And low power consumption is particularly suitable for mobile communication systems. In addition, the ADPCM algorithm as well as similar algorithms can be easily implemented by modifying only the program of the instruction ROM.

Description

Digital signal processor

1 is a structural diagram of an operation unit of a conventional DSP processor.

2 is an overall block diagram of a microprocessor implemented by a digital signal processing apparatus according to the present invention.

3 is a diagram showing the state of the microprocessor shown in FIG.

4 is a structural diagram of a pipeline applied to the microprocessor shown in FIG.

5A and 5C are diagrams showing an operation signal, an in-phase or abnormal control signal, and a clock signal of an operation unit, respectively.

6 is a graph showing power consumption during operation of a CMOS circuit.

7a to 7e are diagrams illustrating power consumption according to input / output control.

8 is a circuit for chip verification.

9 is a view showing a clock signal of the microprocessor shown in FIG.

FIG. 10 is a detailed view of the input / output unit shown in FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus, and more particularly, to a digital signal processing apparatus implementing an adaptive differential pulse coded modulation (ADPCM) algorithm widely used in the field of digital communications with a dedicated microprocessor.

At present, the digital communication method is widely used in the communication field to compensate for the shortcomings of the analog method. In voice band data communication, the Pulse Coded Modulation (PCM) method is widely used to encode data into binary signals.In international PCM communication (CCITT Recommendation G.711), a 64 kHz audio signal sampled at 8 kHz is encoded into an 8-bit signal. Transmit at Kbps. This can increase the channel capacity by reducing the transmission rate of PCM data. Therefore, the CCITT adopted Recommendation G.721 ADPCM with a data rate of 32 kbps. The 32 Kbps ADPCM has the effect of doubling the channel capacity while transmitting nearly the same sound quality as the 64 Kbps PCM.

The ADPCM algorithm is currently being applied to many communication systems, and ADPCM is adopted in digital wireless telephones, which are rapidly expanding in the mobile communication field, and ADPCM technology is becoming a core technology in the mobile communication field.

In the existing system, the ACPCM algorithm is implemented as a general-purpose DSP (Digital Signal Processing) processor. However, since general purpose DSP processors are chips developed for general purpose, there are many disadvantages in applying specific algorithms. For example, first, since the size of the data processed by the operation unit is much larger than necessary, many logic elements must be driven for the operation, which requires relatively high power consumption, and becomes a factor that makes the size of the system relatively large. Second, the operating frequency is relatively high, and thirdly, there are many instructions and circuits that are not required for a specific algorithm. Fourth, in order to implement frequently used and simple operation in a specific algorithm in a general-purpose DSP processor, it is necessary to combine several instructions. There is a problem. These problems are a major obstacle to low power consumption, which is essential in the field of mobile communications, such as digital wireless telephones, and increases the price of the system.

FIG. 1 is a structural diagram of a computing unit in a conventional DSP processor, which uses a single ALU for logical and arithmetic operations, and uses a multiplier, a shifter, and the like in the longitudinal direction. In the conventional DSP processor, even though the logic and arithmetic operations are independent operations, processing of one ALU is because the number of gates that are needed without performing one operation is increased rather than a separate structure. Therefore, the increase in the number of operation gates results in an increase in power consumption.

In addition, if each operation block is arranged in the longitudinal direction, if one operation block operates and the output value changes, the input value of another operation block connected to this operation block changes and operates together, thus increasing the number of gates that are not necessary. Let's go. For example, in order to perform multiplication, not only a multiplier but also a shifter connected to a multiplier and an ALU are operated without a need.

In addition, the conventional DSP processor may waste all unnecessary power by processing all the data to be processed and executing the instruction (NO OPRATION, JUMP OPERATION repetition) until the next data is input.

Accordingly, an object of the present invention is to provide a low power consumption digital signal processing apparatus implementing the ADPCM algorithm as a dedicated microprocessor in order to solve the above problems.

Digital signal processing apparatus according to the present invention to achieve the above object

Three independent data buses (BUSA, BUSB, BUSZ);

A clock generator for generating a clock required for the microprocessor;

An input / output unit that provides both parallel input / output and serial input / output for interfacing with the outside;

A control unit for interpreting a stored program, transferring each data through the three independent data buses, and controlling the transfer of control signals and data to control the entire microprocessor function;

An arithmetic unit for performing arithmetic, logic, multiplication, shift, and logarithm operations, each connected to independent data buses in parallel;

A data storage unit for temporarily storing data of the control unit and the input / output unit; And

It is connected to a data bus BUSZ to store instructions and data necessary for ADPCM algorithms and operations, and includes a storage unit for transmitting data through data buses BUSA and BUSB to the control unit, arithmetic unit, and input / output unit. It is done.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, in analyzing CCITT G.721, most operations consist of arithmetic operations such as shift, addition, subtraction, and multiplication, and logical operations such as AND, OR, and exclusive logical sum. Variables range in size from 1 bit to 19 bits, but most variables are less than 16 bits. The number of each memory variable of the encoder and decoder is up to 32.

Since the basic specification of the digital signal processing apparatus according to the present invention conforms to the CCITT Recommendation G.721 standard, the basic data size is 16 bits, and the basic clock frequency of the system is 16.2 KHz in order to use the same system clock to be applied later. . The basic arithmetic functions required are addition, subtraction, multiplication, shift, logarithm, exclusive logical sum, logical product, logical sum, inverter, and two's complement. In addition, the data input / output is maintained to be compatible with the input / output of commercial PCM codec with 8 KHz sampling cycle. PCM input / output is basically designed to receive serial input and output simultaneously in serial. In addition, the PCM input clock uses internally generated or externally selectively. The PCM signal uses the A-LAW, μ-LAW, and 14-bit linear PCMs of the international standard (CCITT G.711). In addition, since the use of constants has many characteristics, ROMs for storing constants are arranged, and system flags include LAW, COMPAND, and flags for one-bit data indicating characteristics of sign, zero, and PCM signal.

On the other hand, the basic form of microinstruction is made up of one word, because the instruction is brought in one clock cycle to improve the performance and easy to interpret without breaking the pipeline.

In the digital signal processing apparatus according to the present invention, the microinstruction is composed of 31 instructions, and since the stack 22 is configured for subprogram calls, only the instructions frequently used in the ADPCM are selected among the instructions of the general processor. In addition, additional commands (ENJUMP, GPM, LOG, etc.) have been added to support the ADPCM algorithm efficiently.

The basic structure of the digital signal processing apparatus according to the present invention is a RISC structure having a pipelined structure for processing one instruction within one period in a Harvard structure that separates instructions and data, as shown in FIG. For this purpose, three buses (BUSA, BUSB, BUSZ) are used, and the input / output unit 38, the control unit 31, the calculation units 32 to 37, the data storage units 22, 23, 24, 27, and the register unit 25, 26, 29, 30, and the clock generator 21.

The register file 36 constituting the above calculation unit is connected to independent buses in a format based on two outputs and one input.

Among these, the clock generator 21 is for supplying a clock required for the system, and generates a clock as shown in FIG. 9 according to the state of the system. The clock basically uses a non-overlap two phase clock that is not overlapped with each other and uses four phases in the calculation units 32 to 37.

On the other hand, for low power consumption, as shown in FIG. 3, a 'SLEEP' state, which is not present in a conventional processor other than a 'RESET' state and a 'RUN' state, is adopted. In the 'SLEEP' state, a system clock is not generated. Do not operate any circuit except the input / output part. 'SLEEP' state is the state until the completion of the encoding and decoding function for the input signal until the next input signal is entered, which can minimize the number of gates operating in the meantime can reduce power consumption. As soon as the next input signal is received, the process returns to the run state (RUN) and performs the encoding and decoding functions again.

Digital signal processing apparatus according to the present invention has the advantage that the instruction fetch cycle is short because the program can be embedded in the chip as compared to the general-purpose DSP processor. In other words, it takes more than one clock time to write an external memory, but the memory inside the chip can support high speed so that data can be read in one clock. It also has an excellent advantage in terms of power consumption. In addition, one of the great features of the digital signal processing apparatus according to the present invention is that all instructions are performed in one clock.

On the other hand, the pipeline has a three-stage pipeline structure and the operation in each stage is the same as in FIG.

Referring to FIG. 4, in step 1F, the instruction is read and the address of the next instruction is calculated. Instead of using the circuit of the calculation unit for this calculation, a separate circuit is processed. This independent circuit checks the jump condition when executing the jump instruction and adds a relative value to the current program counter. In this way, the position of the next instruction is not calculated by the operation unit, and a dedicated circuit is set aside so that the pipeline is not broken by avoiding instruction execution steps and resource conflicts. It also improves processor performance by reading the next instruction in one cycle.

The ID stage interprets the function of the read command and generates all necessary control signals. The control signal generates two signals synchronized with the PHI11 and PHI21 signals. This control signal is used separately for input control and output control when used in the calculation unit. In addition, if the control signal and the clock signal have the same phase with each other, there is a fear that an actual control signal for operating the operation unit may malfunction. To prevent this malfunction, the clocks of different phases are used for the control and clock signals. Most of the operation blocks are performed by a signal obtained by logically multiplying the control signal and the clock signal as shown in FIG. However, if the clock signal and the control signal use the same phase, the control signal is delayed in the actual circuit due to the length of the wire and other causes. Therefore, glitches and the like occur in a portion such as '601' in FIG. 5b, or malfunction. In order to prevent this, as shown in FIG. 5C, a logical product is performed using signals having different phases from each other.

Returning to Figure 5, the EX step takes the data, computes it, and stores the result in a register. In general processor, the indirect addressing method can be used to read the data, but it is not adopted by this processor because it breaks the pipeline. Also, to prevent the pipeline from breaking, the execution time of all instructions is fixed at one cycle.

In addition, three 16-bit buses are used for the transfer of independent data. In the execution of the instruction, the clock uses four phases. This is to prevent a lot of consumption. If two phases are used, the driving time is long because the input bus must be driven simultaneously with the input of the operation block.

Since the power consumption of the CMOS is largely achieved at the moment when the value changes, as shown in FIG. 6, the power consumption of the operation block is proportional to the length of the driving time. This is expressed as a formula as follows.

P NpΔt ..... (1)

In Equation (1), P is power consumption, N is the number of operating gates, p is instantaneous power consumption, and Δt is the instant of voltage change. As shown in Equation (1), power consumption is proportional to the number of gates operated and the change in value. Of course, it is also proportional to the instantaneous power consumption of the device, but this is not a practical design but a problem in the semiconductor process and this cannot be considered during design. Therefore, the microprocessor according to the present invention is designed with the focus on reducing the number of gates operated and minimizing the change time of values. That is, to reduce the power consumption, the time for driving the bus and the time for driving the operation block are separated. To do this, the EX phase uses a four-phase clock, which can also lower the instantaneous maximum current value, making the system more stable.

FIG. 7A shows a part of the register which reads data and operates. A is the register output, A is the input bus and C is the operation. Figure 7b shows the change in the value of part A. This causes the portion B to be driven by the clock signal PHIi to have a value change as shown in FIG. This change in value is related to the bus's resistance and capacitance. FIG. 7D shows a change in the value in the C portion when the clock signals PHIi and PHIj use the same signal. The moment of change of the value here is the time taken to drive the bus and drive the input part of the calculation unit again. FIG. 7E shows the change in the value of the C portion when PHIj is opened after the input bus is driven. The time at this time is a time taken to drive the input of the calculation unit. Comparing FIG. 7D and FIG. 7E, it can be seen that there is a difference in the change of the input value of the C portion having the operation unit that consumes most of the power. As mentioned in FIG. 6, the longer the change interval is, the more power is consumed, so that the 7e degree consumes less power than the 7d degree.

On the other hand, the operation unit consists of an arithmetic operation unit, a multiplication operation unit, a logic operation unit, a shift operation unit and a log operation unit, unlike other general processors, designed to be separated into several parts. This is to reduce the power consumption by minimizing the number of gates operating in one instruction execution and to minimize the time delay of the operation unit. The multiplier also employs a multiplier that calculates 8-bit inputs rather than calculating 16-bit inputs. This is because ADPCM algorithm rarely needs to multiply 8 bits or more. Also, if the 16-bit multiplier is adopted, the operation result is 32-bit data, and the operation result cannot be stored in the register file in one clock period. This is because the disadvantage of breaking the pipeline structure that executes one instruction in a cycle occurs.

Meanwhile, as shown in FIG. 10, the input / output unit provides both parallel input / output and serial input / output as a part in charge of input and output with the outside. Serial I / O reads serially the input sampled at 8 KHz by making it compatible with I / O signals of commercial PCM codec. The output is designed to run simultaneously with the input and provides both short and long sync signals, and the input clock is selectively used either internally or externally. Serial I / O is used to input and output PCM data corresponding to the voice symbol while ADPCM data is input and output in parallel. In parallel input / output, a handshaking method is used, and a flag signal indicating that input or output may be performed and a control signal that actually performs input or output are provided. In other words, if input and output is possible after viewing the flag signal, data is inputted and outputted as a control signal.

On the other hand, since the microprocessor according to the present invention uses a logic automatic synthesis to achieve a process-independent design, the chip cannot be efficiently verified with a simple test vector for chip verification. This is because the actual circuit may vary depending on the conditions and processes being synthesized. It is almost impossible to verify the chip with specific inputs, so there is a need to offer a generalized verification method. In addition, since the core library is intended, using a large number of pins for verification can be a heavy burden on a chip adopting this library. In general, the full scan (FULL SCAN) method is not used because many input signals are required for chip verification.

The method proposed by the microprocessor according to the present invention is a method of verifying various blocks of a processor by operating an important register such as an instruction register (INST.REG) in various ways as shown in FIG.

In order to verify the instruction ROM which will occupy the largest part of the system, the instruction register is operated in data compression mode.In this case, the program counter (PC) is sequentially entered by inputting NO_OP (No Operation) to the next instruction calculating block (NEXT INST). The circuitry of the instruction ROM is verified by reading, compressing, and outputting the data serially externally.

To verify the next instruction counting block (NEXT INST), set the instruction register to random number generation mode and the program counter to data compression mode. It then adjusts the signal value and the generation order with the initial value of the instruction register. After this, verify the circuit by outputting the contents of the program counter to the outside.

In order to verify the stack and the calculation unit, the instruction register is set to a specific instruction, and only the operand is set to a mode in which random numbers are generated. In addition, for the operation unit, insufficient control unit verification is performed by connecting the control register (CTLA), the immediate register (IMM.REG), and the register (BUSZ REG) that stores the value of the bus (BUSZ) from which the operation results are output. do.

In addition, ADPCM algorithm is implemented in the instruction ROM and the program for circuit verification is used in the remaining part.

It is desirable to select an ATPG (Automatic Test Pattern Generator) tool that automatically generates a verification signal after synthesizing the circuits.

Table 1 summarizes the design results of the ADPCM dedicated microprocessor according to the present invention. Here, the size of the system is the result of logical automatic synthesis using the libraries of each LSI company and the library of Samsung Electronics Co., Ltd., and the size of the system except the instruction ROM, which is a macro cell.

In addition, in order to examine the performance of the system, the performance of the system was verified by inputting the actual voice signal and tones of various frequencies. And ADPCM execution time is the maximum value, minimum value, and average value obtained by performing real voice data and each tone data through the emulator, and the amount of data was 203,980 (about 25 seconds) in total.

The microprocessor according to the present invention is currently designed exclusively for ADPCM, but can be used by changing the microprogram to other signal processing algorithms. In addition, if the current structure is maintained and the size of the calculation data or the calculation unit is modified to be suitable for other applications, it can be easily used for other applications such as a microcontroller or communication.

As described above, the digital signal processing apparatus according to the present invention implements the CCITT G.721 ADPCM algorithm with a relatively small size by designing arithmetic operation unit, multiplication operation unit, logic operation unit, shift operation unit, and logarithm operation unit. It is possible to lower the cost of the system and to consider low power consumption, so it is particularly suitable for mobile communication systems. In addition, the ADPCM algorithm as well as similar algorithms can be easily implemented by modifying only the program of the instruction ROM.

Claims (9)

Three independent data buses (BUSA, BUSB, BUSZ); A clock generator for generating a clock required for the microprocessor; An input / output unit that provides both parallel input / output and serial input / output for interfacing with the outside; A control unit for interpreting a stored program, transferring each data through the three independent data buses, and controlling the transfer of control signals and data to control the entire microprocessor function; An arithmetic unit for performing arithmetic, logic, multiplication, shift, and logarithm operations, each connected to independent data buses in parallel; A data storage unit for temporarily storing data of the control unit and the input / output unit; And a storage unit connected to a data bus BUSZ to store instructions and data necessary for ADPCM algorithms and operations, and transmitting data through data buses BUSA and BUSB to the control unit, the calculation unit, and the input / output unit. Digital signal processing device characterized in that. The digital signal processing apparatus of claim 1, wherein the apparatus is a RISC structure having a pipelined structure that processes one instruction in one period in a Harvard structure that separates instructions and data. The digital signal processing apparatus of claim 1, wherein the operation unit performs an operation by a four-phase clock using a clock having two phases that do not overlap each other. The digital signal processing apparatus of claim 1, wherein the apparatus adopts a 'RESET' state, a 'RUN' state, and a 'SLEEP' state. 5. The method of claim 4, wherein the 'SLEEP' state is a state until the encoding and decoding functions of the input signal are completed and before the next input signal is input, so that no system clock is generated so that all circuits except the input / output unit do not operate. Digital signal processing apparatus, characterized in that. The digital signal processing apparatus of claim 1, wherein the serial input / output unit is used to input / output PCM data corresponding to a voice signal, and the parallel input / output unit is used to input / output ADPCM data. 7. The digital signal processing apparatus according to claim 6, wherein the parallel input / output includes a flag signal indicating that input or output may be performed and a control signal that actually performs input or output. The digital signal processing apparatus according to claim 1, wherein the multiplication operation part of the operation unit is an 8-bit multiplication operation. The pipeline structure of claim 1, wherein the pipeline structure adopted by the device comprises: reading an instruction and calculating the address of the next instruction, interpreting the function of the instruction being read, bringing data and operating the result and then writing the result to a register. Digital signal processing apparatus comprising the step of storing.