KR0154696B1 - Synchronous pattern recording and detecting circuit of digital recording/reproducing apparatus - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to a digital recording / reproducing apparatus, and more particularly, to a digital recording / reproducing apparatus which inserts and records a synchronization pattern in recording information of a digital recording / reproducing apparatus, detects the inserted synchronization pattern, and reproduces recording information without errors. . The apparatus inserts and records a synchronization pattern distinguished from the information word between information words at a predetermined interval for synchronization with recording information words during reproduction, and detects the synchronization pattern during transmission and transmits the reproduction data in units of information words. The data transmitter is transmitted in synchronization with the detected sync pattern. By recording and reproducing the information word as described above, it is possible to prevent an error of data reproduction occurring in accordance with the initial position of the head.

Description

Synchronous pattern recording and detection circuit of digital recording and reproducing apparatus

1 is a block diagram of a conventional digital recording / reproducing apparatus.

2 is a synchronous pattern recording circuit diagram of a digital recording and reproducing apparatus according to the present invention.

3 is a synchronous pattern detection circuit diagram of a digital recording and reproducing apparatus according to the present invention.

4 is an operation timing diagram of FIG.

5 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording / reproducing apparatus, and more particularly, to a digital recording / reproducing apparatus for inserting and recording a synchronization pattern in recording information of a digital recording / reproducing apparatus, and detecting the inserted synchronization pattern to reproduce recording information without errors. It is about.

Over the past few years, signal processing apparatuses focusing on audio and video equipment have been rapidly developed. In addition to signal processing, it is mainly focused on FM modulation not only for recording / reproducing digital information on recording media such as magnetic tapes. In the recording and reproducing method of log signals, digital recording / reproducing mainly on digital modulation / demodulation has been steadily studied. In general, when a predetermined signal is to be recorded on a recording medium as a digital recording / reproducing apparatus, the signal must be processed as parallel digital data. The parallel data is converted into serial data and recorded on the recording medium. When reading information recorded on the recording medium, serial data is converted into parallel data and outputted. The reason why parallel digital data cannot be recorded / reproduced as it is on a recording medium such as a magnetic tape as described above is that parallel data cannot be simultaneously recorded / reproduced as one head. Therefore, the digital recording / reproducing apparatus for recording / reproducing digital data is configured to process the data in parallel in the order of parallel / serial conversion → recording → replay → serial / parallel conversion. Therefore, such a digital recording / reproducing apparatus converts a serial signal into parallel information when performing recording / reproducing on a recording medium such as a magnetic tape after performing digital signal processing. Such apparatuses include digital VCR, DAT, This can be useful for CDP and LDP.

1 is a block diagram of a conventional digital recording / reproducing apparatus, comprising: a latch circuit 12 for latching and outputting an input write data word W-DW by a clock (1/8 CLK); A parallel to serial converter (PSC) 14 for converting parallel data output from the latch circuit 12 into serial data by input of a shift clock CLK, and outputting from the PSC 14; A recording amplifier (REC-A) 16 for amplifying and outputting serial data to be output, the head 18 for recording and picking up data output from the recording amplifier 16 on the magnetic recording medium 30; A reproduction amplifier 20 for amplifying the signal output from the head 18 to a predetermined level, a data detector 22 for waveform shaping and outputting the amplified signal as data, and the data detector 22 Converts serial data output from the parallel data into parallel data by a predetermined clock (CLK). Serial to parallel converter (SPC) 24 and parallel data output from the SPC 24 are latched by the clock (1/8 CLK) to read a read data word (R-). A latch circuit 26 for outputting DW).

First, in describing the operation of the digital recording / reproducing apparatus in FIG. 1, the information word W-DW is assumed to be 8 bits.

Now, when the information word W-DW made of parallel data is input, the information word W-DW is input to the latch circuit 12. At this time, the latch circuit 12 latches the input information word W-DW by an input clock (1/8 CLK) to input 8-bit data to the PSC 14. The PSC 24, which has input the latched 8-bit data, is inputted by the clock CLK having a speed eight times the frequency of the clock 1/8 CLK input to the latch circuit 12. The parallel data is converted into serial data SD to output a pulse train signal to the write amplifier 16. For example, when the information word W-DW of 73H (hexa) is continuously input to the latch circuit 12, the data output from the PSC 14 becomes 1110011. The pulse string output as described above is amplified by a signal of a predetermined level via the write amplifier 16 and input to the head 18. The head 18 magnetically records a signal corresponding to the input pulse train on the tape 30 as a recording medium.

When the data recorded by the above operation is reproduced, the head 18 picks up and outputs the information recorded on the tape. The data to be reproduced at this time is picked up in the same order as the recording order of the serial data recorded on the magnetic tape 30. The signal picked up by the head 18 is amplified by the reproduction amplifier 20 into a signal of a predetermined level and then input to the data detector 22. The data detector 22 which inputs the signal amplified to a predetermined level waveform-shapes the input signal and inputs it to the SPC 24 as digital data (P-SD) having logic high and logic low levels. The SPC 24, which inputs the serial data detected as digital data, shifts the serial data by the input clock CLK and converts the serial data into parallel data having the same information word input at the time of recording. The parallel data output from the SPC 24 is locked in the latch circuit 26 by a clock (1/8 CLK) having a period eight times the period of the clock CLK, thereby reproducing the data R-DW. Is output.

At this time, the clock CLK input to the PSC 14 and the SPC 24 has eight times the frequency of the clock (1/8 CLK) input to the latch circuits 12 and 26 in the above description. The reason is to convert the information word into serial data in one information word transmission time. However, such a conventional circuit has a problem of frequently generating errors of recorded information words. That is, there has been a problem that an error occurs in the reproduction of the information word depending on the initial reproduction position of the head 18 during reproduction.

For example, as information words inputted in parallel are inputted with 73H and 2CH, serial data of 1110011 and 101100 is recorded on the tape 30, and when they are reproduced, they are outputted as 1110011 and 101100. When converting the serial data output as described above into parallel data, the parallel data of 73H and 2CH is output only when the serial data is shifted as described above. There has been a problem that information errors and reproduced information words are different from each other and thus a reproduction error may occur. That is, the information words W-DW having values of 73H and 2CH are converted into 73 (h) and 2C (h) in parallel / serial conversion so that binary information of 1110011 and 101100 is recorded on the tape 30. When the recorded information is picked up and converted into parallel data, it must be converted to 73H, 2CH, and the head 18 is shifted by one bit recording section or several bit recording sections. When data of 0 is picked up, data of D6H and 58H are output as reproduction data, and an information word different from the recorded information word is output, causing a data error. Therefore, the conventional circuit as described above has a problem in that it becomes a different information word depending on the position of a reproducing head that picks up the information recorded on the tape, and thus there is a problem that it cannot be used in a system that records a large number of information words. come.

It is therefore an object of the present invention to provide a synchronization pattern recording and detecting circuit of a digital recording / reproducing apparatus for accurately reproducing and outputting a recording information word in a system for converting parallel information words into serial digital information for recording / reproducing.

Another object of the present invention is to provide a synchronization pattern recording apparatus of a digital recording and reproducing apparatus which inserts and records a synchronization pattern for synchronization during reproduction in a specific section of a parallel information word to be recorded.

It is still another object of the present invention to provide a synchronization pattern detection circuit of a digital recording / reproducing apparatus for detecting a synchronization pattern and reproducing the reproduction data in the same manner as the recording data.

The present invention for achieving the above object is a sync pattern recording and detecting circuit of a digital recording and reproducing apparatus for recording a digital information word on a magnetic recording medium through a head, picking up information recorded on the recording medium, and outputting a waveform. A synchronization pattern insertion means for outputting a recording information word and outputting a synchronization pattern in response to a synchronization pattern insertion control signal input at a predetermined period, and dividing a main clock of a predetermined period by the number of bits of the information word to latch the data. A latch circuit for latching parallel data output from the synchronization pattern insertion means in response to an input of a data latch clock outputted from the first divider, and outputting latch data; The serial data latched and outputted from the circuit is shifted by the main clock as described above. Recording data generating means for converting and supplying to the head, reproducing data detecting means for converting the picked-up serial data input by the main clock into parallel data, and detecting the reproducing data in response to an input of a data transmission clock. Reproduction data transmission means for latching the parallel data outputted from the means and transmitting the reproduction data as reproduction data; and comparing the parallel data outputted from the reproduction data detection means with a preset synchronization pattern to generate a data synchronization reproduction signal when the two values match. And synchronizing the main clock by the number of bits of the information word in synchronization with the synchronous reproduction signal generating means for outputting and the synchronous reproduction signal outputted from the synchronous reproduction signal generating means, and outputting the same to the data transfer clock of the reproduction data transmission means. Number of data transfer clocks It is characterized by consisting of stages.

Hereinafter, an operation of a preferred embodiment according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a synchronous pattern recording circuit diagram of a digital recording and reproducing apparatus according to the present invention, wherein a recording information word (W-DW) and a sync pattern (Sync-pattern) (hereinafter referred to as SPT) are inputted to the recording information word (W-DW). ) And a data latch for eight divisions of the synchronization pattern inserter 32 for selecting and outputting the synchronization pattern SPT in response to the synchronization pattern insertion control signal Sync-s, and a predetermined clock CLK. The sync pattern inserter in response to an input of a first divider 34 outputting a clock (1/8 CLK = DLC) and a data latch clock DLC output from the first divider 34. The latch circuit 36 outputs the latch data L-DATA by latching the parallel data output from 32, and the parallel data L-DATA latched output from the latch circuit 36 is clocked. It consists of the PSC 38 which shifts by CLK, converts into serial data SD, and outputs it to a write amplifier.

In the configuration of FIG. 2, the sync pattern inserter 32 differs from the upper nibble bit of the write information word W-DW and the sync pattern SPT according to the logic of the sync pattern insertion control signal Sync-s. A first multiplexer (hereinafter referred to as MUX) 32a that selects and outputs one of the nibble bits, and a write information word W-DW input according to the logic of the sync pattern insertion control signal Sync-s. And a second multiplexer 32b for selecting and outputting one of the lower nibble bits and the lower nibble bits of the sync pattern SPT. The output of the PSC 38 is connected to the input terminal of the recording amplifier 16 of FIG. 1 as described above, and outputs the serial-converted data as a signal for recording.

3 is a synchronous pattern detection circuit diagram of the digital recording and reproducing apparatus according to the present invention, which converts serial data P-SD input by a predetermined clock CLK into parallel data PD and outputs the same. And a latch circuit 42 for latching and transmitting parallel data PD output from the SPC 40 as regeneration data in response to the input of the data transfer clock DTC, and outputting from the SPC 40. A comparator 44 which compares the parallel data PD and a preset synchronization pattern SPT and outputs a data synchronization reproduction signal RET when the two values match, and the predetermined clock CLK. ) Is divided into 8 in synchronization with the synchronization reproduction signal RET output from the comparator 44, and is output to the data transfer clock DTC of the latch circuit 42.

Reference numeral 48 in the configuration of FIG. 3 denotes an inverter, which inverts a clock (1/8 CLK) output by dividing the clock CLK by eight divisions in the divider 46 so that the latch circuit 42 of the latch circuit 42 is inverted. It is output to the data transmission clock (DTC). Accordingly, it can be seen that the inverter 48 is not necessary if the latch circuit 42 latches the data at the falling edge of the input clock. The input of the circuit constructed as shown in FIG. 3 is connected to the data detector 22 of FIG.

FIG. 4 is an operation timing diagram of FIG. 2, in which the sync pattern SPT preset in parallel with the parallel data and the parallel data in FIG. 4 is written by the sync pattern insertion control signal Sync-s. A process of inserting and recording a sync pattern in a specific section of FIG.

FIG. 5 is an operation timing diagram of FIG. 3, in which a synchronization pattern SPT is inserted for each specific section, and the parallel data PD picked up during reproduction of the recorded information is compared with the synchronization pattern SPT preset with the parallel data. The process of transmitting the reproduction data according to the logic of the output of the data synchronization reproduction signal RET, which is a result signal, is shown.

Hereinafter, operations of FIGS. 2 and 3 according to the present invention will be described in detail with reference to FIGS. 4 and 5, and it is assumed that the information word and the synchronization pattern are each 8 bits of information. A period of T + Δt is called one frame, and an example of transmitting N parallel data during the T period of the frame period will be described. At this time, the transmission time of the parallel data has a transmission period of Δt.

[Recording of data]

Now, at each input terminal of the first and second MUXs 32a and 32b of FIG. 2, a parallel information word (W-DW) such as FIG. 4 (a) and a synchronization pattern (such as FIG. 4 (b) When the SPT is inputted, the first and second MUXs 32a and 32b are connected to the parallel information word W-DW or the logic information according to the logic of the synchronization pattern insertion control signal Sync-s input to the control terminal SEL. One of the sync patterns SPT is selected and output to the latch circuit 36.

For example, when the sync pattern insertion control signal Sync-s is low as shown in FIG. 4E, the first and first MUXs 32a and 32b are parallel information of the two inputs, respectively. The W-DW is selected as shown in FIG. 4C and output to the latch circuit 36. If the sync pattern insertion control signal Sync-s is input high, the first and first MUXs 32a and 32b respectively set the sync pattern SPT of the two inputs to FIG. Selection is also made to supply the latch circuit 36.

The first and second MUXs 32a and 32b are connected to the parallel information word W-DW or the synchronization pattern SPT according to the logic of the synchronization pattern insertion control signal Sync-s input to the control terminal SEL. One of them is selected as shown in FIG. 4 (c) and outputted to the latch circuit 36. Therefore, the parallel information word W-DW is outputted N bytes for the T time of the frame (Frame = T + Δt), and the output period of the synchronization pattern insertion control signal Sync-s is the Δt time after the T time of the frame. Is outputted, the N parallel information words (W-DW) are output from the first and second MUXs 32a and 32b, and as shown in FIG. Is inserted and output.

In the state where the first and second MUXs 32a and 32b are operated as described above, the first divider 34 divides the clock CLK input as shown in FIG. A data latch clock (DLC) such as) is supplied to the latch circuit 36. Accordingly, the latch circuit 36 stores parallel data output from the first and second MUXs 32a and 32b as shown in FIG. 4C at the rising edge of the data latch clock DLC. The latched data L-DATA is output to the PSC 38 by latching as in g). At this time, the PSC 38 shifts the latch data L-DATA by the clock CLK and outputs serial data SD converted as shown in FIG. The data converted into serial data in the PSC 38 is recorded on the tape through the write amplifier and the head as described above in FIG. Therefore, the synchronization pattern is inserted and recorded at regular intervals between the constant information word and the information word by the circuit of FIG.

[Playback of data]

When the tape of the synchronization pattern SPT is inserted and recorded by the circuit of FIG. 2 is reproduced, the signal picked up from the head is input to the data detector 22 through the reproduction amplifier 20 described above in FIG. The serial data P-SD (see FIG. 5A), which is its output, is input to the SPC 40 of FIG. The SPC 40 inputting the serial data P-SD as shown in FIG. 5 (a) receives the reproduction serial data P-SD by the clock CLK input as shown in FIG. 5 (c). Shift is converted to parallel data PD as shown in FIG.

The converted parallel data PD is output to the comparator 44 and the latch circuit 42, respectively. At this time, the parallel data PD output from the SPC 40 and the same sync pattern SPT as the above-described sync pattern SPT of FIG. 2 are transferred to the data terminals Q7 to Q0 and P7 to P0. The comparator 44, which inputs each, compares the inputs of the two data and outputs a logic low signal to the output terminal (/ P = Q) when the data is matched, and outputs a logic high in the other cases.

If the second divider 46 is initially reset in the above operating state, the divider 46 outputs a clock 1/8 CLK divided by eight divisions of the clock CLK. That is, the clock 1/8 CLK whose phase is inverted in Fig. 5H is output to the inverter 48. The inverter 48 inverts the clock (1/8 CLK) output from the second divider 46 to clock the data transfer clock DTC as shown in FIG. Supply to the terminal. Therefore, in the case where the parallel data PD of FIG. 5d converted into parallel data is normally reproduced data, the same data as the recording information word is generated by the data transfer clock DTC of FIG. 5h. It is output from the latch circuit 42.

When the synchronization pattern SPT (SPT = Sync) is output from the PSC 40 during the operation, the comparator 44 outputs an active-low data synchronization reproduction signal RET of the second divider 46. Output to the clear terminal. After the second divider 46 is cleared by the data synchronization regeneration signal RET of the active row, the second divider 46 is divided by eight to output the data transfer clock 1/8 CLK whose phase is inverted. It can be seen that the frame period for recording the information word is synchronized whenever the synchronization pattern is detected. That is, the data synchronization and the reproduction signal RET of the active low output from the comparator 44 clear the second divider 46, and count the number of clocks of the main clock CLK from this time. The transfer clock (1/8 CLK) DTC is supplied to the data latch circuit 42 to transfer data.

As described above, in the circuit of FIG. 3, the rising edge signal of the clock (1/8 frequency of the main clock) that appears after 8 cycles of the clock CLK transmits the data of the latch circuit 42 so that the synchronization pattern SPT is reduced. Until it is read, the input information word is output as it is, but once the sync pattern (SPT) is read, the correct information word is reproduced and output.

As described above, the present invention inserts and records a synchronous pattern at a predetermined interval when recording digital information on a magnetic recording medium, and transmits the information to the reproduction information in synchronization with the detection of the synchronous pattern during reproduction. Error reproduction due to an error can be prevented, and the recording / reproducing efficiency of the system can be improved.

Claims (5)

In a synchronous pattern recording and detecting circuit of a digital recording / reproducing apparatus for recording digital information words on a magnetic recording medium through a head, and picking up the information recorded on the recording medium and outputting a waveform, the recording information words of the input parallel data Sync pattern inserting means for outputting a parallel pattern and outputting a parallel sync pattern in response to a sync pattern insertion control signal input at a predetermined period; A first divider for dividing a main clock of a predetermined period by the number of bits of the information word and outputting a data latch clock, and outputting from the sync pattern inserter in response to an input of a data latch clock output from the first divider A latch circuit for latching parallel data to output latch data, write data generating means for shifting the parallel data latched and outputted from the latch circuit by the main clock, converting the parallel data into serial data, and supplying the data to the head; Reproduction data detection means for converting the picked-up serial data inputted by the main clock into parallel data and outputting the parallel data; In response to the input of the data transmission clock, parallel data output from the reproduction data detector is latched and transmitted as reproduction data, and the transmission means compares the parallel data output from the reproduction data detection means with a preset synchronization pattern. And synchronizing the main clock by the number of bits of the information word in synchronization with the synchronous reproduction signal generating means for outputting a data synchronization reproduction signal when the two values match; And a data transfer clock generating means for outputting the same as the data transfer clock of the reproduction data transfer means. 2. The apparatus of claim 1, wherein the sync pattern inserting means comprises: a first multiplexer for selecting and outputting an upper nibble bit of a recording information word or an upper nibble bit of a sync pattern according to logic of the sync pattern insertion control signal; And a second multiplexer for selecting and outputting a lower nibble bit of a write information word or a lower nibble bit of a sync pattern input according to a logic of a sync pattern insertion control signal. A synchronization pattern recording circuit of a digital information recording apparatus for recording a digital information word to a magnetic recording medium through a head, the recording information word W-DW being input by inputting a recording information word W-DW and a synchronization pattern SPT. ) And a sync pattern inserter 32 for selecting and outputting the sync pattern SPT in response to a sync pattern insertion control signal Sync-s, and a predetermined clock CLK as a bit of the information word. The sync pattern inserter in response to an input of a first divider 34 for dividing by a number and outputting a data latch clock DLC, and a data latch clock DLLC output from the first divider 34. The latch circuit 36 for latching the parallel data output from (32) to output the latch data (L-DATA), and the parallel data (L-DATA) latched for output from the latch circuit 36 are described above. Shift by clock CLK, convert to serial data SD, and output to write amplifier Is a circuit which is characterized in that consists of a PSC (38). The synchronization pattern inserter 32 selects and outputs an upper nibble bit of a recording information word or an upper nibble bit of a sync pattern according to a logic of the sync pattern insertion control signal Sync-s. And a second multiplexer 32b for selecting and outputting a lower nibble bit of a write information word or a lower nibble bit of a sync pattern according to the logic of the sync pattern insertion control signal. Circuit. A synchronous pattern detection circuit of a digital recording / reproducing apparatus, which records a digital information word and a synchronization pattern to be recorded on a magnetic recording medium through a head, and reproduces the recorded digital information word. The SPC 40 converts the serial data P-SD input by the predetermined clock CLK into parallel data PD and outputs the parallel data PD, and the SPC 40 in response to the input of the data transfer clock DTC. The latch circuit 42 for latching the parallel data PD outputted from the LPC to be transmitted as reproduction data is compared with the parallel data PD outputted from the SPC 40 and a preset sync pattern SPT. The comparator 44 outputs the data synchronization reproduction signal RET when the two values match, and the predetermined clock CLK is written in synchronization with the synchronization reproduction signal RET output from the comparator 44. And a divider (46) for dividing as many bits as information words and outputting them to the data transfer clock (DTC) of the latch circuit (42).