KR0154568B1 - Multiplexer/demultiplexer for subscriber's connection of manual optical communication network cable television - Google Patents

Abstract

The present invention provides multiplexing means (11) for multiplexing internal signals to generate data of a predetermined rate; And demultiplexing means (12) for demultiplexing predetermined low-speed data transmitted from a plurality of subscribers into an internal signal, so that three subscribers are available as one 155.52Mb / s signal. By lowering the speed to 25.92Mb / s, the three subscribers can use the system jointly, which not only increases the availability of the signal channel but also reduces the cost, and also combines the multiplexing and demultiplexing devices into one. Rather, the present invention relates to a multiple / demultiplexing device for subscriber connection of a PON optical cable television having an effect of making it possible to relatively reduce the size by manufacturing three subscribers in one integrated device.

Description

Multi / Demultiplex Device for Cable TV Subscriber Access in Passive Optical Network

1 is a configuration diagram of an optical CATV network of a general passive optical communication network (PON).

2 is a block diagram of a conventional molded optical CATV network.

3 is a block diagram of an embodiment of a multiplexing / demultiplexing device for cable television subscriber access of a passive optical network (PON) according to the present invention;

4 is a block diagram of an embodiment of the 155.52 Mb / s multiplexer of FIG.

FIG. 5 is a block diagram of an embodiment of the 25.92 Mb / s demultiplexer of FIG.

6 is a diagram illustrating an embodiment of a 51.84 Mb / s frame according to the present invention.

7 is a diagram illustrating an embodiment of a 25.92 Mb / s frame according to the present invention.

FIG. 8 is an operation timing diagram of the phase alignment unit of FIG. 4 and the bit synchronization unit of FIG.

* Explanation of symbols for main parts of the drawings

11: 155.52 Mb / s multiplexer 12; 25.92 Mb / s Demultiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multiplex / demultiplexing device for subscriber access of a cable television (CATV), in particular a passive optical network (PON) for constructing a subscriber network using passive optical elements. The present invention relates to a multiple / demultiplex device for optical cable television (CATV) subscriber access.

In general, in the optical CATV, as shown in FIG. 1, multiple / multiple data are used to transmit data between line termination (LT) which is an end of a distribution network and network termination (NT) which is an end of a subscriber network. The demultiplexer is mainly used.

As a network structure in transmitting data between the line termination and the network termination of the optical CATV system, as shown in FIG. 2, the uplink and the downlink both have the same transmission rate of 155.52Mb / s. It is intended to be occupied and used by a subscriber.

However, in such a structure, the number of service channels provided to one subscriber is large, but there is a problem in that the upstream channel wastes the signal channel because the amount of the actual signal for the available signal is small. In addition, since an integrated device having a multi / demultiplex function used for a subscriber access device located at the end of a line must be used per subscriber, when the number of subscribers is increased, the size of the subscriber access device is very large, which leads to a costly problem. .

Accordingly, the present invention has been made to solve the above problems, the three subscribers to share a single optical path, in which the passive optical transmission and reception by multiplexing and demultiplexing the signal between the line termination and network termination An object of the present invention is to provide a multiplex / demultiplex device for cable television subscriber access of a communication network.

In order to achieve the above object, the present invention provides a multiplex / demultiplexing system for a subscriber station (PON) optical cable television subscriber access provided at a line end portion of an distribution network connected to a network end portion of an subscriber network. In the apparatus, it is disposed in the end of the line, generates a predetermined clock, receives a video signal (DS3) and channel data from the outside to generate a frame, and multiplex the generated frame to multiple subscribers Multiplexing means; And demultiplexing means disposed at the line termination part and demultiplexing the frame signals transmitted from the plurality of subscribers and transmitting the demultiplexed frames to the upper end according to the clock transmitted from the multiplexing means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 7.

The basic principle of the present invention will be described in detail as follows.

First, the downlink signal means a signal sent from the subscriber access device located at the end of the line to the subscriber device located at the network end, and the uplink signal means a signal sent from the subscriber device to the subscriber access device.

The downlink signal is multiplexed by nine 64 Kb / s signals, three 2.048 Mb / s signals, and three DS3 (44.736 Mb / s) signals in the subscriber access device through the optical path to the subscriber device at a transmission rate of 155.52 Mb / s. The subscriber device demultiplexes this into the reverse process of multiplexing. Among the signals multiplexed at 155.52 Mb / s, the subscriber device generates a polling signal, which is a signal indicating the time that the subscriber device can transmit a signal to one 2.948 Mb / s signal channel, and sends it to the subscriber device. The subscriber device can send a signal to the subscriber device only at the time determined by the polling signal.

The uplink signal analyzes the polling signal at the subscriber device, multiplexes two 2.048Mb / s signals and two 64Kb / s signals at a predetermined time, and transmits the signal to the subscriber device using the optical path at a transmission rate of 25.92Mb / s. The subscriber access device demultiplexes the uplink signal into the reverse process of multiplexing.

The construction and detailed operation of the present invention will be described based on the system currently being developed.

3 is a block diagram of a 155.52 Mb / s multiplexer and a 25.92 Mb / s demultiplexer according to the present invention.

The present invention is configured to be used by three subscribers as shown in the figure.

The downlink signal is inputted to the subscriber device 1, the subscriber device 2, and the subscriber device 3 using the passive optical device. On the contrary, the uplink signal is combined with the signals transmitted from the subscriber device 1, the subscriber device 2, and the subscriber device 3 from the passive optical device.

The 155.52 Mb / s multiplexer 11 includes three image (DS3) (44.736 Kb / s) signals, three 2.048 Kb / s signals (B channel, 2B + D channel and polling signal) and nine 64 Kb / s signals. With the frameword, channel number discrimination and parity check bits, the frame is first composed of 51.84Kb / s as shown in Fig. 6, and then the seven-stage scrambler is used by CCITT's recommendation for the part except the frameword. After encryption, three /51.84Mb/s signals are simply bit-multiplexed into 155.52Mb / s and transmitted to the subscriber. The internal signal is 4-bit parallelized to slow down, reduce power consumption and increase reliability.

The 25.92Mb / s demultiplexer 12 phase-aligns the 25.92Mb / s signal from the three subscribers in the bit synchronization circuit, selects the subscriber using the frameword among the signals, and then analyzes the encrypted signal. It demultiplexes into two 2.048Mb / s signals (B and 2B + D) and two 64Mb / s signals (channel selection / maintenance) per subscriber, and checks for parity errors to detect 10e if 123 parity errors occur in 1536 ms. -6, If 12,288 parity errors occur during the same time, 10e-4 error alarm is generated, and this alarm is maintained for at least 78㎲ and repeats the inspection and initialization process at intervals of 1536ms.

The 25.92 Mb / s demultiplexer 12 generates a Loss of Signal Loss (LOS) alarm if the frame synchronization continues to be lost for more than 4 ms, and maintains this alarm until frame synchronization is acquired again. The internal signal is 6-bit parallelized to slow down, reduce power consumption and increase reliability.

4 shows a lower functional block diagram of the 155.52 Mb / s multiplexer of FIG. 1, and the functional blocks 21 to 29, 210, and 211 in the drawing represent functional blocks (frames) that constitute one 51.84 Kb / s frame. The 155 Kb / s multiplexer 212 is a multiplexing function that produces 155.52 Mb / s. The 155 Kb / s multiplexer 212 uses a 51.84 Mb / s frame, which is an output of each of the three frames, as an input signal.

As shown in FIG. 4, the multiplexer of FIG. 3 includes a phase aligner 21, an adjustment signal generator 22, a clock generator 23, a frameword generator 24, and an image. Signal DS3 speed converter 25, 2.048 Mb / s signal speed converter 26, 64 Mb / s signal speed converter 27, channel number generator 28, and 64 Mb / s clock A generation unit 29, a 51.84 Mb / s frame generation / encryption unit 210, a parity generation unit 211, and a 155 Mb / s frame multiplexer 212 are provided.

The operation of the multiplexer of FIG. 3 having the structure as described above will be described in detail as follows.

The phase aligner 21 removes the phase shift on the path of the input DS3 signal (44.736 Kb / s) and aligns it with the timing (clock) used in the multiplexing device, as shown in FIG. A series of four generation clocks having a phase difference of 90 degrees (4 generation clocks having a phase difference of 0 degrees, a generation clock 2 having a phase of 90 degrees, and a generation clock having a phase of 180 degrees using a 44.736 MHz clock having two phase differences of 90 degrees from outside A generation clock 4 having a phase of 270 degrees is used to retime the input signal into four signals (retimed signal 1, retimed signal 2, retimed signal 3, retimed signal 4). Then select the most stable clock and the phase relationship of the signal from the signal and match it again with the timing used in the multiplexing device. Since the signal transition point of the input signal is between the generation clock 2 with the phase 90 degrees and the generation clock 3 with the phase 180 degrees, the value of the four input signals re-timed in the rising transition of the four generation clocks is the retimed signal 2. And the retimed signal 3 is different from each other. Comparing the value of the retimed signal based on the same principle, the signal transition point of the input signal can be known, and thus, it is possible to determine the phase relationship between the most stable clock and the input signal among the four retimed signals. . In addition, instead of continuously monitoring and determining the signal phase relationship for stabilizing the bit synchronization function, the signal phase is periodically checked at intervals of about 4 ms. Here, the retimed signal 4 is the most reliable signal.

As shown in FIG. 6, the adjustment signal generation section 22 generates various adjustment signals necessary for constructing a 51.84 Kb / s signal frame, and is configured as an 810 binary counter and a decoder.

The clock generator 23 uses the output of the decimal counter as an input signal to generate an enable signal so that it can be selectively multiplexed among a plurality of input signals, and generates a 51.84 Kb / s signal having two phase differences of 10 degrees. It is used to construct three 51.84Mb / s frames by generating a clock with three phase differences of 120 degrees from the outside and multiplexes to 155.52Mb / s.

The frame word generation unit 24 is controlled by the adjustment signal output from the adjustment signal generation unit 22 to generate a frame word, and generates a 12-bit predetermined code 111110100000.

The video signal DS3 speed converting section 25 converts the 44.736 Mb / s video signal outputted from the phase aligning section 21 to 51.84 Mb / s as a decoder and buffer buffer (64 x 4 bits). It consists of. The continuous input signal is written to the buffer buffer at the address indicated by the decoder, and only when the signal is enabled by the control signal output from the adjustment signal generator 22, the signal is read from the buffer buffer at the address indicated by the decoder. do.

The 2.048 Mb / s signal rate converting section 26 is composed of a decoder and a buffer buffer (16 × 4 bits), and 2.048 Mb / s B channel data and 2B + D channel data and a multiplexing unit transmitted from an external user. The 2.048 Mb / s polling signal generated from the polling signal generator (not shown) of (11) is converted into a 51.84 Mb / s signal. The continuous input signal is written to the buffer buffer of the address instructed by the decoder, and only when the signal is enabled by the control signal output from the adjustment signal generator 22, the signal is read from the buffer buffer of the address instructed by the decoder. do.

The 64 Kb / s signal speed converting section 27 converts the 64 Kb / s signal into 51.84 Mb / s and is composed of a simple latch (1 bit) and a counter.

The channel number generation section 28 is controlled by the adjustment signal output from the adjustment signal generation section 22, so that a predetermined 12-bit code (000000000000 (subscriber # 1), 001001001001 (subscriber # 2), like a frame word), 111111111111 (subscriber # 3) is generated, that is, a channel number of 12 bits is generated.

The 64KHz clock generator 29, which is composed of a counter and a decoder, divides a 2.048 MHz clock input from the outside into 32 and generates a 64KHz clock for use in a multiplex / demultiplexer.

The 51.84 Mb / s frame generation / encryption unit 210 is controlled by the adjustment signal output from the adjustment signal generation unit 22 to actually constitute the 51.84 Mb / s frame as shown in FIG. Encrypt the channel data, channel number and polling signal except for the following. At this time, the encryption used a 7-stage scrambler (1 + X (6 power) + X (7 power) polynomial) of the set-reset method as recommended by CCITT.

The parity generating unit 211 is controlled by the adjusting signal output from the adjusting signal generating unit 22, and is a signal encrypted by the frame generating / encrypting unit 210 excluding the frame word among signals composed of 51.84 Mb / s. Parity is checked to generate parity. At this time, even parity is used.

The 155 Mb / s frame multiplexer 212 uses three 51.84 Mb / s clocks having three 120 degree phase differences as control signals for multiplexing using 51.84 MHz clocks having two 120 degree phase differences. Multiplex simple bits into frames.

FIG. 5 is a lower functional block diagram of the 25.92Mb / s demultiplexer of FIG. 3 which demultiplexes the upward 25.92Mb / s signal, which is the path difference between subscribers among the signals of 25.92Mb / s in which the signals from the three subscribers are mixed. After removing the phase shift caused by the desired frameword, the frame is synchronized and the encoded signal is analyzed. The 25.92Mb / s signal is de-neutralized into two 2.048Mb / s signals and two 64Kb / s signals. In addition, parity is checked and an alarm is generated when more than a certain number of errors occur at a predetermined time, compared to parity information loaded on a 25.92 Mb / s frame. In addition, if no frame word is found for a specified time, a signal loss alarm is generated.

One 25.92 Mb / s demultiplexer 12 includes three such lower functional blocks.

As shown in FIG. 5, the demultiplexer of FIG. 3 includes a poly signal generator 31, a bit synchronizer 33, an adjustment signal generator 33, a parity error checker 34, A signal loss error checking unit 35, a synchronization and stabilizing unit 36, a cryptographic analysis unit 37, a 2B + D channel data rate converting unit 39, a channel selection signal rate converting unit 310, A maintenance signal speed converter 311 is provided.

The operation of the demultiplexing of FIG. 3 having the structure as described above will be described in detail as follows.

The polling signal generator 31 generates a 12-bit predetermined code as a part for generating the polling signal, and sends the signal to the 155.52Mb / s multiplexer 11 at a rate of 2.048Mb / s. The polling signal is set to 111101100000 in the subscriber device 1, to 111101100001 in the subscriber device 2, and to 111101100010 in the subscriber device 3.

The bit synchronization unit 32 functions to align the phase of the signal to the internal clock of the demultiplexer by removing phase shift due to the path difference of the 25.92Mb / s signal sent from the subscriber. A series of 25.92 Mb / s generation clocks (generation clock 1 with phase 0 degrees, generation clock 2 with phase 90 degrees and phases as shown in FIG. 8 having 51.84 MHz from the outside as shown in (21) with four phase differences of 90 degrees) Generating clock 3 having 180 degrees and generating clock 4 having phase 270 degrees, using the four generating clocks having a phase difference of 90 degrees, and retiming the input signal as shown in FIG. The relationship between the signals is examined and the most stable signal is retimed back to the clock of the demultiplexer. In addition, when the frame is found in the phase that is set in bit synchronization for stable operation, the phase is maintained continuously and when the frame synchronization is lost, the operation of the bit synchronization is made again. In addition, the bit synchronization unit 32 allows one input bit to have an appropriate phase relationship with the system clock.

The adjustment signal generator 33 generates and supplies various adjustment signals necessary for demultiplexing the data frame as shown in FIG. 2430 counters and decoders are used for this purpose.

The parity error checker 34 checks the parity of the signal from the subscriber except for the frame word as in FIG. 7 and compares it with the parity information carried in the 25.92 Mb / s frame to generate an alarm. Parity check uses even parity, and alarms generate 10e-4 and 10e-6 alarms.

The signal loss error inspection unit 35 generates a signal loss alarm when 4 ms or more elapses while the frame synchronization is lost.

The synchronizing and stabilizing unit 36 finds a frameword, and as a part of checking frame synchronization, if the frameword is found at a predetermined position three or more times in succession, it is determined as a frame synchronization state. If not, alarm is regarded as loss of frame synchronization.

The cipher interpreter 37 uses a two-stage descrambler whose starting point is determined by frame synchronization as a part of analyzing the signal encrypted from the subscriber.

The B-channel data rate converter 38 is composed of a decoder and a buffer buffer (6 x 32 bits), controlled by an adjustment signal output from the adjustment signal generator 33, and used in a signal sequence of 25.92 Mb / s. It extracts only the channel data and converts the speed to 2.048Mb / s. In addition, the B-channel data rate converter 38 stores the signal from the 25.92 Mb / s signal sequence in the buffer buffer only when enabled by the adjustment signal output from the adjustment signal generator 33.

The 2B + D channel data rate converter 39 is composed of a decoder and a buffer buffer (6 x 32 bits), and is controlled by an adjustment signal output from the adjustment signal generator 33 to control a signal sequence of 25.92 Mb / s. It extracts only 2B + D channel data and converts it to 2.048Mb / s. In addition, the 2B + D channel data rate converter 39 stores the signal from the 25.92Mb / s time signal sequence in the buffer buffer only when enabled by the adjustment signal output from the adjustment signal generator 33.

The channel selection signal rate converter 310 is composed of a decoder and a buffer buffer (6x1 bits), controlled by an adjustment signal output from the adjustment signal generator 33, and has a channel in a signal sequence of 25.92Mb / s. Extract only the selected data and convert it to 64 Kb / s. In addition, the channel selection signal rate converter 310 stores the signal from the 25.92 Mb / s signal sequence in the buffer buffer only when enabled by the adjustment signal output from the adjustment signal generator 33.

The maintenance signal rate converting section 311 is composed of a decoder and a buffer buffer (6x1 bits), controlled by an adjustment signal output from the adjustment signal generation section 33, and held in a signal sequence of 25.92 Mb / s. Extracts only the repair data and converts the speed to 64Kb / s. Further, the signal is stored in the buffer buffer from the 25.92 Mb / s signal sequence only when enabled by the adjustment signal output from the maintenance signal speed converter 311 and the adjustment signal generator 33.

FIG. 6 shows a downlink signal composed of 51.84 Mb / s frames, including 12-bit frameword (FAW), 12-bit channel number (CN) classification code, 69-bit DS3 signal, and 32-bit 2.048. It consists of Mb / s signal and 3-bit 64Kb / s signal (maintenance and signaling) (C) and 1-bit parity information, and 51.84 Mb / s after encryption is performed for all parts except frameword (FAW). The three signals are collected to produce a 155.52 Mb / s signal. For reference, in the drawing, X represents a reserved bit (51 bits).

7 shows a frame format in which signals of three subscribers are mixed by passive optical elements and transmitted at a rate of 25.92 Mb / s, and one subscriber signal includes a 10-bit invalid signal (D) and a 12-bit frameword (S1). , S2, S3), 192 bit B channel signals (DUB1, DUB2, DUB3), 192 bit 2B + D channel signals (DUNI1, DUNI2, DUNI3), 6 bit channel selection signals (M11, M12, M13), 6 bits of maintenance signals M21, M22, M23, 6 bits of parity information B1, B2, and B3, and 386 bits of guard time. The guard time is a period for preventing collision between subscriber signals when the transmission delay difference due to the distance difference between the passive optical element and the subscriber device is 15 ms or less. In this section, the signal value is '0'.

8 is an operation timing diagram of the phase alignment unit of FIG. 4 and the bit synchronization unit of FIG.

In the present invention configured as described above, the PON was introduced to allow 3 subscribers to use one channel of 155.52Mb / s to increase availability and to enable low-speed operation with an uplink signal of 25.92Mb / s. In the present invention, one 155.52 Mb / s multiplexer and three 25.92 Mb / s demultiplexers are used.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention not only bundles the multiplexing and demultiplexing apparatuses into one, but also makes it possible to increase the reliability by manufacturing the three-members for one integrated device, thereby making it possible to relatively reduce the size.

Claims (7)

A multiplex / demultiplexer for optical cable television subscriber access of a PON (Passive Optical Network) provided at a line end portion of a distribution network connected to a network end portion of a subscriber network, the line termination portion A multiplexing means arranged to generate a predetermined clock, receive a video signal DS3 and channel data from the outside, generate a frame, and multiplex the generated frame to a plurality of subscribers; And a demultiplexing means arranged at the end of the line and demultiplexing the demultiplexed frame signals transmitted from the plurality of subscribers according to the clocks transmitted from the multiplexing means, and transmitting the demultiplexing means to the upper end. / Demultiplexer for Windows. 2. The apparatus of claim 1, wherein the multiplexing means comprises: phase aligning means for aligning a phase to match a clock used in the multiplexing means by removing a phase shift on a path of an input video signal DS3; Adjustment signal generating means for generating an adjustment signal necessary for constructing a signal frame; First clock generation means controlled by an adjustment signal output from the adjustment signal generator, the first clock generating means for receiving a signal having two phase differences of 120 degrees and generating a series of clocks having three phase differences of 120 degrees; Frame word generation means controlled by an adjustment signal output from said adjustment signal generation means to generate a predetermined predetermined frame word; First speed converting means for changing the speed of the video signal output from said phase aligning means to a predetermined speed; Second speed converting means for converting a speed of a polling signal generated by the multiplexing means and channel data input from the outside; Channel number generation means controlled by a control signal output from said adjustment signal generation means to generate a channel number of a predetermined predetermined bit; Second clock generation means for generating a predetermined clock for use in the multiplexing means and the demultiplexing means by dividing a clock input from the outside; Frame generation / encryption means controlled by the adjustment signal output from the adjustment signal generation means, generating a frame, and encrypting the channel data, the channel number and the polling signal; Parity generating means controlled by the adjustment signal output from the adjustment signal generating means, checking parity of the encrypted signal output from the frame generating / encrypting means to generate parity and outputting the parity to the frame generating / encrypting means; And a multiplexing unit for multiplexing the output signal of the frame generation / encryption means and the frame signal transmitted from other subscribers at the same time. 3. The multiplexing / demultiplexing apparatus for a cable television subscriber connection of a passive optical communication network according to claim 2, wherein the phase aligning means periodically checks the phase of the signal at predetermined intervals. 2. The apparatus of claim 1, wherein the demultiplexing means comprises: polling signal generating means for generating a polling signal according to a clock input from the outside; A bit synchronous means for generating an internal clock of the demultiplexing means according to a clock input from the outside and aligning a phase of the signal to the internal clock by removing phase shift due to a path difference of a signal transmitted from a subscriber; Adjustment signal generating means for generating an adjustment signal for demultiplexing a data frame according to an internal clock output from the bit synchronization means; Synchronizing and stabilizing means for finding a frame word by receiving an output signal of the bit synchronizing means and checking frame synchronism according to an internal clock output from the bit synchronizing means; Cryptographic analysis means connected to said bit synchronization means for interpreting an encrypted signal transmitted from a subscriber in accordance with an internal clock output from said bit synchronization means; Parity error checking means for receiving the output signal of the encryption analysis means and the output signal of the synchronization and stabilization means, and checking parity of signals other than frame words among signals transmitted from subscribers and outputting an alarm signal when an error occurs; Signal loss error checking means for receiving an output signal of the synchronization and stabilization means according to a clock input from the outside and generating a signal loss alarm if a predetermined time elapses after the frame synchronization is lost; And speed conversion means controlled by an adjustment signal output from the adjustment signal generation means, and for converting a speed of a predetermined detection signal detected in a signal input from the encryption analysis means and the synchronization and stabilization means. / Demultiplexing Device for Cable TV Subscriber Access. 5. The cable of a passive optical communication network according to claim 4, wherein the bit synchronization means maintains the phase when the frame is found in the phase synchronized with the bit synchronization and performs the bit synchronization again when the frame synchronization is lost. Multiplex / Demultiplexer for Television Subscriber Access. The frame generated by the frame generation / encryption means includes a 12-bit frameword, a 12-bit channel number, a 32-bit 2.048 Mb / s signal, a 3-bit 64Kb / s signal, and a 1-bit parity. And a 699-bit DS3 signal, comprising 51 bits of reserved bits, for multiplexing / demultiplexing apparatus for cable television subscriber access in a passive optical communication network. 5. A signal transmitted from a subscriber according to claim 4, wherein a signal of three subscribers is mixed, and one subscriber has a 12-bit frameword, a 192-bit B-channel signal, a 192-bit 2B + D signal, and a 6-bit channel selection. Signal, 6-bit maintenance signal, 6-bit parity information, 10-bit invalid signal, and 386-bit guard time, and the total signal frame is 2430 bits, for cable television subscriber access of passive optical network Multiple / Demultiplexer.