KR0154490B1 - Apparatus for converting atm cell in bisdn - Google Patents

Abstract

The present invention relates to an ATM cell conversion apparatus for broadband communication, which matches a data center in the middle of an ATM cell by using a counter. In the present invention, a space for inserting synchronization data is provided using an ATM. By freely forming in the middle of the cell, it is possible to insert a variety of information in the ATM cell, in this way it is possible to form a variety of space in the ATM cell to perform a variety of services.

Description

ATM cell converter for broadband communication

1 is a block diagram showing an embodiment of an AT cell conversion apparatus of broadband communication according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a 64-byte conversion unit according to FIG. 1; FIG.

3 is a block diagram illustrating an embodiment of a cell lead controller according to FIG. 2.

4 is a timing diagram for explaining the operation of the AT cell conversion apparatus of the broadband communication according to the present invention.

* Explanation of symbols for main parts of the drawings

11: 64 byte conversion unit 12: buffer

13: signal synchronization unit 21, 22: first and second count 64

23: ATM cell conversion position determination unit 24: cell lead control unit

25, 35: first and second negative circuit 31: combination

32,34: 1st, 2D flip-flop 33: logical sum circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an ATM cell conversion device for broadband communication, and more particularly, to an ATM cell conversion device for matching to create a conversion data space in the middle of an ATM cell using a counter. It is about.

In general, a broadband transmission system is a transmission system in which the bit rate of a digital signal to be transmitted is hundreds of Mbps or several Gbps, and a high bit rate signal is generated through a frequency division or time division multiplexing process or asynchronous transmission. It is common to make optical transmission by making ATM cell flow by mode (ATM).

Each of these standard ATM cells consists of 53 bytes, and may have additional data for an ATM switch. In this case, the standard ATM cells may have 56 bytes, 57 bytes, and the like.

The serial communication path of an ATM cell requires additional data for high speed synchronization of about 155 Mbps.

In this regard, an object of the present invention is to provide an AT cell conversion apparatus for broadband communication capable of realizing a matching function capable of freely forming a space for inserting additional synchronization data in the middle of an ATM cell. There is a purpose.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object is as follows.

Referring to FIG. 1, FIG. 1 is a block diagram showing an embodiment of an ATM cell conversion apparatus for broadband communication according to the present invention, in which a signal SYNCSSQEMTYB indicating that an ATM cell exists in a buffer 12 is applied. In this case, the ATM serial communication link master clock (MCLK) is applied and used as the clock of the count. The signal (MCS) for initiating the start of one ATM cell every 64 counts is received from the outside. A 64-byte converter 11 for outputting a signal capable of being converted into bytes, and a signal capable of being converted into 64-byte ATM cells from the 64-byte converter 11 by receiving 56 bytes of ATM cells. A buffer 12 outputs a signal indicating that a current ATM cell exists, and a current ATM cell exists from the buffer 12 by inserting it in the middle of a 56-byte authorized ATM cell, converting it into a 64-byte form, and outputting it. Receiving a signal to inform AT And a signal synchronizing section 13 for synchronizing with the M serial communication link master clock MCLK to apply a signal SYNCSSQEMTYB to the 64-byte conversion section 11 to indicate that the ATM cell is in the buffer 12.

FIG. 2 is a block diagram showing an embodiment of the 64-byte converter 11 according to FIG. 1, and receives an ATM serial communication link master clock (MCLK) and uses it as a clock for counting. A first count 64 (21) synchronously cleared by a signal informing the start (MCS), a first negative circuit (25) receiving an ATM serial communication link master clock (MCLK) and performing a negative logic operation to output it; A second count 64 (22) receiving the output of the first negative circuit 25 and latching the output of the first count 64 (21) by the falling edge of the ATM serial communication link master clock (MCLK); ATM cell conversion position determiner that generates and outputs a signal SSVALIDB that can secure a space in an ATM cell by using the count value output from 64 (22) and the rising edge of the ATM serial communication link master clock (MCLK). 23, the output signal SSVALIDB of the ATM cell conversion position determiner 23, and the first count 21; If the ATM cell is received in the buffer 12 by receiving a signal SYNCSSQEMTYB indicating that the ATM cell is in the buffer 12, the buffer is synchronized with the ATM serial communication link master clock MCLK. 12) The cell read control unit 24 generates a read signal SFFRDB and applies it to the buffer 12.

FIG. 3 is a block diagram showing an embodiment of the cell read control unit 24 according to FIG. 2, wherein the count value of the first count 64 (21) and the buffer 12 applied from the signal synchronizer 13 are stored in the ATM. A combination unit 31 for outputting a signal for finding the position of the signal MCS by combining the signal SYNCSSQEMTYB indicating that the cell is present and the output PSSFFRDENB of the 1D flip-flop 32, and the ATM serial communication link master The second negative circuit 35, which performs a negative logic operation on the clock MCLK, and outputs the signal, a signal for finding the position of the signal MCS applied from the combiner 31, and an output of the second negative circuit 35. ATM serial communication of the outputs of the 1D flip-flop 32 and the output of the 1D flip-flop 32 which hold the read signal PSSFFRDENB and apply it to the combining unit 31 so that all 56 bytes of ATM cells can be continuously read out. The 2D flip-flop 34 and the 2D flip-flop 34 which D flip-flop by the link master clock MCLK to output the signal SSFFRDENB Signal (SSVALIDB) capable of securing space for inserting synchronization data two bytes for every 56 bytes of ATM cells of the call (SSFFRDENB) and the ATM serial communication link master clock (MCLK) and the ATM cell conversion positioning unit 23 ) Is included in the logical sum circuit 33 for outputting the buffer 12 read signal SFFRDB to the buffer 12.

The present invention thus achieved will be described in detail with reference to FIG.

4 is a timing diagram for explaining the operation of the ATM cell conversion apparatus for broadband communication according to the present invention.

First, when the signal SYNCSSQEMTYB such as FIG. 4 (H) indicating that there is an ATM cell is applied to the buffer 12, the 64-byte conversion unit 11 receives an ATM such as FIG. 4 (A). ATM cell 56 bytes intermediate intermediate by receiving a signal (MCS) such as FIG. 4 (B) that receives the serial communication master clock (MCLK) and uses it as a clock for counting. Data is inserted into the signal, so that 56 bytes of the ATM cell are converted into 64 bytes of the ATM cell.

Next, the buffer 12 receives a 56-byte ATM cell into 8 bits, and inserts a signal capable of converting the 64-bit ATM cell from the 64-byte converter 11 into 64 bytes in the middle of the 56-byte ATM cell. This function converts the data into byte format and outputs 8 bits. It outputs a signal indicating that an ATM cell exists.

In this case, the butter 12 may be first-in first-out with a first-in first-out (FIFO).

The signal synchronizer 13 receives a signal indicating that an ATM cell exists from the buffer 12 and synchronizes with the ATM serial communication link master clock MCLK as shown in FIG. 11), a signal SYNCSSQEMTYB such as FIG. 4 (H) indicating that the ATM cell is in the buffer 12 is applied.

In addition, as shown in FIG. 2, the first count 64 (21) in the 64-byte converter 11 is a 6-bit counter, and is applied with the ATM serial communication link master clock (MCLK) as shown in FIG. In the same manner as in Fig. 4C, the signal MCS shown in Fig. 4B indicates the start of one ATM cell every 64 counts.

That is, the first count 64 (21) is the same as the fourth diagram (B) informing the start of one ATM cell every count 64 at the rising edge of the ATM serial communication link master clock (MCLK) as shown in FIG. When the signal MCS is low, it is cleared to 0, and is increased by 1 each time the rising edge of the ATM serial communication link master clock MCLK as in the fourth (A) comes, and then as shown in FIG. Increment until the hexadecimal value 3F is reached until the signal MCS low.

At this time, the signal (MCS) as shown in FIG. 4 (B) is a signal supplied from an external device that requires a 64-byte converted ATM cell type, and the ATM serial communication link master clock (MCLK) shown in FIG. 4 (A). It is supplied in the form of low every 64 clocks of

The second count 64 (22) is a circuit latching the output value of the count 64, and the ATM serial communication link master clock (MCLK) as shown in FIG. It is applied through the 6-bit output as shown in Fig. 4 (C) of the first count 64 (21) by the falling edge of the master clock (MCLK) and outputs 6 bits as shown in Fig. 4 (D).

Next, the ATM cell conversion position determiner 23 uses the count value output from the second count 64 22 and the rising edge of the ATM serial communication link master clock MCLK as shown in FIG. 4A. A signal SSVALIDB is generated and output as shown in FIG. 4 (L) so that space can be reserved in the ATM cell, that is, space for inserting synchronization data by 2 bytes for every 56 bytes of ATM cells. .

Subsequently, the cell read control unit 24 receives the output signal SSVALIDB and the output of the first count 21 as shown in FIG. If the ATM cell is present in the buffer 12 by receiving a signal SYNCSSQEMTYB as shown in FIG. 4 (H) indicating that the signal is present in FIG. 4, it is synchronized with the ATM serial communication link master clock (MCLK) as shown in FIG. The buffer 12 read signal SFFRDB as shown in FIG. 4 is generated and applied to the buffer 12.

Then, as shown in FIG. 3, the combination unit 31 in the cell read control unit 24 may have the same count value as that of FIG. 4C of the first count 64 21, and indicate that there is an ATM cell in the buffer 12. Signal (MCS) such as 4 (B) applied from the outside by combining the signal (SYNCSSQEMTYB) such as 4 degrees (H) and the output (PSSFFRDENB) such as 4 (I) of the 1D flip-flop 32 Outputs a signal to find the position of).

In addition, the second negative circuit 35 performs a negative logic operation on the ATM serial communication link master clock MCLK as shown in FIG. 4A, and outputs the first D flip-flop 32 from the combination unit 31. A signal for locating the signal (MCS) as shown in FIG. 4B and an output of the second negative circuit 35 are applied, so that 56 bytes of ATM cells can be continuously read out as shown in FIG. The read signal PSSFFRDENB is held and applied to the combination unit 31.

Next, the 2D flip-flop 34 flips the output of the 1D flip-flop 32 with the ATM serial communication link master clock MCLK as shown in FIG. The same signal SSFFRDENB is output, and the OR circuit 33 is the signal SSFFRDENB of the 2D flip-flop 34 and the ATM serial communication link master clock MCLK as shown in FIG. 4A and the ATM cell conversion position. The signal SSVALIDB such as FIG. 4 (L), which can secure space for inserting synchronization data by 2 bytes for each 56 bytes of the ATM cells of the decision unit 23, is OR-operated. The buffer 12 read signal SFFRDB is output to the buffer 12.

As described above, the present invention has an effect that a variety of information can be inserted into an ATM cell by freely forming a space for inserting synchronization data in the middle of the ATM cell using a counter.

That is, in this manner, various services may be provided by forming various spaces in an ATM cell.

Claims (4)

When a signal SYNCSSQEMTYB indicating that an ATM cell is present in the buffer 12 is applied, the ATM serial communication link master clock MCLK is applied and used as a clock for counting to start the start of one ATM cell every 64 counts. A 64-byte converter 11 for receiving a signal MCS and outputting a signal capable of converting 56 bytes of ATM cells into 64 bytes of ATM cells; A signal capable of receiving 56 bytes of ATM cells and converting them into 64 bytes of ATM cells from the 64-byte conversion unit 11 is inserted in the middle of the 56 bytes of the authorized ATM cells, and converted into a 64-byte form. A buffer 12 for outputting a signal indicating that an ATM cell exists; A signal indicating that an ATM cell is present from the buffer 12 is received and synchronized with an ATM serial communication link master clock MCLK to indicate that the ATM cell is in the buffer 12 in the 64-byte converter 11. An ATM cell converter for wideband communication, comprising a signal synchronizer (13) for applying an informing signal (SYNCSSQEMTYB). 2. The apparatus of claim 1, wherein the buffer (12) comprises a FIFO. 2. The 64-byte converter 11 receives an ATM serial communication link master clock (MCLK) and uses it as a clock for counting to provide a signal (MCS) indicating the start of one ATM cell every 64 counts. A first count 64 (21) synchronously cleared by the first count 64; A first negative circuit (25) for receiving an ATM serial communication link master clock (MCLK) and outputting a negative logic operation; A second count 64 (22) receiving the output of the first negative circuit 25 and latching the output of the first count 64 (21) by the falling edge of the ATM serial communication link master clock (MCLK); An ATM cell that generates and outputs a signal SSVALIDB that can secure a space in an ATM cell by using the count value output from the second count 64 22 and the rising edge of the ATM serial communication link master clock MCLK. A conversion position determiner 23; The output signal SSVALIDB of the ATM cell conversion position determiner 23 and the output of the first count 21 are applied, and the signal SYNCSSQEMTYB indicating that the ATM cell is in the buffer 12 is received. If there is an ATM cell in the buffer 12, the cell read control unit 24 generates the buffer 12 read signal SFFRDB and applies it to the buffer 12 in synchronization with the ATM serial communication link master clock MCLK. ATM cell conversion device for broadband communication comprising a. 4. The cell read control unit 24 according to claim 3, wherein the cell read control unit 24 indicates a count value of the first count 64 (21) and a signal (SYNCSSQEMTYB) indicating that there is an ATM cell in the buffer 12 applied from the signal synchronizer 13. And a combination unit 31 for combining the output PSSFFRDENB of the first D flip-flop 32 to output a signal for locating the signal MCS; A second negative circuit 35 for performing a negative logic operation on the ATM serial communication link master clock MCLK and outputting the negative logic operation; Read signal PSSFFRDENB so that 56 bytes of ATM cells can be read out continuously by receiving the signal for finding the position of the signal MCS applied from the combination unit 31 and the output of the second negative circuit 35. 1D flip-flop (32) for holding and applying to said combination part (31); A second D flip-flop (34) for outputting the signal SSFFRDENB by D flipping the output of the first D flip-flop (32) by the ATM serial communication link master clock (MCLK); For inserting synchronization data by 2 bytes every 56 bytes of ATM cells of the 2D flip-flop 34 and the ATM serial communication link master clock MCLK and the ATM cell conversion position determiner 23. ATM cell conversion for wideband communication comprising a logical sum circuit 33 for ORing a signal SSVALIDB capable of securing a space and outputting the buffer 12 read signal SFFRDB to the buffer 12 Device.