KR0152227B1 - Signal recovering apparatus - Google Patents

Abstract

The present invention is to provide a signal recovery apparatus that can be implemented using all of the digital logic, does not require a separate analog device or oscillator, and does not need to transmit a separate clock because the clock of the receiver is used. have.

In order to achieve the above object, the present invention provides a four-phase clock generator 11 that generates four phase clocks by inputting a clock twice as fast as a signal speed, and reproduces the input signal as four reproduction signals. The input signal reproducing unit 12 for outputting, the four signals that are reproduced are inputted, and an exclusive logical sum processing signal is output, the signal comparing unit 13 for outputting the final comparison signal of the reproduced signal, and the final comparison signal is a control signal. An output signal selector 14 for selecting and outputting one of the reproduced signals, and a phase fixing unit 15 for sending a phase locked signal to the signal comparator 13 are provided.

Description

Signal recovery device

1 is an overall configuration diagram of a signal recovery circuit.

2 is a detailed configuration diagram of the four-phase clock generator.

3 is a detailed configuration diagram of an input signal reproducing unit.

4 is a detailed configuration diagram of the signal comparison unit.

5 is a detailed configuration diagram of the output signal phase fixing unit.

6 is a detailed configuration diagram of the output signal selection unit.

7 is a timing diagram showing an input / output signal relationship of a signal recovery circuit.

The present invention relates to a signal recovery apparatus that facilitates recovery of a received signal in a synchronous network, and absorbs jitter contained in the received signal to enable recovery of a correct signal.

Conventionally, in order to recover a received signal, a clock is extracted from a received signal, or a signal and a clock are simultaneously transmitted to recover a received signal using the same. To this end, a separate analog device, an oscillator, or a separate clock transmission path is required.

Therefore, the present invention devised to solve the problems of the prior art, all can be implemented using digital logic, and does not require a separate analog device or oscillator, and uses a clock of the receiving end to transmit a separate clock The purpose was to provide a signal recovery circuit that does not need to be done.

In order to achieve the above object, the present invention, a four-phase clock generator for generating a clock with four phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, by inputting a double clock twice as fast as a signal speed, An input signal reproducing unit for receiving the input signal as a received signal and reproducing the input signal using the four clocks received from the four-phase clock generating unit and outputting the four reproducing signals as four reproducing signals; reproduction from the input signal reproducing unit A signal comparator which receives the four signals which have been inputted and outputs a signal obtained by performing an exclusive OR on each other, and which receives a phase-fixed signal and outputs a final comparison signal of the reproduced signal by its control; Output signal selection unit for selecting and outputting one of the signals reproduced by the input signal reproducing unit according to the number of 16 cases by using the control signal, and from the signal comparing unit When the exclusive ORed signal is input and all of the values are '0' or '1', the logic specific logic value signal is sent to the signal comparator as a phase lock signal to fix the value of the signal comparator output to the previous value. An output signal phase fixing unit.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall configuration diagram of a signal recovery circuit. Referring to the drawings, the operation of each component of the present invention will be described below.

The four-phase clock generator 11 inputs a clock twice as fast as the signal speed to generate clocks having four phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. The input signal reproducing unit 12 receives the input signal, which is a received signal, and uses the four clocks received from the four-phase clock generating unit 11, namely, clock 1, clock 2, clock 3, and clock 4 to obtain the input signal. The input signal is reproduced and then output as signals 1, 2, 3 and 4. The signal comparator 13 receives signals 1, 2, 3, and 4 from the input signal reproducing unit 12, and logically exclusives-ORs the signals to compare them with each other, XOR1, XOR2, and XOR3. And XOR4. In addition, the phase fixing signal is received from the output signal phase fixing unit 15 to be described later, and under the control thereof, the final comparison result signals of comparison 1, comparison 2, comparison 3 and comparison 4 are output.

The output signal selector 14 receives the comparison 1, the comparison 2, the comparison 3, and the comparison 4 from the signal comparison unit 13 according to the output signal selection logic table (Table 1) below. Select one of the signal 1, the signal 2, the signal 3, and the signal 4 reproduced from the output.

[Table 1] shows the output signal selection logic table. This is the logic used in the output selection signal section 14, and the comparison signal 1, 2, 3 and 4 are used as control signals so that the optimum output signal is selected according to the number of 16 cases. When the values of the comparison 2, the comparison 3 and the comparison 4 are binary logic '0000', the signal 3 is outputted to set the initial value, but after that, the utility is lost by the phase lock signal. In the case of the binary logic '1111' of the values of the comparison 2, the comparison 3, and the comparison 4, the input signal is considered to be useless and the output signal is not sent.

On the other hand, the output signal phase fixing unit 15 receives XOR1, XOR2 XOR3 and XOR4 from the signal comparing unit 13 and compares the logic 'Low' signal when the binary logics '0000' and '1111' are used. It is sent to the unit 13 to fix the values of the comparison 1, comparison 2, comparison 3 and comparison 4 to its previous value.

2 shows a detailed configuration of the four-phase clock generator (11 in FIG. 1).

The dividing unit 21 inputs a double clock and divides it into two to make a clock having a speed of 1/2, and outputs it to the input 1 of the decoder unit 22 to be described later and the D-flip flop 23 to be described later. do. The decoder 22 receives the clock as the input 1 from the dividing unit 21, receives the clock from the D-flip flop 23 as the input 2, and decodes it as a control signal so that the phases are 0 degrees and 90 degrees, respectively. We make clock 1, clock 2, clock 3 and clock 4 which are 180 degrees and 270 degrees.

The D-flip flop 23 receives a double clock divided by two into the dividing unit 21, and inverts a double clock, which is an input of the two dividing circuit 21, by 180 degrees, to be input to a clock input terminal. By using this, the output of the two-dividing circuit 21 is phase shifted by 90 degrees and output to the input 2 of the decoder 22.

3 shows the detailed configuration of the input signal reproducing unit (12 in FIG. 1).

The D-flip flops 31, 33, 35, and 37 retime the input signal to the respective clocks by using the clock 1, clock 2, clock 3, and clock 4 received from the four-phase clock generator 11.

The other D-flip flops 32, 34, 36, and 38 receive signals re-timed from the D-flip flops 31, 33, 35, and 37, respectively, and retime them back to clock 1 to output signals 1, Outputs signals 2, 3 and 4.

4 shows the detailed configuration of the signal comparator (13 in FIG. 1).

The exclusive OR gate (hereinafter referred to as XOR) 41 is signal 1 and signal 2, XOR 42 is signal 2 and signal 3, XOR 43 is signal 3 and signal 4, and XOR 44 is signal 4 and signal. 1 is taken as an input and is output as XOR1, XOR2, XOR3, and XOR4, which are exclusive ORs, respectively. The AND gate 49 (hereinafter referred to as AND) 49 outputs the result of ANDing the clock 3 and the phase locked signal to the D-flip flops 42, 44, 46 and 48.

The D-flip flops 42, 44, 46 and 48 convert the XOR1, XOR2, XOR3 and XOR4 signals into the final comparison result signals under the control of the output signal of AND 49 as Comparative 1, 2, 3 and 4 respectively. Output

5 shows the output signal phase correction (15 in FIG. 1).

The OR gate 51 (hereinafter referred to as OR) 51 performs an OR operation on the XOR1, XOR2, XOR3, and XOR4 signals from the signal comparator 13, and outputs the same. ) Multiplies XOR1, XOR2, XOR3, and XOR4, then takes the inverse and outputs it. The AND 53 logically multiplies the outputs of the OR 51 and the NAND 52 and outputs the phase-fixed signal.

6 shows a detailed configuration of the output signal selection section 14 of FIG.

The multiplex 61 receives the signal 1, the signal 2, the signal 3 and the signal 4 from the input signal reproducing unit 12 as inputs. Using 4 as a control signal, a signal is selected and output as shown in the output signal selection logic table in [Table 1].

7 is a timing diagram showing an input / output signal relationship of a signal recovery circuit according to the present invention.

Reference numeral 71 denotes an input signal entering the input signal reproducing section 12, 72 a double clock entering the four-phase clock generating section 11, 73, 74, 75, and 76 input signal reproducing section 12. Shows clock 1, clock 2, clock 3, and clock 4 entering Reference numerals 77, 78, 79 and 710 show signals 1, 2, 3 and 4 outputted from the input signal reproducing unit 120. Reference numerals 711, 712, 713, and 714 show comparison 1, comparison 2, comparison 3, and comparison 4, which are outputs of the signal comparison unit 13. FIG. Denoted at 715 is a phase fixing signal from the output signal phase correction section 15, and 716 is a final output signal from the output signal selector 14.

Therefore, in the present invention configured and operated as described above, the entire circuit can be implemented using digital logic, and since a separate analog device or an oscillator is not used and a clock of the receiving end is used, a separate clock needs to be transmitted. There is no effect, and jitter of the received signal can be absorbed.

Claims (7)

A four-phase clock generator 11 that generates two clocks each having four phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees by inputting a double clock which is twice as fast as the signal speed, and receives an input signal that is a received signal. An input signal reproducing unit 12 and the input signal reproducing unit 12 which reproduces the input signal using four clocks received from the four-phase clock generating unit 11 and then outputs the four reproducing signals as four reproducing signals. A signal comparator 13 which receives four reproduced signals from and outputs an exclusive OR-processed signal from each other, and receives a phase-fixed signal and outputs a final comparison signal of the reproduced signal by its control; An output signal selector 14 for selecting and outputting one of the signals reproduced by the input signal reproducing unit 12 according to the number of 16 cases using the final comparison signal as the control signal from the signal comparing unit 13, and Exclusive logic from the signal comparator 13 When the processed signal is input and all of the values are '0' or '1', the logic-specific logic value signal is sent to the signal comparator 13 as a phase locked signal to immediately transfer the value of the signal comparator 13 output. And an output signal phase fixing unit (15) for fixing at a value of. According to claim 1, wherein the four-phase clock generation unit 11, the two-division divider 21 for generating a clock having a speed of 1/2 by dividing the two-clock input as a double clock 21, the two minutes A D-flip flop 23 which receives the output of the main part 21, phase-inverts the double clock by 180 degrees, and receives the output of the double divider 21 by 90 degrees out of phase; And receiving an output from the dividing unit 21 as a first input, receiving an output from the D-flip-flop 23 as a second input and decoding it as a control signal, respectively, so that the phase is 0 degrees, 90 degrees, And a decoder unit (22) for outputting a four-phase clock of 180 degrees and 270 degrees. The input signal reproducing unit 12 of claim 2, wherein the input signal reproducing unit 12 re-times the input signal using the four-phase clock received from the four-phase clock generating unit 11. 33, 35, 37, and a second signal receiving the retimed signals from the D-flip flops 31, 33, 35, 37, respectively, and retiming them to a clock having a phase of 0 degrees and outputting them as reproduced signals. And a D-flip-flop (32, 34, 36, 38). 4. The exclusive logical sum element unit (41, 42, 43, 44) according to claim 3, wherein the signal comparing unit (13) outputs the exclusive OR of the output signals of the input signal reproducing unit (12). Logical AND (AND) 49 for outputting the result of the AND multiplication by inputting the clock and the phase locked signal of the phase 180 of the output of the phase clock generation unit 11, and the output signal of the exclusive OR sum unit And a third D-flip-flop portion (42, 44, 46, 48) for latching and outputting under the control of an output signal of the element (49). 5. The logic circuit according to claim 4, wherein the output signal phase fixing unit (15) comprises: a logic sum element (51) for performing a logic sum of the output signals of the exclusive logic sum element parts (41, 42, 43, 44), and the exclusive logic sum element part. Negative logical element 52 for performing an AND operation on the output signals of (41, 42, 43, 44), and reciprocating and outputting the AND, and ORing the outputs of the logical sum element 51 and the logical AND element 52 by phase And a logical product element (53) for outputting a fixed signal. 6. The output signal selector 14 according to claim 5, wherein the output signal selector 14 receives the signal reproduced from the input signal reproducer 12 as a control signal and uses the comparison signal received from the signal comparator 13 as a control signal. And a multiplexer (61) for selecting and outputting any one of them. 7. The signal recovery apparatus according to claim 6, wherein the multiplexer (61) is configured to select an optimum output signal according to the number of 16 cases by using the output signal of the signal comparator (13) as a control signal.