KR0152226B1 - System clock generator - Google Patents

Abstract

The present invention relates to a system clock generator, which selects a reference timing of one of a plurality of input sources, generates a system clock and system timing required by a broadband circuit distribution system, and generates an STM-N signal processor. Reference timing selecting means (11) for receiving a plurality of input synchronization sources and selecting a reference timing according to a selection signal in order to provide a system clock generator for supplying to a switch unit and generating an external clock and supplying it to a domestic synchronization network clock generator. ); Digital processing phase locked looping means (12) for receiving a reference timing from the reference timing selecting means (11) to generate and output a synchronized clock; Timing generating means (13) for receiving a count clock from said digital processing phase locked looping means (12) and dividing it to generate timing; External clock generation means (14) for receiving a reception timing from the reference timing selection means (11), receiving a timing from the timing generation means (13), and selecting an external clock according to the selection signal and outputting it externally; A clock for generating a plurality of system clocks, system timings, and system distribution timings by receiving a synchronization clock from the digital processing phase-locked looping means 12 and a timing from the timing generating means 13. The driving means 15 can be used to synchronize the entire system, improve the processing speed, reduce the load on the microprocessor so that the phase data can not be missed, and the performance degradation of the synchronous network clock can be minimized. have.

Description

System clock generator

1 is an overall configuration diagram of a system clock generator according to the present invention.

2 is a detailed configuration diagram of a reference timing selector according to the present invention.

3 is a detailed block diagram of a digital processing phase locked loop according to the present invention.

4 is a detailed block diagram of a digital phase comparator according to the present invention.

5 is a timing diagram of FIG.

6 is a detailed configuration diagram of an external clock generator according to the present invention.

7 is a detailed configuration diagram of a timing generator according to the present invention.

8 is a timing diagram of system timing.

* Explanation of symbols for main parts of the drawings

11: reference timing selector 12: digital processing phase locked loop

13 timing generator 14 external clock generator

15: Clock Driver 21, 22, 61: Multiplexer

31 Digital Phase Comparator 32 Microprocessor

33: digital-to-analog converter 34: voltage controlled oscillator

35,36,47,71: divider 41: upward edge detector

42: counter 43, 44, 45: latch

46: coefficient detector 62: phase locked loop (PLL)

63: framer / line connection 72: duty adjustment circuit

The present invention generates a system clock (77.760 MHz) and a system timing (8 KHz) required for a wideband circuit distribution system by using a reference timing selected from a variety of synchronization source candidates inputted and supplied to an external synchronization network node device. A system clock generator for generating an external clock.

Synchronous Digital Hierarchy (SDH) technology accepts synchronous shear mode level N (STM-N: Synchronous Transport Module level-N) signals and switches circuits in AU / TU (Administration Unit / Tributary Unit) signal units The Broadband Digital Cross-Conect System (BDCS), which has the function of transmitting STM-N signals, can easily configure the inter-station transmission network according to mutual distribution / branch combining function. In the event of a failure, reconfiguring the transmission path not only provides fast transmission link recovery but also can perform a test access to any signal.

In order to realize the functions of the broadband line distribution system, the 77.760HMz clock used in the STM-N signal processing unit and the switch unit and the 8KHz timing, which is the reference point of the frame start position, must be synchronized with the reference timing. In order to minimize the effect of the domestic synchronous network clock due to pointer adjustment jitter, the reception timing extracted from the STM-N signal is minimized. An external clock can be generated by using and provided to a domestic synchronous network clock generator (DOTS: Digital Office Timing Supply).

Therefore, the present invention selects a reference timing of one of a plurality of input synchronization sources, generates a system clock and system timing required by the broadband circuit distribution system, and supplies it to the STM-N signal processing unit and the switch unit, An object of the present invention is to provide a system clock generator for generating an external clock and supplying the domestic synchronous network clock generator.

In order to achieve the above object, the present invention includes: reference timing selecting means for receiving a plurality of input synchronization sources input from the outside and selecting reference timing according to a selection signal input from an external central control means; Digital processing phase-locked looping means connected to said central control means for receiving a reference timing from said reference timing selecting means and generating and outputting a synchronized clock; Timing generation means for generating a timing by dividing a coefficient clock from the digital processing phase locked looping means; External clock generation means for receiving a reception timing from the reference timing selection means, receiving a timing from the timing generation means, and selecting an external clock according to a selection signal of the central control means to output the external signal; And a clock driving means for generating a plurality of system clocks, system timings, and system distribution timings by receiving a synchronous clock from the digital processing phase locked looping means and a timing from the timing generating means. It features.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

1 is an overall configuration diagram of a system clock generator according to the present invention, where 11 is a reference timing selector, 12 is a digital processing phase locked loop, 13 is an external clock generator, 14 is a timing generator, and 15 is a clock driver. Indicates.

As shown in FIG. 1, the system clock generator according to the present invention interfaces with an external central processing unit (CPU) and has a reference terminal connected to input sources such as external timing, reception timing, and internal timing, respectively. A digital processing phase lock loop 12 connected to a timing selector 11 and an external central processing unit (CPU) to receive a reference timing output from the reference timing selector 11 to generate and output a synchronized clock. The timing generator 13 receives the count clock from the digital processing phase lock loop 12 and divides the signal clock into 4860 and generates two 8KHz timings having a duty required by the system. 4 reception timings connected to a processing unit (CPU) and output from the reference timing selector 11 and 8KHz timings output from the timing generation unit 13 are received. An external clock generator 14 for generating a sub-clock and outputting the external clock to an external synchronous network clock generator, a synchronous clock output from the digital processing phase synchronization loop 12, and two outputs from the timing generator 13. And a clock driver 15 for receiving a plurality of system clocks and generating system timings and system distribution timings.

The detailed operation thereof is as follows.

The reference timing selector 11 uses one of the input synchronization sources such as two external timings, twelve reception timings, and internal timings by using a selection signal input from an external central control unit (CPU) not shown in the figure. Select the timing. Here, among the 12 reception timings (reception timing 1 to reception timing 12), the actual input synchronization candidate is used as 4 reception timings (reception timing A to reception timing D), and the selection method thereof is the third phase of the domestic synchronization network. Select a timing with a higher clock quality.

The method of selecting the reference timing depends on the priority of the synchronous clock quality of the synchronous status message (SSM) provided in the STM-N signal (S1 byte) and the priority according to the reliability of the external timing, the reception timing, and the internal timing. If a failure occurs in the reference timing, a synchronization source switching is performed to select the next higher synchronization source as the reference timing according to the above rank.

The digital processing phase lock loop 12 generates a synchronous clock of 77.760 MHz using the reference timing selected in the manner described above, and supplies it to the external STM-N signal processor and switch unit not shown in the drawing through the clock driver 15. The external central control unit (CPU) is connected to the internal microprocessor 32 to report each state of the digital processing phase lock loop 12.

The timing generator 13 divides the count clock of 38.880 MHz output from the digital processing phase lock loop 12 into 4860 times (38.880 MHz / 8 KHz) and supplies the external clock generator 14 to two duty cycles. An 8KHz timing is generated and supplied to the STM-N signal processing unit and the switch unit, which are not shown in the drawing, as part of the broadband circuit distribution system through the clock driver 15.

The external clock generator 14 is designed to minimize the effect of deterioration of the domestic synchronous network clock characteristics due to pointer adjustment jitter. The external clock generator 14 receives four reception timings (reception timing A to reception timing D) from the reference timing selector 11. ) And the 8K (1) from the 8KHz timing generator 13 to select one of them by a selection signal of an external central controller (CPU), and then generate a 2.048Mbps external clock signal synchronized with the selection timing. Provided to the synchronous network clock generation device (DOTS).

The clock driver 15 is a 77.760 MHz synchronous clock output from the digital processing phase lock loop 12 and two 8 KHz timings output from the 8 KHz timing generator 13, 8K (1) and 8K (2). The system generates 9 system clocks and 8 system timings, and supplies one system clock and system distribution timing to the STM-N signal processor, which is not shown in the drawing. Supply the timing. The clock driver 15 used here uses the MC10E111 from Motorola, which is a low skew clock driver.

2 is a detailed configuration diagram of the reference timing selector according to the present invention, and includes four 12: 1 multiplexers 21 and a 7: 1 multiplexer 22.

Twelve reception timings (reception timing 1 to reception timing 12) are input to each 12: 1 multiplexer, and four reception timings (reception timing A to reception timing D) are selected by an external central controller (CPU) interface. Output to the external clock generator 14, the output signal is used as an input signal of the 7: 1 multiplexer (22). The 7: 1 multiplexer 22 receives a total of seven signals such as external timing 1, external timing 2, receiving timing A to receiving timing D, and internal timing, and selects one of them by the central controller (CPU) interface as a reference timing. use.

3 is a detailed configuration diagram of a digital processing phase locked loop according to the present invention, in which 31 is a digital phase comparator, 32 is a microprocessor, 33 is a digital / analog converter, 34 is a voltage controlled oscillator, 35 is a divider, and 36 is Each of the four dividers is shown.

The digital phase comparator 31 performs a function of counting the reference timing with a count clock to calculate 5-bit phase difference data for every 125usec, and the phase difference data are sent to the microprocessor 32.

The microprocessor 32 interfaces with an external central control unit, calculates a 16-bit digital / analog converter control value by accumulating and averaging data input from the digital phase comparator 31 at a 512 msec period, and then performs a digital / analog converter 33. ), The calculation function is performed by a program, and implemented using a Motorola MC68000 chip.

The digital-to-analog converter 33 converts the 16-bit control value input from the microprocessor 32 into an analog voltage value and outputs it to the voltage controlled oscillator 34. The analog / analog converter 33 implements the AD569.

The voltage controlled oscillator 34 converts the analog voltage value output from the digital / analog converter 33 into a frequency, generates a 155.520 MHz clock, and outputs the SNP3030A manufactured by NDK of Japan. Implemented.

The divider 35 divides the 155.520 MHz clock inputted from the voltage controlled oscillator 34 into two and generates a synchronous clock of 77.760 MHz and supplies it to the input of the clock driver 15.

The four divider 36 divides the 155.520 MHz clock input from the voltage controlled oscillator 34 into four and generates a count clock of 38.880 MHz to supply the digital phase comparator 31 and the timing generator 13. .

The divider 35 and the divider 36 are implemented using a counter.

4 is a detailed configuration diagram of a digital phase comparator according to the present invention, wherein 41 is an upward edge detector, 42 is a hexadecimal counter, 43 and 44 are 5-bit latches, 45 is a 10-bit latch, 46 is 304 detectors, and 47 is Each dividing cycle is shown.

The up edge detector 41 detects and then detects only the rising edge of the reference timing input from the reference timing selector 11 using the 38.880 MHz counting clock inputted from the four divider 36. Generates a period-width signal (Active 1) of the count clock at its location, which consists of a D flip-flop and a logic circuit.

The phase difference data is generated by the hexadecimal counter 42 and the 304 count detector 46. If the phase difference or frequency difference does not occur when counting the section from the current up edge to the next up edge of the 8 KHz reference timing with the 38.88 MHz counting clock, the count value is 4860 (= 16x303 + 12). Is greater than or less than 4860.

Therefore, using the above method, the hexadecimal counter 42 loads a value of 4 by the up edge signal output from the up edge detector 41, and by the count clock input from the four-minute period 36. Four phase difference data such as QA, QB, QC and QD are generated and output to the 5-bit latch 43 by counting up to the next up edge.

The 304 count detector 46 performs the counting of the up edge signal input from the up edge detector 41 by the QD clock of the hexadecimal counter 42. When the 304 counting point is reached, one cycle of the QD clock is reached. QE, a signal having a pulse width, is output to the 5-bit latch 43 and reset by the next up edge signal.

The 5-bit latches 43 and 44 latch five phase difference data generated by the hexadecimal counter 42 and the 304 count detector 46 in two stages by an up edge signal having a period of 8 KHz.

The divider 47 divides the up edge signal inputted from the up edge detector 41 into 4 KHz and outputs the phase data latch signal to the 10-bit latch 45.

The 10-bit latch 45 simultaneously latches the respective phase difference data input from the two 5-bit latches 43 and 44 by the phase data latch signal input from the divider 47. Will be sent). Here, the phase difference data generation rate is 8KHz, but the actual read rate of the microprocessor 32 is 4KHz in order to prevent the loss of data due to the load of the microprocessor 32. The hexadecimal counter 42 and the divider 47 use a general counter, and the 5-bit latches 43 and 44 and the 10-bit latch 45 are also implemented using a general latch. 46 consists of a general counter and a logic circuit.

5 shows an up edge signal, a phase data, and a phase data latch signal of a digital phase comparator according to the present invention.

6 is a detailed configuration diagram of the external clock generator 13 according to the present invention, in which 61 is a 5: 1 multiplexer, 62 is a phase lock loop (PLL), and 63 is a framer / line connection unit 53. Represent each.

The 5: 1 multiplexer 61 inputs four reception timings from the 12: 1 multiplexer 21 and 8K (3) from the 8KHz timing generator and selects one of them by an external central control interface. .

The phase locked loop 62 performs a function of generating a synchronized 2.048 MHz clock using the selected 8 KHz signal as a reference input.

The framer / line connection unit 63 generates and outputs a signal of 2.048 Mbps (E1 signal of general European hierarchy) using the 2.048 MHz clock, and the insertion of the synchronization status message is performed by the CPU interface. The framer / line connection part 63 was implemented using LXT305A of US Level One and MT9079 of Mitel.

7 is a detailed configuration diagram of the timing generator according to the present invention, where 71 denotes 4860 dividers and 72 denotes a duty adjustment circuit.

The 4860 divider 71 divides the count clock of 38.880 MHz coming from the four divider 36 of the digital processing phase locked loop 12 into 4860 times to produce 8K (3) which is one cycle signal of the count clock. It is then supplied to the external clock generator 14.

The duty adjustment circuit 72 uses an 8K (3) and a counter output signal (Q signal) output from the 4860 frequency divider 71 and an 8K (1) signal and 38.880MHz corresponding to 46 cycles of a 38.880 MHz count clock. An 8K (2) signal corresponding to 59 cycles of the count clock is generated and supplied to the clock driver 15 to generate system timing and system distribution timing. The 4860 divider 71 is composed of a general counter, a D flip-flop, and a logic circuit, and the duty adjustment circuit 72 is composed of a D flip-flop and a logic circuit.

8 shows waveform diagrams of 8K1 (1), 8K (2), and 8K (3) output from the timing generator.

The present invention constructed and operated as described above generates a 77.760 MHz system clock and an 8 KHz system timing synchronized with the reference timing input to the system clock generator of the BDCS and does not display the system timing. By supplying to the STM-N signal processor and switch unit, the entire system can be synchronized. In the digital processing phase lock loop, unlike the 8-bit microprocessor used in the existing system, the 16-bit microprocessor is used to increase the processing speed of the software. Although the phase data generation rate is 8KHz in the digital phase comparator, the use of 5-bit and 10-bit latches reduces the read rate of the microprocessor to 4KHz, reducing the load on the microprocessor so that phase data is not missed. Existing Network Dividers Unlike stem newly added as an external clock generating section there is an effect that it is possible to minimize the performance degradation of the synchronous network clock that may occur due to the pointer adjustment jitter.

Claims (8)

Reference timing selecting means (11) for receiving a plurality of input synchronization sources input from the outside and selecting a reference timing according to a selection signal input from an external central control means; Digital processing phase-locked looping means (12), connected to said central control means, for receiving a reference timing from said reference timing selecting means (11) to generate and output a synchronized clock; Timing generating means (13) for receiving a count clock from said digital processing phase locked looping means (12) and dividing it to generate timing; An external clock generation means for receiving a reception timing from the reference timing selecting means 11 and receiving a timing from the timing generating means 13 and selecting an external clock according to a selection signal of the central control means and outputting it externally; 14); A clock for generating a plurality of system clocks, system timings, and system distribution timings by receiving a synchronization clock from the digital processing phase-locked looping means 12 and a timing from the timing generating means 13. System clock generator, characterized in that it comprises a driving means (15). The external clock generating means (14) according to claim 1, wherein the reference timing selecting means (11) receives a plurality of receiving timings from the outside and selects a plurality of receiving timings according to a selection signal of the central control means. A plurality of first multiplexing means (21) for outputting; And receiving the plurality of reception timings from the plurality of first multiplexing means 21, receiving an external timing and an internal timing from the outside, and selecting the received timings according to a selection signal of the central control means. And a second multiplexing means (22) for outputting to the phase locked looping means (12). The digital phase comparison means (31) according to claim 1, wherein said digital processing phase locked looping means (12) calculates phase difference data by counting a reference timing input from said reference timing selecting means (11) as a coefficient clock. ; A microprocessor (32) which is interfaced with the central control means and calculates a digital / analog converter control value by accumulating averaged phase difference data input from the digital phase comparing means (31); Digital / analog converting means (33) for converting a control value input from the microprocessor (32) into an analog voltage value and outputting the analog value; Voltage controlled oscillation means (34) for generating a clock by converting an analog voltage value input from said digital / analog conversion means (33) into a frequency; First dividing means (35) for dividing a clock input from the voltage controlled oscillating means (34) to generate a synchronous clock and output the same to the clock driving means (15); And second dividing means 36 for dividing a clock input from the voltage controlled oscillation means 34 to generate a count clock and outputting the counted clock to the digital phase comparing means 31 and the timing generating means 13. System clock generator, characterized in that. 4. The digital phase comparison means (31) according to claim 3, wherein the digital phase comparison means (31) is an upward edge of the reference timing input from the reference timing selection means (11) by using a count clock input from the second division means (36). An upward edge detecting means 41 for detecting a rising edge and then generating a signal (active 1) of one cycle width of the counting clock at the detected position; Counter means for receiving the up edge signal output from the up edge detection means 41 and counting up to the next up edge by a counter clock inputted from the dividing means 36 to generate and output phase difference data. (42); Coefficient detecting means for counting an up edge signal input from the upside edge detecting means 41 by the clock of the counting means 42 and outputting phase difference data having one period pulse width of the clock of the counting means 41; 46; First latch means (43, 44) for latching phase difference data generated by said counting means (42) and said counting detecting means (46) by an upward edge signal output from said upward edge detecting means (41); Third dividing means (47) for dividing an up edge signal input from said up edge detection means (41) to output a phase data latch signal; And simultaneously latching the respective phase difference data input from the first latching means 43 and 44 by the phase data latching signal input from the third distributing means 47 to output to the microprocessor 32. And a second latch means (45). 5. The system clock generator as set forth in claim 4, wherein said first latching means (43, 44) is comprised of two 5-bit latches (43, 44). 5. The system clock generator as claimed in claim 4, wherein the second latch means (45) is configured such that the speed at which the microprocessor (32) reads data is lower than the phase difference data generation rate. According to claim 1, wherein the external clock generating means 14 receives the plurality of reception timings input from the reference timing generating means 11 and the timings input from the timing generating means (13) to the center Multiplexing means (61) for selecting in accordance with the selection signal of the control means; Phase-locked looping means (62) for generating a clock synchronized with the signal selected by the multiplexing means (61) as a reference input; And framer / line connecting means (63) for generating an external clock and outputting it externally by using the output of said phase locked looping means (62). 2. The apparatus according to claim 1, wherein the timing generating means (13) divides a count clock input from the digital processing phase locked looping means (12) and supplies timing to the external clock generating means (14). 71); And a duty adjustment means (72) for generating two timings by using the timing output from the dividing means (71) and the counter output signal to the clock driving means (15). .