KR0150671B1 - Manufacturing method of semiconductor having a different isolation structure between peripheral circuit area and cell area - Google Patents

Abstract

omission

Description

Method of fabricating semiconductor device having device isolation structure in which peripheral circuit area and cell area are different

1A through 1E are diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present invention.

2a and 2b is a manufacturing process diagram of a semiconductor device according to another embodiment of the present invention.

3a to 3c is a semiconductor device manufacturing process according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

31 silicon substrate 32 oxide film for pad

33,35,37: photosensitive film pattern 34: investment oxide film

36: P-well 38: device isolation oxide film

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a device isolation structure in which a peripheral circuit region and a cell region are different from each other.

In the manufacture of semiconductor devices, device isolation films are commonly used to insulate between cells or to insulate between wells. Conventionally, device isolation films are formed by forming an oxide film therein by a thermal oxidation process that is a national part of a substrate for insulation purposes. The method of forming the is mainly used. However, as the device becomes increasingly integrated, a latch-up problem is seriously raised. In the related art, the isolation oxide layer is deeply formed by performing a thermal oxidation process in which a substrate is partially etched to form a trench. Although a method of forming is used, there is a problem in that the reliability and yield of the device are reduced by increasing the generation factor of impurities and defects due to the complicated process. For example, in a local oxidation process using a trench, etching is performed to a depth of 1 to 2 μm of a substrate by plasma etching to form a trench, and an oxide film is formed thereon to separate the N-well and the P-well to prevent latch-up. There was a problem that impurities and defects increase by this etching process.

In addition, in order to prevent latch-up, a thin buried oxide layer having a thickness of 0.1 μm or less is formed below a depth of 0.1 to 1 μm of the substrate, and a device is formed on the oxide layer. This is done by partially dry etching the substrate on the thin oxide film. Subsequently, gate patterning is performed, and since the device is separated by dry etching, the thickness of the stepped region is about twice as thick as the thickness of the other region, resulting in substrate loss at the source / drain junction formation region. Thus, substrate loss not only makes the source / drain junction difficult to form, but also damages the gate oxide film, thereby reducing the reliability and yield of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which prevents latchup of a highly integrated device and minimizes occurrence of impurities and defects.

It is another object of the present invention to provide a semiconductor device manufacturing method which reduces the chip area by applying back bias to all cells by only one well pickup while preventing latch-up of the highly integrated device and minimizing impurities and defects. It is.

A semiconductor device manufacturing method of the present invention for achieving the above object is a semiconductor device manufacturing method having a peripheral circuit and a cell array, the first region of the semiconductor substrate on which the peripheral circuit is to be formed on the semiconductor substrate is opened; Forming a mask pattern; Forming an oxide film buried at a predetermined depth inside the first region of the semiconductor substrate by oxygen ion implantation; Removing the first mask pattern; Forming a second mask pattern in which a second region of the semiconductor substrate on which the cell array is to be formed is opened; Forming a well in the second region of the semiconductor substrate by injection of ion ion implantation, and forming a bottom of the well deeper than the buried oxide film; Removing the second mask pattern; Forming a third mask pattern having the device isolation region open on the semiconductor substrate; And forming a device isolation oxide film to a depth of the buried oxide film by oxygen ion implantation, wherein only one well pickup is made in a well formed in a second region of the semiconductor substrate.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical ideals of the present invention. do.

1A to 1E illustrate a process of forming a device isolation film according to an embodiment of the present invention, illustrating an embodiment of the present invention by simultaneously showing a cell region and a peripheral circuit region in the drawings.

FIG. 1A illustrates the formation of an oxide film 10 ′ on the semiconductor substrate 10, and then forming a first photoresist pattern 11 having an isolation region between transistors or an isolation region between wells by a photolithography process and injecting oxygen ions. Thus, oxygen ions 12 are injected into the isolation region between the transistors or the isolation region between the wells.

Subsequently, as shown in FIG. 1B, the first photoresist layer pattern 11 is removed, and then the second photoresist layer pattern 13 in which the separation region between the wells is opened is formed again, and then oxygen ion implantation is performed again to obtain the separation region between the wells. Allow oxygen ions 12 to penetrate deeper.

As described above, after the ion implantation is performed, as shown in FIG. 1C, when the second photoresist layer pattern 13 is removed and nitrogen annealing is performed, the semiconductor substrate at the site subjected to oxygen ion implantation is formed of oxide films 14 and 15. In this case, the depth of the oxide film 14 formed in the isolation region between the transistors is 200 to 400 nm, and the oxygen ion implantation depth is adjusted in the foregoing process so that the oxide film 15 formed in the isolation region between the wells is 1 to 2 μm.

Subsequently, in FIG. 1d, the third photoresist pattern 16 is formed again to form the N-well, and then the N-well 17 is formed by implanting phosphorus (P) ions. The depth of the N-well 17 should be lower than that of the oxide isolation film 15 for isolation between the wells formed by the oxygen ion implantation in the circuit area, and this must be done to prevent the latchup of the device.

Subsequently, in FIG. 1E, after removing the third photoresist pattern 16, the fourth photoresist pattern 18 is formed again to form the P-well, and then boron (B) ions are implanted to form the P-well 19. In this case, the depth of the P-well 19 should be lower than that of the oxide film 15 for separating the devices between the wells.

Thereafter, the photoresist film 18 is removed and a transistor is completed by performing a gate oxide film formation, a gate patterning process, a source train junction formation, a metal wiring process, and the like as a conventional subsequent process.

In one embodiment of the present invention, the device isolation film is formed by oxygen ion implantation, but the device isolation oxide film is deeply formed by two ion implantation in the isolation region between the wells, thereby preventing latch-up. In general, in the implementation of a semiconductor memory device, since only NMOS transistors are formed in a cell region in which cells are arrayed, the device isolation layer formed in the cell region does not need to be deeper than the depth of the P-well. Since the transistor and the PMOS transistor are implemented at the same time, the device isolation layer for separating the N-well and the P-well implemented in the peripheral circuit region is formed deeper than the wells to prevent latch-ups generated between the wells.

2A and 2B illustrate a process of forming a device isolation film according to another embodiment of the present invention. Similarly, another embodiment of the present invention will be described by simultaneously showing a cell region and a peripheral circuit region in the drawings.

In FIG. 2A, after forming the pad oxide film 20 'on the semiconductor substrate 20, oxygen ion implantation is performed to form a buried oxide film 21 within a depth of 1 to 2 탆 from the surface of the semiconductor substrate.

Thereafter, as shown in FIG. 2B, the photosensitive film pattern 22 having the isolation region between the transistors and the isolation region between the wells is formed, and the device isolation oxide layer 23 is formed by performing oxygen ion implantation. In this case, the semiconductor substrate 20 is formed. The buried oxide film 21 formed at a depth of 1 to 2 μm from the surface of the C) prevents latch-up, so that a separate oxide ion implantation is required to form an oxide film for deep device separation by separating oxygen from the well in the peripheral circuit region. Unlike the above-described embodiment of the present invention, the channel forming process is performed instead of the well forming process, and the subsequent processes are the same.

3A to 3C are semiconductor device manufacturing process diagrams according to still another embodiment of the present invention. Another embodiment of the present invention is not to form the buried oxide film as a whole on the wafer, but the buried oxide film is formed so that only the peripheral circuit region is formed. In the same manner as in the previous embodiment, only the isolation layer and the P-well are formed without the buried oxide layer, so that a back bias is applied to improve the refresh ability of all cells through one well pickup. It would be possible.

First, as shown in FIG. 3A, an oxide film 32 for pads is formed on the silicon substrate 31. Then, a photosensitive film pattern 33 in which only the peripheral circuit region is opened is formed, and oxygen ion implantation is performed to form only the peripheral circuit region. An investment oxide film 34 is formed.

Subsequently, as illustrated in FIG. 3B, the photoresist pattern 33 is removed, and the photoresist pattern 35 is formed by opening only the cell region. Then, boron ion is implanted to form the P-well 36.

Subsequently, as shown in FIG. 3C, the photoresist pattern 35 is removed and a photoresist pattern 37 is formed in which device isolation regions between transistors and device isolation regions between the wells are opened, and oxygen ion implantation is performed for device isolation. The device isolation oxide film 38 is formed.

Here, since the cell region has no problem of latch-up between the wells, the device isolation oxide film for transistor-to-transistor isolation does not have to be deeper than the wells, and the P-wells of the unit cells in the cell region are all connected. One P-well pickup can apply a back bias to all cells. That is, in the structure of FIG. 2b described above, all wells must be picked up for each cell in order to apply the back bias. However, in the structure of FIG. 3c, which is another embodiment of the present invention, one well pickup may be formed. The chip area of the device can be reduced. In addition, the peripheral circuit region where the latch-up between the P-well and the N-well well may occur is three-dimensionally separated by a buried oxide film, thereby preventing the problem of latchup in advance.

As described above, the present invention does not form the device isolation oxide film after etching the substrate to form a trench, but instead forms an oxide film by performing nitrogen annealing after oxygen ion implantation. To improve complexity and problems.

In addition, by solving the latch-up problem and the well pick-up problem for back bias application at the same time there is an effect of improving the reliability of the device as well as the yield.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (2)

A method of manufacturing a semiconductor device having a peripheral circuit and a cell array, the method comprising: forming a first mask pattern on an opening of a first region of a semiconductor substrate on which the peripheral circuit is to be formed; Forming an oxide film buried at a predetermined depth inside the first region of the semiconductor substrate by oxygen ion implantation; Removing the first mask pattern; Forming a second mask pattern in which a second region of the semiconductor substrate on which the cell array is to be formed is opened; Forming a well in the second region of the semiconductor substrate by injection of ion ion implantation, and forming a bottom of the well deeper than the buried oxide film; Removing the second mask pattern; Forming a third mask pattern having the device isolation region open on the semiconductor substrate; And forming a device isolation oxide film to a depth of the buried oxide film by oxygen ion implantation. The method of claim 1, wherein only one well is picked up in the well formed in the second region of the semiconductor substrate.