KR0148178B1 - Apparatus which employs a memory to compensate a moving image - Google Patents

Abstract

The present invention relates to a memory device for image motion compensation. The memory device of the present invention outputs data of estimated blocks based on the same motion vector in units of rows, receives memory compensation data and stores them in columns, and a line memory for storing data output from the memory. The open dress for specifying the position of the line memory to be accessed and read is inputted according to the CAS signal, and the open dress latch portion for specifying the position of the line memory to be accessed and read while automatically increasing the open dress and the open dress portion The chip adds the data stored in the open address of the specified line memory and the DPCM data processed by the link exchange and outputs the motion compensation data, and the multiplexer delivers the data output from the adder to the memory. Doing.

Accordingly, the present invention can easily configure the image decoder in HDTV by performing the image motion compensation in the memory device, and provides the effect that the memory does not need to operate at high speed.

Description

Memory device for image motion compensation

1 is a block diagram showing a memory device for image motion compensation according to the present invention.

2 is a conceptual diagram illustrating an image motion compensation process in the memory device of FIG. 1.

3 is an operation timing diagram for the memory device of FIG.

* Explanation of symbols for main parts of the drawings

10: memory device 11: memory

13: Line memory 15: Open dress latch

17: Multiplexer 19: Adder

The present invention relates to motion compensation of an image in a video decoder of an HDTV receiver. In the system of a video motion compensation method which is generally used in hardware, the present invention compensates using a page mode function of a DRAM. The present invention relates to a memory device for compensating for motion of a video, which can simplify a video decoder and reduce memory processing speed.

In general, in a coding / decoding apparatus for compressing and restoring massive video information in high-definition TV, CATV, video conferencing, and video telephony, a motion compensator is essential for efficient compression of massive video information, and a motion compensator is used to compensate for video motion. The operation of reading or writing video information from a frame memory is often performed. In general, the basic unit of motion compensation is a macroblock, which is 16 (horizontal) x 16 (vertical) pixels, and one pixel of image information corresponds to one byte of memory capacity in the case of a luminance signal. If it is assumed that the memory segment unit of the frame memory is 8 byte unit, one address is allocated in 8 byte unit which is one segment, and 8 pixel image information can be stored in each segment, thereby accessing 8 pixel image information at a time. To read or write.

In order to compensate for the motion, memory input data stored in the frame memory is read, DPCM data for motion compensation processed by the inverse transform is added to the image decoder, and the addition result is stored in the frame memory. In this case, the time required for reading the image information from the memory, the time taken by the decoder to add the corresponding DPCM data, and the time for writing the addition result back to the memory are large. In addition, since the unit of reading or writing image information from the memory is 8 pixels, when the number of pixels constituting one screen is large, when the motion compensation is performed by the conventional method, data must be exchanged at a very high speed between the decoder and the memory. There is a problem in that a memory is required and a lot of power consumption is required for the memory interface in the decoder.

Accordingly, an object of the present invention is to provide a video motion compensation memory device that can reduce the burden on the decoder because the decoder can perform the motion compensation process in the memory to solve the above-mentioned problems, so that the decoder only needs to write to the memory. have.

An image motion compensation memory device of the present invention for achieving the above object is a memory device for performing an image motion compensation function, which designates a storage position of estimated block data by a motion vector to access and read an input address. A first operation timing process of inputting a row address and outputting data stored in a specified row address position to a line memory; and a row designated by inputting an input address into a row address and an open address specifying a storage location of motion compensation data, respectively A memory for performing a second operation timing process for storing motion compensation data in a position where an address and an open dress are combined, and an open dress for designating a line memory location to be accessed and read for the first time are received, and the open dress is automatically increased. Open to specify the location to access and read A line memory for receiving data from a latch unit, a data load signal for storing row-by-row data read out from the memory, storing data, and outputting data stored at an open dress position of the open latch portion, and an inverse conversion process. And an adder for adding the input data to be compensated for the motion and the column unit data read out from the line memory, and outputting the addition result as the motion compensation data to the memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a memory device for image motion compensation according to the present invention. As shown, the memory device 10 of the present invention is implemented as one chip and is enabled by an external chip select (CS) signal. The memory device 10 includes a memory 11 having a DRAM structure and a line memory 13 for storing data read from the memory 11 in units of rows. The memory 11 stores the data of the estimation block by the same vector, and the addition result of the adder 19, which will be described later, is located at the position where the row address A _R and the opening address A _C designated by the address input unit are combined. Save it. The memory 11 is provided with a row address strobe (RAS) signal and a column address strobe (CAS) signal to recognize that the input address is a valid row address and an open address. The memory device 10 also receives an address ADDR, which specifies the position of the line memory 13 to be accessed and read from the address input section for the first time, and an open-drag section for specifying a position to access and read while automatically increasing the address. (15) is provided. An open dress strobe (CAS) signal is added to the open latch latch 15 so as to recognize that the input address is a valid address, and an address load (AL) signal is added to latch the input address. A Motion Compensation (MC) signal is added to automatically increase the address. The data input / output terminal D of the memory 11 receives the estimated block data by the same vector from the decoder and the addition result of the adder 19 to be described later, and stores it in the memory 11 or the moving compensation data stored in the memory 11. A multiplexer (MUX) 17 for outputting the to the decoder is connected. Opens the DPCM data input between the multiplexer (MUX) 17 and the line memory 13, adds the data to the open address of the line memory 13 specified by the latch latch unit 15, and adds the result. The adder 19, which outputs to the multiplexer (MUX) 17, is connected. The adder 19 is configured to perform an addition operation by the above-described dynamic compensation (MC) signal.

Operation of the image motion compensation memory device 10 according to the present invention configured as described above will be described in more detail with reference to FIGS. 2 and 3.

2 is a conceptual diagram illustrating a motion compensation process in the memory device 10 of FIG. 1, and FIG. 3 is an operation timing diagram of the memory device 10 of FIG. 1.

First, as shown in FIG. 2, the memory device 10 for performing the motion compensation process of the image has a high level at which the chip select (CS) signal input as shown in FIG. If it is, it becomes an enable state. Here, it is assumed that each component is enabled for the signal of the high potential level. The open latch section 15, the adder 19, and the line memory 13 have an input address / data (A / D LOAD) signal and a dynamic compensation (MC) signal represented by binary form 0. If the level is low, it becomes a disabled state and does not perform motion compensation.

On the contrary, in the case where the motion compensation is to be performed in units of 8 × 8 to 16 × 16 pixels for a plurality of consecutive pixels, the address input unit stores the address ADDR in the order shown in FIG. ). First, the address input unit inputs into the memory 11 an address ADDR which specifies the location of the memory 11 to be accessed and read first. At this time, the memory 11 has a high potential level row address strobe represented by binary form 1 as shown in FIG. 3 (C) in accordance with the address input timing so that the input address can be recognized as the row address A _R. RAS) signal is received. The memory 11 stores the address ADDR designated as the row address A _R of FIG. 3 (B) at the head of the high potential level section of the row address strobe RAS signal of FIG. 3 (C). Receive input. The row address A _R applied to the memory 11 represents a position for storing data to be motion compensated, i.e., N x N block (indicated by part A of FIG. 2) data estimated by the motion vector. The memory 11 outputs the data of the portion A of FIG. 2 stored at the designated row address A _R to the line memory 13 in units of rows. The line memory 13 stores data applied from the memory 11 in accordance with an address / data load (A / D LOAD) signal. At this time, the open latch unit 15 receives an address ADDR specifying a position of the line memory 13 to be first accessed and read from the address input unit. The address latch unit 15 has a high potential level open-dress strobe (CAS) signal expressed in binary form 1 as shown in FIG. 3 (d) in accordance with the address input timing so that the input address can be recognized as a dress. Get input. The open dress latch unit 15 inputs a high potential level address / data load (A / D LOAD) signal represented by binary form 1 as shown in FIG. 3 (G) to latch the input open dress. Receive. The open dress latched in the open dress latch section 15 indicates an open dress position for accessing and reading the row unit data stored in the line memory 13. In this operation timing, the data input from the decoder side is dummy data as shown in FIG.

In this timing state, the memory device 10 performs motion compensation using the page mode function of the DRAM. Generally, there is a square memory array among DRAM characteristics, and after the row address of the memory is designated, the open address is designated, and the data stored in the memory address witch which combines the specified row address and the open address is read or inputted. Save it. A DRAM having such a structure reads or writes a large amount of data through a page mode in which a row address remains unchanged and a continuous data is read and a continuous page is read.

The address input unit then inputs into the memory 11 an address ADDR specifying a location of the memory 11 for storing motion compensation data. At this time, the memory 11 shows the input address as a row address (indicated by A _R ′ so as to be distinguished from the row address A _R to read out data). As described above, a high potential level row address strobe (RAS) signal represented by binary form 1 is received. Here, the memory 11 has an address ADDR designated as the row address A _R 'of FIG. 3 (B) at the head of the high potential level section of the row address strobe (RAS) signal of FIG. 3 (C). Get input. The row address A _R ′ applied to the memory 11 indicates a position for storing motion compensation data, that is, an addition result of the adder 19 (indicated by part B in FIG. 2). At this time, the corresponding DPCM data (indicated by part C of FIG. 2) subjected to inverse conversion processing from the decoder side is input to one side of the adder 19. The line memory 13 is also read, and the data stored at the position designated by the open dress A _C latched by the open latch unit 15 is read out and input to the other end of the adder 19. The adder 19 stores the corresponding DPCM data (Part C of FIG. 2) and the data received from the line memory 13 (Part A of FIG. 2) of the dynamic compensation (MC) signal shown in FIG. It is added within the high potential level section and output to the multiplexer (MUX) 19. The multiplexer (MUX) 19 inputs data applied from the adder 17 into the memory 11. At this operation timing, the address input unit inputs the open address A _C ′ in the designated row address A _R ′ to the memory 11. The memory 11 has a high potential level open-dress strobe (CAS) expressed in binary form 1 as shown in FIG. 3 (D) at an address input timing so that the input address can be recognized as a dress A _C '. Receive a signal. Here, the open dress designated to the memory 11 is an address for storing the addition result of the adder 19 in units of columns at the position indicated by the second part B of the memory 11. The memory 11 is an addition result of the adder 17 inputted through the multiplexer MUX 19 at a position where a specified row address A _R ′ and open addresses A _CI 'to A _C4 ' are combined. Save the motion compensation data.

The open dress latch unit 15 increases and extends the open dress which is automatically latched whenever a falling edge of the open dress strobe (CAS) signal is detected in the effective section of the dynamic compensation (MC) signal. The memory 11 receives a new open dress from the address input unit for each valid section of the open address strobe (CAS) signal at the designated row address position. At this time, the DPCM data is input and the motion compensation data obtained by the adder 19 is stored at the position of every open dress designated in the memory 11. The memory device 30 performs the above process during the write enable period WE in the row address designation state of the memory 11.

As described above, the present invention relates to a memory device for image motion compensation, which takes a lot of time to read data stored in the memory, add the DPCM data to the decoder, and store the data again in the memory to compensate for the image motion. In addition, the memory device can simplify the configuration of the image decoder by performing the motion compensation function in the memory device, compared to the conventional method of using the memory capable of high speed processing for a limited time. Has an effect.

Claims (7)

A memory device for performing a video motion compensation function, comprising: a line memory receiving data stored in a specified row address position by inputting a row address specifying a storage location of estimated block data by a motion vector to read an input address; A second operation timing process of outputting a second motion timing signal and a second operation of storing the motion compensation data at a position where the specified row address and the opening address are respectively inputted to the row address and the opening address which designate the storage address of the motion compensation data; A memory for performing an operation timing process; An open-dressing latch unit which receives an open-dress for designating a line memory location to be accessed and read for the first time, and designates a location to be accessed and read while automatically increasing the open-dress; A line memory configured to receive a data load signal for storing the row unit data read from the memory, store data, and output data stored in the open dress switch of the open dress latch unit; And an adder for adding inverse transform-processed input data and column unit data read from the line memory and outputting the addition result as motion compensation data to a memory. The image motion compensation memory device of claim 1, wherein each component of the memory device is implemented as a single chip to be enabled by an external chip select signal. The method of claim 2, wherein the open dress latch unit receives an open dress strobe signal for recognizing that an input open dress is a valid address, receives an address load signal for latching the open dress, and automatically increases the latched open dress. A memory device for image motion compensation, characterized in that for receiving a dynamic compensation signal and an open dress strobe signal. 4. The method of claim 3, wherein the open latch latch latches the input open dress during the valid period of the address load signal, and automatically increases the latched open dress in synchronization with the falling edge of the open dress signal during the valid period of the compensating signal. Memory device for image motion compensation characterized in that. The image motion compensation according to claim 1, wherein the memory has a DRAM structure having a square memory array, and uses a page mode function of a DRAM that reads or writes data while changing only an open address after a row address is designated. Memory device. The image motion compensation of claim 5, wherein the memory receives a row address strobe signal for recognizing that the input address is a valid row address, and receives an open address strobe signal for recognizing that the input address is a valid open address. Memory device. The image motion compensation memory device of claim 6, wherein the memory alternately performs a first operation timing process and a second operation timing process for each input write enable period.