KR0146255B1 - Modified booth multiplier - Google Patents

Abstract

According to the present invention, an encoder outputs a selection signal by encoding a multiplier input so that the selector selects a plurality of cube numbers supplied to the first to fourth complementary selectors, and first to second signals by the signals output from the encoders. Since the first and second adder arrays, which add the data generated by the second complementary selector according to the number of digits of each bit, and the adder which outputs the carry outputs from the first and second adder arrays, are added to reduce the number of steps The present invention relates to an expansion booth multiplier with improved processing speed.

Description

Extension Booth Multiplier

1 is a circuit diagram of a conventional multiplier in a case where the multiplication is 8 bits.

2 is a 4-bit expansion booth multiplier circuit diagram of the present invention for a case where the multiplication is 12 bits

3 is a 5-bit expansion booth multiplier circuit diagram of the present invention for a case where the multiplication is 16 bits.

* Explanation of symbols for main parts of the drawings

20: Number generator 21-23,25: 1-4 2's complement selector

24: first adder array 26: second adder array

27: adder 30: encoder

The present invention relates to a multiplier, and more particularly, an encoder for outputting a selection signal by encoding a multiplier input so that the selector selects a plurality of multiplicative numbers supplied to first to second complementary selectors; First and second adder arrays configured to add data generated by the first to fourth second complement selectors according to the number of digits of each bit by the signal output from the encoder; The present invention relates to an extension booth multiplier that improves the processing speed by reducing the addition step by implementing an adder that adds and outputs a carry output from the first and second adder arrays.

The present invention can be very useful for a digital signal processing (Digital Singal Processor) and coprocessor that requires a high processing speed.

In the conventional multiplier (Modified Booth Mutiplier) addition step, the number of complements of 2 is X,

Provided that N = 0, 2, 4,... m-1.

If m-1 is not a multiple of 2, it is expanded to be a multiple of 2.

The formula (Equation 2-2) can be made to the booth encoding table as shown in Table 1.

(N = 0.2… m-1)

Implemented when m = 8 in the above formula (Equation 2-3), and shows a conventional multiplier for the case where the multiplication is 8 bits as shown in FIG.

The conventional multiplier as described above has a problem in that the addition speed is too slow due to the large number of addition steps in performing the multiplication.

Accordingly, an object of the present invention is to reduce the number of adder array staff so that multiplication at a higher speed can be performed.

In order to achieve the above object, the present invention includes an encoder for outputting a selection signal by encoding the input multiplier so that the selector selects a plurality of the number of cubes supplied to the first to the fourth complementary selector; First and second adder arrays configured to add data generated by the first to fourth two complement selectors according to the number of digits of each bit by the signal output from the encoder; The adder outputs by adding a carry output from the first and second adder array.

Hereinafter, the technical principles of the 4-bit extended booth multiplier used in the present invention will be described.

Generally two's complement

It can be written as follows, and if it is grouped by 23 units in the above formula (Equation 2-1),

(N = 0,3,6,9, ... m-1)

If m-1 is not a multiple of 3, expand it to be a multiple of 3.

Table 2 which is a 4Bit expansion booth encoding table can be made by the above equation (Equation 3-1).

The circuit diagram in the case of inflation when m = 12 in the above formula (Equation 3-2) is the second diagram.

Let's take a look at the 5Bit expansion booth multiplier which is the most efficient in the bit recording method according to the above equation (Equation 3-2).

In general, if the number of two's complement is X,

Tied in units of 24 in the above formula,

(N = 0,4,8,12, m-1)

Here, if (m-1) is not a multiple of four, it should be expanded to be a multiple of four.

(N = 0.4.8.12m-1)

In the above formula (3-3), when m = 16, the circuit diagram of FIG. 3 corresponds to hardware.

When the 5Bit extended booth encoding table is made in the above equation (Equation 3-3), it is as shown in the following table (Table 3).

Hereinafter, with reference to the accompanying drawings the present invention will be described in more detail.

FIG. 2 is a circuit diagram when a multiplier is 12 bits. When the multiply number is input, the multiplier generator 20 generates O * Y, 1 * Y, 2 * Y, 3 * Y, 4 * for the multiplier. A Y (pig number) is made and supplied to the first to fourth complementary selectors 21, 22, 23 and 25.

On the other hand, in the 4-bit booth encoder 30, as shown in Table 2, a selection signal for 0 * Y, 1 * Y, 2 * Y, 3 * Y and a selection signal to be performed during 2Y complement are made. By applying to the second complementary selectors 21, 22, 23 and 25, the selectors 21, 22, 23 and 25 select data in parallel.

The data generated by the first to the 42nd complement selectors 21, 22, 23, and 25 are added to the adder 27 by adding operations in the first and first adder arrays 24 and 26 according to the number of digits of each bit. Output

3 is an application example of a 16-bit multiplier using a multiplication method extended to 5 bits.When the multiplicative number is input, the multiplier generator 40 outputs 0 * Y, 1 * Y, ... 7 * Y for the multiplier. Each of 8 * Y is made and supplied to the first to fourth complementary selectors 41, 42, 43, and 45.

On the other hand, the 5-bit booth encoder 48 selects a selection signal for 0 * Y, 1 * Y ... 7 * Y, 8 * Y and a control signal for whether or not it is a sign value as shown in Table 3 above. Make.

If the number of products is 7Y and the sign, the two's complement selectors 41, 42, 43, and 45 make -7Y and send it to the first and second adder arrays 44,46.

The data added to the number of digits in the first and second adder arrays 44 and 46 is sent to the final adder 47 and output.

As described in detail above, the present invention has the effect of improving the processing speed by reducing the addition step to be used in digital signal processing and coprocessor.

Claims (4)

In the multiplier that calculates the product of the input variables X and Y, if the multiplication is input when the multiplication is 12 bits, the multiplication (0 * Y, 1 * Y, 2) Means for making * Y, 3 * Y, 4 * Y) and supplying them to the first to fourth complement selectors; A select signal for 0 * Y, 1 * Y, 2 * Y, 3 * Y and a 2Y complement are generated by a 4-bit booth encoder and applied to each of the first to fourth complement selectors. Means for selecting data; By adding the carry output from the first and second adder array to the adder according to the number of digits of each bit, the data generated by the first to fourth complement selectors are output to the adder, thereby reducing the addition step and improving the processing speed. Expansion booth multiplier. The 4-bit extension boot multiplier according to claim 1, wherein the 4-bit extended boot multiplier encodes an input multiplier so that the selector selects a plurality of multiplies supplied to the first to second two complement selectors and outputs a selection signal. A booth encoder; First and second adder arrays configured to add data generated by the first to fourth two's complement selectors according to the number of digits of each bit by the signal output from the 4-bit bus-en core; And an adder configured to add and output a carry output from the first and second adder arrays. In the multiplier that calculates the product of the input variables X and Y, if the multiplier is input when the multiplier is 16 bits, the multiplier for the multiplier (O * Y, 1 * Y, 2) Means for making * Y, 3 * Y, ... 7 * Y, 8 * Y) and supplying to the first to fourth complementary selectors; In the 5-bit booth encoder, a selection signal for 0 * Y, 1 * Y, 2 * Y, 3 * Y ... 7 * Y, 8 * Y and a selection signal to be performed during 2Y complement are made. Means for applying data to the two's complement selector to select data at each selector; By adding the carry output from the first and first adder array to the adder according to the number of digits of each bit, the data generated by the first to fourth complement selectors are added to the adder, thereby reducing the addition step and improving the processing speed. Expansion booth multiplier. 4. The 5-bit expansion booth multiplier according to claim 3, wherein the 5-bit extension boot multiplier outputs a selector signal by encoding an input multiplier so that the selector selects a plurality of multiplies supplied to the first to fourth complementary selectors. A booth encoder; First and second adder arrays configured to add data generated by the first through fourth complementary selectors according to the number of digits of each bit by signals output from the 5-bit bus encoder; And an adder configured to add and output a carry output from the first and second adder arrays.