KR0141319B1 - Multi-point control unit architecture for video conference - Google Patents

Abstract

The present invention relates to the structure of the MCU 20 of the video conferencing system in the PCs 2-1 to 2-n connected to the LAN card 10, the code / decoder 30 and the PC interface 40. An address decoder 23 for decoding an ID of audio and video data input into the MCU in a stream form and outputting a decoded signal; At least two decoder first-in, first-out buffers (FIF01-FIF08) in which addresses are updated for each intraframe in a data buffer corresponding to each ID, and the audio and video data inputted according to the decoding signal of the address decoder is recalled. An A / V separator 22 selectively applying to the decoder first-in first-out buffers FIFO1-FIFO8; A decoder input switch (24) connected to the decoder first-in first-out buffer (FIF01-FIF08) and selectively outputting video and audio signals of the first-in first-out buffer (FIF01-FIF08); A dual port RAM 25 connected to the PC interface circuit 40 and receiving and transmitting all information transmitted from the PCs 2-1 to 2-n; A header generator 26 for inserting a header into the encoded video and audio data applied to the MCU 20; An encoder first-in first-out buffer (FIFO) connected to the header generator 26 and outputting in accordance with a bit transfer ratio at the time of transmission of the compressed data applied from the header generator 26; A microprocessor 27 for controlling each component of the MCU 20 is provided.

Therefore, the present invention has the effect that the video conference can be smoothly performed by allowing the user to select and view a plurality of attendees while attending the video conference.

Description

Multipoint Control Unit Structure for Video Conference

1 is a conceptual diagram of a video conferencing system using a conventional LAN environment,

2 is a conceptual diagram of an entire LAN network required to carry out the present invention;

3 is an internal block diagram of a personal computer having a multi-point control unit according to the present invention;

4 is a block diagram showing the structure of a multi-point control unit according to the present invention;

5 is a screen state diagram according to the multi-point control unit structure according to the present invention.

* Explanation of symbols for main parts of the drawings

10: LAN card 20: MCU

30: Code / Decoder 22: A / V Separator

23: address decoder 24: decoder input switch

25: dual port RAM 26: header generator

27: microprocessor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a videoconferencing system, and more particularly, to a structure of a video conferencing multi point control unit (hereinafter referred to as MCU) that enables a plurality of images of conference participants to be viewed.

Video conferencing is a system that sends video and audio between distant conference rooms, allowing attendees to conduct meetings as if they are in the same meeting room while looking at the monitor. This video conferencing system is expected to be a system that can exchange information, make decisions, and have an economic effect depending on the situation in business activities.

1 is a conceptual diagram of a video conferencing system using a LAN environment.

As shown in the drawing, a conventional video conferencing system using a LAN environment is connected to a plurality of PCs 2-1 to 2-n attending a video conference to one MCU 1. In this environment, when the administrator 3 of the system designates one of the PCs 2-1 to 2-n, the audio and video information transmitted from the designated PCs 2-1 to 2-n are transferred through the MCU 1. It is a system which is transmitted to each PC 2-1 to 2-n.

Therefore, in this method, only one person, i.e., one PC (2-1 to 2-n) is captured, and only the input video and audio signals are transferred to the remaining PCs (2-1 to 2-n). Attendees will be able to watch only one selected picture and audio.

However, depending on the state of the conference, there may be cases where the user wants to watch the video of the other attendees in addition to the selected one.

The present invention has been made to solve this problem,

SUMMARY OF THE INVENTION An object of the present invention is to provide a MCU for video conferencing that enables smooth video conferencing by selectively displaying a plurality of video of meeting participants in one screen.

A feature of the present invention for achieving this object relates to the MCU structure of a video conferencing system in a PC connected to a LAN card, a code / decoder and a PC interface, wherein the audio and video data input into the MCU in the form of a bit stream. An address decoder for decoding an ID and outputting a decoded signal; At least two decoder first-in first-out buffers whose address is updated in each intraframe in the data buffer corresponding to each ID, and audio and video data inputted according to the decoding signals of the address decoder are selectively added to the decoder first-in first-out buffer. An A / VD separator applied with; A decoder input switch connected to the decoder first-in first-out buffer and selectively outputting video and audio signals of the first-in first-out buffer; A dual port RAM connected to the PC interface circuit and receiving and transmitting all the information transmitted from the PC; A header generator for inserting a header into the encoded video and audio data applied to the MCU; An encoder first-in, first-out buffer connected to the header generator and outputting at a bit transmission ratio upon transmission of the compressed data applied from the header generator; In the MCU structure of the video conferencing system having a microprocessor for controlling each component of the MCU,

2 is a conceptual diagram of an entire LAN network required for carrying out the present invention, in which a plurality of PCs 2-1 to 2-n having an MCU 20 are connected to a network 100 through a line. At this time, it is said that there is a person who will conduct a multi-party conference in one line (dedicated or general line) in such a LAN network, there is a group ID for all of them, and for each PC (2-1 to 2-n) There will be a separate ID.

3 shows a block diagram of these PCs 2-1 to 2-n. As shown in FIG. 3, a LAN card 10 is constructed in the PCs 2-1 to 2-n. The video and audio data compressed in the form of a bit stream input through the LAN card 10 is applied to the MCU 20 through the LAN card 10, and the video and audio data compressed and output in the form of a bit stream from the MCU 20 is output to the LAN card 10. Is applied to the line.

At this time, the MCU 20 selects the compressed data applied from the LAN card 10 and applies the data corresponding to the image to be displayed on the screen to the code / decoder 30, and the remaining compressed data is intraframe to the memory buffer. (Intraframe) Stores only data.

The code / decoder 30 is configured to decode and display the data selected by the MCU 20 on the monitor as described above, and encode and apply the video and audio signals input through the camera and the speaker to the MCU 20. have.

The code / decoder 30 to the LAN card 10 and the MCU 20 is connected to a PC interface 40 such as an Industry Standard Architecture (ISA) or a Parallel Carry Iterconnection (PCI).

4 shows a block diagram of the internal configuration of the MCU 20.

As shown in the figure, a header corresponding to a group is applied to the MCU 20 in the form of a bit stream in addition to the compressed video and audio signals. In addition, the MCU 20 is connected to the PC interface 40 through a bus such as ISA or PCI to communicate with the PCs 2-1 to 2-n and the microprocessor 27 for control in the MCU 20. Let's do it.

In addition, the ports P1, P2, and P3 are for applying the compressed video and audio data selected by the MCU 20 to the code / decoder 30, as can be seen in the description below. / To receive the video and audio data applied from the decoder (30).

As described above, the audio and video data input into the MCU 20 in the form of a bit stream is applied to the A / V separator 22 and the address decoder 23, and the address decoder 23 decodes the ID of the applied data. Is applied to the A / V separator 22.

The A / V separator 22 selectively applies the input audio and video data to the decoder first-in first-out buffers FIF01-FIF08 according to the decoding value of the address decoder 23.

In this case, the decoder first-in first-out buffer (FIF01-FIF08) is designed to update the address per every Intraframe in the buffer corresponding to each ID. Thus, these decoder first-in first-out buffer (FIF01-FIF08) is intraframe We need logic to detect this and make sure the address is updated every intraframe. When the decoder first-in, first-out buffers FIF01-FIF08 are enabled for decoding purposes, they are delivered in successive bit streams.

The decoder input switch 24 is connected to the decoder first-in first-out buffer (FIF01-FIF08) to selectively apply the compressed video and audio signals of the decoder first-in first-out buffer (FIF01-FIF08) to the ports (P1, P2, P3). It is configured to.

At this time, the dual port RAM 25 connected to the PC interface 40 is for controlling all information of the PCs 2-1 to 2-n, and the PCs 2-1 to 2-n. n) is used to transmit and receive all information transmitted from the PCs 2-1 to 2-n in order to control these MCUs 20.

The header generator 26 connected to the port P4 is for inserting the header into the encoded video and audio data applied to the MCU 20, and the header contains the necessary group ID and various information.

The encoder first-in first-out buffer (FIF09) connected to the header generator 26 is for outputting in accordance with the bit transfer ratio at the time of transmission of the compressed data applied from the header generator 26.

The microprocessor 27 connected to the dual port RAM 25 and the header generator 26 is configured to control the respective components of the MCU 20 described above.

The operation of the MCU for video conferencing according to the present invention configured as described above is as follows.

Initially, an initialization command is applied to the microprocessor 27 in the MCU 20 through the PC interface 40. At this time, the initialization writes data to the dual port RAM 25 and interrupts the microprocessor 20 in the MCU 20. The microprocessor 27 then reads the data recorded in the dual port RAM 25. At this time, the entire system is initialized by the read data.

When the code / decoder 30 is initialized to proceed with the video conference after the initialization is completed, the LAN card 10 is also initialized.

When this initialization process is completed, the image and input video and audio signals are compressed by the code / decoder 30 by the camera and the audio and then applied to the port P4. The video and audio data applied to the port P4 attaches the ID corresponding to the group to the header every segment (about 2 Kbytes) in the header generator 26.

At this time, data having its own header are inserted through the encoder first-in first-out buffer (FIF09), and these data are transmitted to each other for the mutual video conferencing group through the LAN network.

On the other hand, audio and video data in the form of a compressed bit stream are applied to the A / V separator 22 and the address decoder 23, respectively. Since the data has its own ID to separate conference participants, the address decoder 23 decodes the ID and inputs the data input to the A / V separator 22 to the corresponding decoder first-in, first-out buffer (FIF01-). Selectively to FIF08).

At this time, the decoder first-in first-out buffer (FIF01-FIF08) is formed with a separate detector for detecting the intra frame to reset the intra-frame of the compressed data, the compressed data is stored in each intra frame using this detector Is updated. When the information is requested by the decoder input switch 24, the information is stopped at this time, and continuous compression information is output.

At this time, the decoder input switch 24 is for displaying a speaker of interest on the screen during video conferencing, and selectively applies data of the decoder first-in-first-out buffers FIF01-FIF08 to the code / decoder 30. .

5 shows an example of a state displayed on the screen according to the present invention. In the figure, the person is his or her screen watching the screen, and the image means another participant who is attending the video conference. In FIG. 5, only four speakers are displayed, but according to the above-described embodiment, it can be seen that eight speakers can be displayed.

As described above, the present invention enables the video conference to be performed smoothly by allowing the user to select and view a plurality of participants during the video conference.

Claims (1)

An address decoder 23 for decoding the ID of the audio and video data input into the multi-point control unit in the form of a bit stream and outputting a decoded signal; At least two decoder first-in, first-out buffers (FIF01-FIF08) for updating the address value per intraframe in the data buffer corresponding to each ID; An A / V separator 22 for selectively applying audio and video data input according to a decoding signal of an address decoder to the decoder first-in first-out buffers FIF01-FIF08; A decoder input switch (24) connected to the decoder first-in first-out buffer (FIF01-FIF08) and selectively outputting video and audio signals of the decoder first-in first-out buffer (FIF01-FIF08); A dual port RAM 25 connected to the PC interface circuit 40 and receiving and transmitting all information transmitted from the PCs 2-1 to 2-n; A header generator 26 for inserting a header into the encoded video and audio data applied to the MCU 20; An encoder first-in, first-out buffer (FIF09) connected to the header generator 26 for outputting in accordance with the bit transfer ratio at the time of transmission of the compressed data applied from the header generator 26; Multipoint control unit structure of a video conferencing system having a microprocessor (27) for controlling each component of the MCU (20).