KR0141296B1 - Apparatus for generating clock signals in a digital european cordless telecommunication radio fixed port - Google Patents

Abstract

The present invention relates to a data clock signal generating apparatus of a deck base station suitable for making a signal that is out of phase with the data clock signal for a data clock signal used for a modular bus of an integrated telecommunication network in a deck wireless base station. According to the present invention, when the phase velocity controller 60 generates a signal having a phase higher than that of a signal based on a specific signal, various gate signals and controls that cannot be processed by the conventional DCL clock alone when a speech coding method having a high speech compression rate is used. Can be used to generate a signal.

Description

DECT base station data clock signal generator.

Figure is a block diagram showing an embodiment of a data clock signal generation apparatus of a deck base station according to the present invention.

* Explanation of symbols for main parts of the drawings

10: IOM2 bus unit 20: high frequency clock generator

30: clear signal generation unit 40: DCL detection unit of a specific time

50,70: first and second counter 60: phase velocity control unit

80: comparison unit

The present invention is to use a wireless access method of the Digital European Codeless Telecommunications (DECT) method, which is a standard for personal mobile communication in Europe prescribed by the European Telecommunication Standards Commission, for an Integrated Services Digital Network (ISDN) exchange. The present invention relates to a device for connecting a deck wireless base station to an integrated telecommunication network switch, and is particularly used for a modular (ISDN Oriented Modulo: IOM2, hereinafter referred to as IOM2) bus in a deck wireless base station. The present invention relates to a data clock signal generator of a dec base station suitable for producing a signal in advance of the data clock signal with respect to the data clock signal.

In order to connect with the general information network switch, the general information network communication controller for connection with the U interface, the D channel controller for processing the D channel in the information transmission through the U interface, and the B channel A B-channel controller for processing is connected in the form of an IOM2 bus.

In addition, since the speech data at the exchange is processed as a pulse code modulation (PCM) type signal, the speech data transmitted from the dec radio base station to the exchange is, for example, pulse code modulated data having a transmission rate of 64 kbps. Should be

However, since the speech coding scheme defined by the deck wireless base station is a 32 kbps adaptive pulse code modulation (ADPCM) scheme, voice information in the wireless base station between the wireless base station and the terminal (or hand set) is processed by the ADPCM.

Therefore, if using the IOM2 bus known as 64 kbps of PCM data, there is no problem, but the connection between the dec radio base station and the terminal (or portable telephone) is wirelessly connected, and 32 kbps of voice is used to increase the efficiency of the wireless channel. When connecting between deck-based wireless base stations using the ADPCM method, the signal type of the known IOM2 bus cannot be used as it is.

In other words. Until now, the voice information of one subscriber could be transmitted through one 8 channel, but as in the dec method, when two subscribers' information are transmitted in one B channel using 32 Kbps ADPCM voice coding method In this case, the clock signal of the existing simple IOM2 bus is used to process voice information about two subscribers in one B channel and transmit them, or separate voice information of two people transmitted through one B channel. You can't handle it alone.

This has led to the use of more than one IOM2 bus in a board in a dart wireless base station.

As described above, when two or more signals generated on the IOM2 bus are used on one board, voice information of two subscribers is combined and transmitted in one B channel, or two people transmitted through one B channel. Rising edges that coincide with the frame synchronization signal are used for the purpose of generating voice input information separately, load input signals of registers used in the present invention, and masking signals of ADPCM and PCM conversion signals. Some signal is required that has a rising edge and a much shorter duration than the frame sync signal.

Here, the terms used are simply defined as follows.

Integrated Services Digital Network (ISDN):

As a digital communication network that provides various types of services comprehensively, many existing communication services had to establish a communication network for each of them, but this is not preferable from the viewpoint of the communication network and the efficiency of the service.

Therefore, the integrated information and communication network is a communication network recommended by the CCITT. As an alternative, the integrated information and communication network integrates and connects various existing communication networks in a digital manner, and provides comprehensive services such as telephone, telex, facsimile, and videotex. 통신 One network.

In recent years, the standardization of the Broadband Integrated Services Digital Network (BISDN), which is one step further from the comprehensive information network, to comprehensively provide hundreds of Mbpb-class broadband services such as high definition television signals.

However, only the reference signals of the IOM2 bus (for example, FSC signal and DCL signal) configured to use one conventional IOM2 bus, such as combining or separating signals from two or more IOM2 buses, can be processed. In order to be inadequate or lacking.

That is, according to the request as described above, a certain reset signal having a shorter duration than the FSC signal and the DCL signal is required, and a DCL signal delayed for a predetermined period based on the newly generated reset signal, that is, the first based on the FSC signal. When counting from DCL, since the rising edge of the first DCL signal overlaps the FSC signal, the first DCL signal cannot be used as the clear signal because the rising edge of the first DCL signal overlaps with the FSC signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a data clock signal generating apparatus of a deck base station capable of processing data of the deck base station without errors.

Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings.

Referring to the accompanying drawings, the accompanying drawings are block diagrams showing an embodiment of a data clock signal generating apparatus of a base station according to the present invention, a frame synchronization signal (FSC), data clock signal (DCL) between the exchange and the terminal , IOM2 bus unit 10 for relaying downlink transmission data (DDN) and uplink transmission data (DVP), a high frequency clock generator 20 for generating a high frequency clock signal, and a high frequency clock of the high frequency clock generator 20 By the clear signal generation unit 30 for generating a fast-clear signal to the frame synchronization signal (FSC) of the IOM2 bus unit 10 by the high-speed clear signal of the clear signal generation unit 30 The DCL detection unit 40 for detecting the 32nd data clock signal DCL of the IOM2 bus unit 10 and the data clock signal DCL after the high speed clear signal of the clear signal generation unit 30. High frequency cleats The data clock signal (the first counter 50 for counting the clock of the generator 20, the high frequency clock signal of the high frequency clock generator 20 and the high speed clear signal of the clear signal generator 30) Phase velocity control unit 60 having a value one ahead of the number of clocks of the high frequency clock generator 20 after the DCL), the count of the first counter 50 and the 32nd data clock of the specific DCL detector 40. A second counter 70 for counting an average number of clocks of the high frequency clock generator 20 with respect to one data clock signal DCL by detecting the signal DCL, and a count value of the second counter 70. And a comparison unit 80 that compares the preceding values of the phase speed controller 60 and detects one less time than the number of clocks of the high frequency clock generator 20 corresponding to one data clock signal DCL.

The present invention made as described above is as follows.

First, the IOM2 bus unit 10 is a frame synchronization signal (FSC), data clock signal (DCL), downlink transmission data (DDN) and uplink transmission data (DUP) between the exchange and the terminal (or other device in the dec radio base station). The high frequency clock generator 20 generates a high frequency clock signal.

Next, the clear signal generator 30 may be initialized by a reset signal applied from the outside or may be initialized by a high frequency clock of the high frequency clock generator 20 to the frame synchronization signal FSC of the IOM2 bus unit 10. While generating a clear signal, the specific DCL detector 40 detects the 32nd data clock signal DCL of the IOM2 bus unit 10 by the high speed clear signal of the clear signal generator 30.

Subsequently, the first counter 50 counts the clock of the high frequency clock generator 20 during the data clock signal DCL of the IOM2 bus unit 10 after the high speed clear signal of the clear signal generator 30, and phase The speed controller 60 is a high frequency clock generator after the data clock signal DCL of the IOM2 bus unit 10 by the high frequency clock signal of the high frequency clock generator 20 and the high speed clear signal of the clear signal generator 30. It has a value one ahead of the number of clocks in (20).

Then, the second counter 70 is a dada clock signal of the IOM2 bus unit 10 by counting the first counter 50 and detecting the 32 th data clock signal DCL of the specific DCL detector 40. The average number of clocks of the high frequency clock generator 20 for one DCL) is counted.

Next, the comparator 80 compares the count value of the second counter 70 and the preceding value of the phase speed controller 60 to generate a high frequency clock corresponding to one data clock signal DCL of the IOM2 bus unit 10. It detects one less time than the clock number of the unit 20.

As described above, according to the present invention, the phase speed control unit 60 generates a signal having a phase higher than that of the signal based on a specific signal, so that the existing DCL clock alone cannot process the speech coding method having a high speech compression rate. It can be used to generate various gate signals and control signals.

Claims (1)

An IOM2 bus unit 10 for relaying a frame synchronization signal (FSC), a data clock signal (DCL), downlink data (DDN), and uplink data (DUP) between the exchange and the terminal; A high frequency clock generator 20 for generating a high frequency clock signal and a high speed clear signal for the frame synchronization signal PSC of the IOM2 bus unit 10 by the high frequency clock of the high frequency clock generator 20. Clear signal generator 30 and a specific DCL detector 40 that detects the 32nd data clock signal DCL of the IOM2 bus unit 10 by the high speed clear signal of the clear signal generator 30. )Wow ; A first counter 50 for counting the clock of the high frequency clock generator 30 during the data clock signal DCL after the high speed clear signal of the clear signal generator 30: the high frequency clock generator 20 A phase speed control unit 60 having a value that is one ahead of the number of clocks of the high frequency clock generator 20 after the data clock signal DCL by the high frequency clock signal and the high speed clear signal of the clear signal generator 30; : Of the high frequency clock generator 20 with respect to one data clock signal DCL by counting the first counter 50 and detecting the 32nd data clock signal DCL of the specific DCL detector 40. A second counter 70 for counting an average number of clocks; and comparing the count value of the second counter 70 with a preceding value of the phase speed controller 60 to correspond to one data clock signal DCL. Said high frequency clock Apparatus for generating a data clock signal of a deck base station including a comparator (80) for detecting when the number of times less than the clock of the generation unit (20).