KR0137147B1 - Circuit pack for test-connecting inside-line of an exchanger system - Google Patents

Abstract

The present invention relates to a test connection circuit pack for connecting an internal line test bus of an electronic switching system with a measurement module. In particular, one shelf affects another shelf to improve reliability of the test. It relates to an internal line test connection circuit pack in which only one pair of internal test buses is selected to prevent degradation.

The test connection circuit pack of the present invention includes a data receiving unit 10 for receiving board and relay selection 8-bit parallel data D0-D7 from subscriber and relay line test matching boards, and the board selection data D5 and D6. Is a comparator 30 for generating an enable signal by comparing a fixed board address from a back board and a lower 4 bit data D0-D3 from the data receiving unit 10 to select an output. A first and second decoder circuits 16A and 16B, a buffer / driver 40 that receives the radiated signal RDY and outputs a strobe signal, and a selection output signal of the first and second decoders 16A and 16B. A plurality of relay drivers 50A-50D and 50A'-50D 'operated according to the strobe signal, and a plurality of relays connected to each of the drivers and driven by the driver, are used as internal lines of the electronic switching system. city It allows to connect the bus and the measurement module.

Description

Circuit pack for internal line test connection of electronic switching system

1 is a block diagram of a circuit pack for internal test connection of a conventional all-electronic exchange system,

Figure 2 is a block diagram of a circuit pack for the internal line test connection of the electronic switching system according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: data receiving unit 20: semi-automatic

30: comparator 40: buffer / driver

50A to 50D, 50A 'to 50D': Relay driver

16A, 16B: first and second decoder circuits

9: relay

The present invention relates to a test connection circuit pack for connecting an internal line test bus of an electronic switching system with a measurement module. In particular, it affects one shelf or another shelf during the subscriber internal line test, thereby reducing the reliability of the test. An internal line test connection circuit pack is selected so that only the first pair of internal test buses are selected to prevent them.

The electronic switchboard has a function to check the status of the switchboard. In particular, the test equipment for checking the status of a particular subscriber in the switchboard, as well as checking a telephone line problem or a telephone problem, is an internal line test module.

In order to test the internal circuit of the subscriber of the electronic switching system using the internal line test module, a circuit for interfacing each other is required. At this time, when testing the subscriber internal circuit of an electronic switching system, it is necessary to select only one pair of internal test buses so that one shelf does not affect the other shelf and degrade the reliability of the test.

This conventional internal circuit test connection pack is shown in FIG. The test connection pack contains two 8-bit serial-to-parallel converters (S / P) (1A, 1B) for converting 16-bit serial data from the processor in parallel, and a test connection circuit between the strobe signal and the 16-bit data converted in parallel. A latch clock generation circuit 3 that can be stored in the latches 2A / 2B by a combination with the pack control identification data D14, an option circuit 5 selected according to the board mounting slot, and an option circuit 5 Using the lower 6 bits of the relay conversion memory 4 for outputting the relay selection data using the data stored in the latches and the data stored in the latches 2A / 2B as input addresses. Two 4/16 decoders (DEC) 6A, 6B and 2/4 decoder 7 and relay drivers DRV 8A to drive two relays from the outputs of these decoders 6A, 6B and 7 8L) and two relay relays 8A to 8L It consists of the connected relay (9A to 9X).

First, serial 16-bit data applied from a processor is converted into converted data into parallel data by two 8-bit serial / parallel converters 1A and 1B, and then applied to the input of the latch circuit 2.

At this time, the latch clock generation circuit 3 composed of an AND circuit of the strobe signal from the processor and the control identification signal of the test connection circuit pack among the 16-bit parallel data is clocked out of the required 9 bits of the 16-bit latches 2A, 2B).

Decoded 8-bit relay drive data using the 9-bit data output stored in the latches 2A and 2B and the option to select according to the board mounting slot from the option circuit 5 as the address of the relay conversion memory 4. Output to (6A, 6B, 7).

Of the 8-bit relay drive data D0 to D7, four bits of D0 to D3 are applied to the addresses of two 4/16 decoders 6A and 6B and decoded, and at this time, the decoder 6A selected by the combination of D4 and D5. Only 6B) is enabled. D0 and D1 are also applied to the address of the 2/4 decoder 7 and decoded. In this case, the corresponding decoder is exclusively enabled by D6 and D7.

The outputs of the decoders 6A, 6B, and 7 operate one of 20 relay drivers (8A to 8H or 8A 'to 8H', 8I to 8L) capable of driving two relays, respectively, so that the corresponding relay is driven and tested. Connect the in-test bus of the subscriber or relay line to the sideview module.

In the above-described prior art, since the 16-bit serial data is received from the processor, the control circuit is complicated because the parallel / serial conversion unit inside the processor circuit pack and the serial / parallel conversion unit are required in the internal line test connection circuit pack.

In addition, since the relay drive data is converted from the relay conversion memory using the serial / parallel converted parallel data, an expensive EPROM must be used for the relay conversion memory, and a process of programming the EPROM must be added separately.

In addition, it is inconvenient to designate a separate option according to the mounting slot during operation, and it increases the material cost because it uses expensive mercury relays.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a circuit pack for test connection of internal lines of an all-electronic exchange system having a simple structure and low cost.

To achieve the above object, the present invention provides a data receiver for receiving board and relay selection 8-bit parallel data from subscriber and relay line test matching boards, and comparing the board selection data with a fixed board address from a back board. A comparator for generating an enable signal, first and second decoder circuits for receiving low-order 4-bit data from the data receiving unit, and selecting an output, and a buffer / driver for receiving a radial signal RDY and outputting a strobe signal And a plurality of relay drivers operated according to selection output signals and strobe signals of the first and second decoders, and a plurality of relays connected to the plurality of drivers and driven by the drivers. It connects the internal bus test bus of the measuring module with I provides a pack for an internal circuit connected to the line testing of an electronic exchange system for a.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 shows a block diagram of a circuit pack for the internal line test connection of the electronic switching system according to an embodiment of the present invention.

Referring to FIG. 2, the present invention provides a data receiver 10 for receiving incoming board and relay-selected 8-bit parallel data from subscriber and relay line test matching boards, and the board selection denta (D5, D6) from the backboard. A comparator (COMP) 30 for producing the enable signal of the decoder compared to a fixed board address, and an inverter (INV) 20 for selecting one of the two 4/16 decoder circuits 16A, 16B. ) And 4/16 first and second decoder circuits (DEC) 16A, 16B for selecting one of the relay drivers 50A-50D, 50A'-50D ', and decoder circuits 16A, 16B. Relay driver 50A-50D, 50A'-50D 'for driving one of the four relays 9 selected and connected according to the output, and the relay driver is driven so that only the selected relay receives the RDY signal. Strobe Buffer / Driver 40 and 4 for each Relay Driver It consists of several dry relays 9 connected one by one.

According to the present invention configured as described above, the 8-bit parallel data of the board and the relay selection from the subscriber and the relay line test matching board is received by the data receiving unit 10, and the 4-bits of D0 to D3 of the 8-bit parallel data (D0-D7). Data is applied from terminals A0 to A3 of the 4/16 first and second decoder circuits 16A and 16B.

In addition, the D4 data from the receiving unit 10 and the D4 data passing through the inverter 20 are applied to each of the enable terminals EN of the first and second decoder circuits 16A and 16B, and among the 32 relays 9. Decode to run one.

At this time, the comparator 30 compares the D5 and D6 data for determining the mounting slot of the controlling board with the board address from the back board, and enables the 4/16 first and second decoder circuits 16A and 16B to correspond to each other. Only relay the board's board relays.

The relay drive 32-bit data selected by the first and second decoder circuits 16A and 16B are connected to the input terminals of eight relay drivers, four bits each.

At this time, the RDY signal from the subscriber and the relay line matching board strobes the relay driver via the buffer / driver 40 to drive the relay while latching the corresponding data to connect the in-test bus of the subscriber or the relay line with the measurement module. A note performs a function.

Therefore, according to the present invention, since the 8-bit parallel data is directly received from the internal line test matching circuit pack, the parallel / serial conversion unit in the internal line test matching circuit pack and the series / parallel conversion unit in the internal line test connection circuit pack need to be separately. none.

In addition, it is not necessary to access the relay conversion memory using the serial / parallel converted parallel data, thereby eliminating the need for an expensive EPROM and simplifying the process by eliminating the EPROM program process.

In addition, there is no need to specify a separate option according to the mounting slot of the circuit pack, so it is easy to operate, and it is possible to use a low-cost and reliable dry relay, thereby reducing the cost.

Claims (2)

A data receiver 10 for receiving board and relay selection 8-bit parallel data D0-D7 from subscriber and relay line test match boards, A comparator 30 for generating an enable signal by comparing the board selection data D5 and D6 with a fixed board address from a backboard; First and second decoder circuits 16A and 16B for receiving the lower 4-bit data D0-D3 from the data receiver 10 and selecting an output; A buffer / driver 40 that receives the radiated signal RDY and outputs a strobe signal, A plurality of relay drivers 50A-50D and 50A'-50D 'operated according to selection output signals and strobe signals of the first and second decoders 16A and 16B, It is composed of a plurality of relays (9) connected to the plurality of drivers driven by the driver, the internal line of the electronic switchboard system, characterized in that for connecting the test bus with the measurement module. Circuit pack for test connection. 2. An inverter (20) according to claim 1, further comprising an inverter (20) for selecting one of the first and second decoder circuits (16A, 16B) between the data receiver (10) and the second decoder circuit (16B). Circuit pack for the internal line test connection of the electronic switching system.