KR0134290B1 - Apparatus for emboding asynchronous transfer mode layer - Google Patents

Abstract

The present invention relates to an apparatus for implementing an ATM layer suitable for speeding up the processing of an ATM layer. In the conventional technology, since the central processing unit is used, input and output of data becomes very slow, and eventually, ATM layer processing. Although there is a disadvantage in that the speed is lowered, in the present invention, 5 count information is received from the counter 10 in which the selector 20 counts 53 to the transmission buffer 50 without using a central processing unit as in the prior art. By using the header error control signal, the ATM layer processing can be faster overall, and the cost of the device for this can be lowered.

Description

Devices that implement the asynchronous delivery mode layer

Figure is a block diagram illustrating one embodiment of an apparatus implementing an asynchronous delivery mode layer in accordance with the present invention.

* Description of the symbols for the main parts of the drawings *

10: counter, 20: selection unit,

30: buffer control unit, 40: reception buffer,

50: transmission buffer, 60: circuit redundancy check unit,

70: multiplexer

The present invention relates to an apparatus for implementing an asynchronous transfer mode layer (hereinafter referred to as an ATM layer), and more particularly, to an apparatus for implementing an ATM layer suitable for speeding up the processing of an ATM layer.

The AMT layer utilizes Generic Flow Control (GFC) intervals to control access and information flow at the User Network Interface (UN), and the Virtual Path Identifier (VPI) / Virtual Translate and associate a Virtual Channel Identifier (VCI) with Service Access Points (SAPs), multiplex and demultiplex cells, and payload type (PT) It processes the Cell Loss Priority (CLP) intervals and generates and extracts headers of ATM cells. Here, the terms are briefly described as follows.

Subscriber network: The part that connects subscribers with exchanges. Virtual Path Identification Number: To identify cells belonging to the same virtual path among ATM cells. Virtual Channel Identification Number: For identifying cells belonging to the same virtual channel in one virtual path of ATM cells. Multiplexer (MPX): A logic circuit that selects and outputs one from a plurality of input signals according to a designation of a selection signal, or a device or circuit that controls one channel to be used by many devices or circuits. It is often used for connecting low speed I / O and high speed devices.

Paid load type section: A section that indicates whether the payload contents are user information or network information. Cell Abandonment Function: Variable Bit Rate (VBR) services have a variable width in their bit rate and if the moments with the maximum bit rate for variable bit rate services overlap, the network becomes congested. As a way to solve the problem, the cell abandonment function can be used.

That is, for the variable bit rate service, each ATM cell should indicate a priority for cell abandonment in a cell abandonment priority interval, and then give up cells having a lower priority when a congestion occurs. If the cell abandonment priority interval is 1, it is possible to give up, indicating a low priority cell.

In addition, the cell abandonment function must be provided in association with the quality of service determined at the time of establishing a virtual path connection (VPC) / virtual channel connection (VCC), i.e., at least assured bit rate after the cell abandonment process. It should be possible to provide a certain quality of service.

Therefore, the network should determine the bit rate of the high-priority cells when establishing the connection and make it possible to renegotiate it even after the connection, and the network controls whether the number of cells in the connection exceeds that negotiated. When cell traffic exceeds the negotiated level, the network may ignore the cell even if the cell abandonment priority is assigned to a high priority.

ATM cell: In a broadband integrated telecommunications network (BISDN), information is conveyed by a continuous flow of packets of constant size, which is called an ATM cell, and the size of an ATM cell is 53 bytes. It is divided into a byte header and 48 bytes of payload space.

ATM cell header: For identifying cells belonging to the same virtual channel among ATM cells present in the asynchronous time division multiplexing (ATDM) information flow, and identifying the cells using the virtual path identification number and the virtual channel identification number.

In this case, the virtual path refers to a bundle of virtual channels sharing a certain path, the AMT cell header distinguishes other payload types, indicates cell abandonment ranking, and header error control (HEC) function. To provide. In addition, at the user network interface, general flow control is added to the cell header.

In this regard, the conventional ATM layer implements the ATM layer using a Central Processisng Unit (CPU). In this conventional technique, the central processing unit is very slow to input and output data. As a result, there is a drawback that the ATM layer processing speed is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described drawbacks, and an object thereof is to provide an apparatus for implementing an ATM layer capable of quickly processing an ATM layer without a central processing unit.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for achieving the above object is as follows.

Referring to the accompanying drawings, the accompanying drawings are block diagrams illustrating an embodiment of an apparatus for implementing an ATM layer according to the present invention, and the upper layer stores 52 bytes including a 4-byte cell header in the reception buffer 40. A counter 10 that receives 53 signals and receives a count signal when both signals are written and transmitted, and outputs a detection signal for selecting a header error control signal when the count signal of the counter 10 is 5 counts. A signal from the buffer control unit 30 and the buffer control unit 30 for receiving a signal from the selection unit 20, the signal from the selection unit 20, and outputting a signal for controlling each buffer according to the count value of 5. A reception buffer 40 for receiving upper layer data, a transmission buffer 50 for receiving an signal from the buffer control unit 30, and transmitting an ATM cell signal including a header error control signal in a fifth byte; The upper layer of the buffer 40 The cyclic redundancy check (CRC) and the cyclic redundancy check unit 60 to output the header error control signal, and the signal from the selection unit 20 to receive higher layer data of the reception buffer 40. The multiplexer 70 writes the header error control signal of the circular redundancy check unit 60 when the count value is 5 while writing to the transmission buffer 50.

According to the present invention, the counter 10 first receives a signal when the upper layer writes and transmits 52 bytes including a 4-byte cell header to the ATM layer, that is, the reception buffer 40. 53 counts, and the selector 20 receives the count signal of the counter 10 and transmits a detection signal for selecting a header error control signal to the buffer controller 30 and the multiplexer 70 when the count is 5 counts. Print each.

In this case, the counter 10 counts 53 because the ATM cell has a total of 53 bytes including 5 bytes of header and 48 bytes of payload space.

Next, the buffer controller 30 receives the signal from the selector 20 and controls each of the reception and transmission buffers 40 and 50 according to the count value of 5, so that the reception buffer 40 of the buffer controller 30 Receives a control signal and outputs the upper layer data stored at first, and the transmit buffer 50 receives the control signal of the buffer controller 30 and transmits an ATM cell signal including a header error control signal in the fifth byte. do.

That is, the circuit redundancy check unit 60 receives the higher layer data of the reception buffer 40 and outputs the header error control signal by performing the circuit redundancy check, and the multiplexer 70 receives the signal of the selector 20 and receives the signal. The upper layer data of the buffer 40 is written to the transmission buffer 50, and when the count value is 5, the header error control signal of the cyclic redundancy check unit 60 is written.

Therefore, the header error control signal consisting of one byte is inserted into the fifth byte of the header consisting of five bytes in the ATM cell consisting of 53 bytes.

As described above, in the present invention, the header error control signal is transmitted to the transmission buffer 50 by receiving 5 count information from the counter 10 counted by the selector 20 without using a central processing unit as in the conventional art. In addition, the ATM layer processing is faster overall, and the cost of the device is lowered.

Claims (1)

A counter 10 which receives 53 signals when the upper layer writes and transmits all 52 bytes including the 4-byte cell header to the reception buffer 40; A selection unit 20 receiving a count signal of the counter 10 and outputting a detection signal for selecting a header error control signal of 1 byte when the count is 5 counts; A buffer controller 30 which receives the signal of the selector 20 and outputs a signal for controlling each buffer when the count value is 5; A reception buffer 40 for receiving a signal from the buffer controller 30 and outputting upper layer data; A transmission buffer 50 receiving the signal from the buffer control unit 30 and transmitting an ATM cell signal including a header error control signal in a fifth byte; A cyclic redundancy check unit (60) which receives the higher layer data of the reception buffer (40) and outputs a header error control signal by performing cyclic redundancy check; Multiplexing the upper layer data of the reception buffer 40 to the transmission buffer 50 by receiving the signal of the selection unit 20 and writing the header error control signal of the circuit redundancy check unit 60 when the count value is 5 Apparatus for implementing an asynchronous delivery mode layer comprising a section (70).