KR0132949B1 - Network interfacing apparatus for atm network with multi - Google Patents

Abstract

The present invention relates to an asynchronous delivery mode (ATM) network matching device for simultaneous processing of multi-channel traffic, and receives CBR (Constant Bit Rate) traffic from the outside and outputs CBR traffic according to a token signal indicating the time point of use of the bus. A plurality of first matching means 11 for receiving CBR traffic and outputting the same to its own header address; and receiving VBR (Variable Bit Rate) traffic from the outside and receiving VBR traffic from the outside; An R-connection point interface module 10 composed of a plurality of second matching means 12 for outputting to the R-connection point; A multiplexed traffic bus (MT-bus) connected to the plurality of first matching means (11) to provide a fixed bandwidth for transmitting CBR traffic and to multiplex and transmit multiple channels; A system bus connected to the plurality of first and second matching means (11, 12) to transmit VBR traffic of the second matching means (12) and to transmit a resource control signal of the system; And outputting a token signal to the first matching means 11 to transmit the CBR traffic received through the MT-bus to an Asynchronous Transfer Mode (ATM) network, and transmitting the CBR traffic received from the ATM network to the MT-bus. Outputs to the plurality of first matching means 11, transmits VBR traffic input from the plurality of second matching means 12 through a system bus to an ATM network, and transmits VBR traffic received from the ATM network to the system. It is equipped with an ATM network interface module (ANI) 20 which outputs to the plurality of second matching means 12 via a bus and simultaneously processes multi-channel traffic CBR or VBR to build a multimedia communication environment that is emerging. Broadband has the effect of efficiently using the expensive line of the characteristic.

Description

Asynchronous delivery mode network matching device for simultaneous processing of multi-channel traffic

1 is a schematic overall configuration diagram of a broadband terminal matching device according to the present invention;

2 is a detailed configuration diagram of a temporary example of a broadband terminal matching device according to the present invention;

3 is a detailed configuration diagram of the MT-bus interface according to the present invention;

4 is a detailed configuration diagram of the MT-bus management unit according to the present invention,

5 is a conceptual diagram illustrating a section in which CBR and VBR traffics are mixed and serviced within a period time according to the present invention;

6 is an MT-bus signal timing diagram according to the present invention;

7 is a signal timing diagram of the MT-bus interface according to the invention.

* Explanation of symbols for main parts of the drawings

10: R connection point interface device 11: Matching part

20: ATM network interface device 21: MT bus management unit

23: Packet memory section 24: ATM processor section

25: ATM physical layer unit 110: CBR interface

111: MT-bus interface 112, 121, 22: system bus interface

120: VBR interface

The present invention relates to an Asynchronous Transfer Mode (ATM) network matching device applied to a broadband terminal matching device (B-TA) and a broadband terminal device (B-TE) constituting a broadband integrated information communication network (B-ISDN). In particular, the present invention relates to an ATM network matching device capable of simultaneously supporting a multi-channel fixed bit rate (CBR) and a variable bit rate (VBR).

The conventional ATM network matching device, which is designed for use in a broadband terminal matching device (B-TA) and a broadband terminal device (B-TE), is configured to accommodate only a single type of traffic (CBR or VBR).

Therefore, it is not possible to accommodate complex traffic such as voice and video data, and it is difficult to construct a multimedia communication environment that is emerging in recent years, and there is an inefficient problem of not being able to efficiently use a high-priced line of broadband.

Accordingly, the present invention has been made in order to solve the problems of the prior art, there is a need for an ATM network matching device that can accommodate traffic in combination, a terminal matching device or a terminal device requiring a broadband ATM matching function The purpose of the present invention is to provide an ATM network matching device capable of simultaneously processing multi-channel traffic for application to a host computer (including a host computer).

In order to achieve the above object, the present invention receives CBR (Constant Bit Rate) traffic from the outside and outputs the CBR traffic according to the token signal indicating the time of use of the bus, or receives the CBR traffic and receives the same CBR traffic as its header address. R-access point interface comprising a plurality of first matching means for outputting this to the outside and a plurality of second matching means for receiving and outputting variable bit rate (VBR) traffic from the outside or receiving and outputting VBR traffic to the outside. A multiplexed traffic bus (MT) bus coupled to the plurality of first matching means to provide a fixed bandwidth for transmitting CBR traffic and to multiplex and transmit multiple channels; A system bus connected to a second matching means to transmit VBR traffic of the second matching means, and to transmit a resource control signal of the system; A token signal is output to a first matching means to transmit CBR traffic received through the MT-bus to an ATM (Asynchronous Transfer Mode) network, and CBR traffic received from an ATM network is transmitted through the MT-bus. Outputs to the first matching means, transmits the VBR traffic inputted from the plurality of second matching means through a system bus to an ATM network, and sends the VBR traffic received from the ATM network to the plurality of second matching means through a system bus. ATM network interface module (ANI) for outputting means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a schematic overall configuration diagram of a broadband terminal matching device according to the present invention. In FIG. 10, an existing local area network (LAN), a frame relay, an integrated information network (ISDN), and a phone are shown. Or an R-connection point interface device (RIF) consisting of n matching units capable of connecting a video phone (Videl phone) and the like, and 20 denotes an ATM network interface (ANI) for connection with a broadband ATM network. Indicates.

When connected to a LAN or a frame relay network, the R-access point interface device 10 receives VBR traffic of an ATM Adaptation Layer (AAL) Type 1/3/4/5 type, and receives an ISDN phone. When connecting to a video phone or the like, ABR 1 receives CBR traffic.

The ANI 20 implements the ATM layer and physical layer protocols of the ITU-T Recommendation B-ISDN reference model, and has Q.2931 and QSAAL signaling interfaces and AAL 1/3/4/5. User interface, hierarchical management, and plan management functions are performed. That is, the B-ISDN and User Network Interface (UNI) protocols are performed, and a matching function for ATM network communication of various traffics of the R-access point interface device 10 is performed. .

Multiplexed traffic bus (MT-bus) is a means to multiplex multiple channels while guaranteeing real-time bandwidth of CBR to simultaneously accommodate multi-channel CBR and VBR traffic through ATM network. Is located between the matching portion of the R-connection point interface device 10 and the ATM network interface device (ANI) 20.

The MT-bus includes a token input / output signal, a transmission data enable signal (TDEN) that is a transmission data validity time indication signal, a transmission data clock signal (TDCLK) that is a transmission data synchronization clock, and transmission data in bytes or words ( TD0 to TD7 (15), the received data enable signal RDEN which is the received data valid period display signal, the received data clock signal RDCLK that is the received data synchronization clock signal, and the received data in bytes or words ( RD0 to RD7 (15) transmits and receives a reception related signal group.

Accordingly, the MT-bus is a full-duplex parallel bus type in which a transmission signal and a reception signal are separately provided, and may be written in byte width or word width, and the transmission signal is transmitted from the R-junction interface device 10 to the ANI 20. It refers to a signal and operates in the limit-1 service method by token input / output signals.

In addition, the received signal refers to a signal transmitted from the ANI 20 to the R-connection point interface device 10, and takes a broadcasting method, and each matching part of the R-connection point interface device 10 has headfield information. Only the data with its own address is received through the filter.

Since VBR traffic is non-real time, it is configured through a system bus (eg, VMEbus) having an arbitration device suitable for more non-real time packet type service, rather than through an MT-bus. At this time, the system bus simultaneously serves as a passage through which the R-access point interface device 10 controls resources in the system such as the matching unit and the ANI 20 in the main control unit, which is an original task.

2 is a configuration diagram of an embodiment of a broadband terminal matching device according to the present invention, 11 is a matching unit, 110 is a CBR interface, 111 is an MT-bus interface, 112, 121, 22 is a system bus interface, 120 is A VBR interface, 21 represents an MT-bus management unit, 23 represents a packet memory unit, 24 represents an ATM processor unit, and 25 represents an ATM physical layer unit.

The R-access point interface device 10 includes a plurality of first matching units 11 transmitting constant bit rate (CBR) traffic and a plurality of second matching units 12 transmitting variable bit rate (VBR) traffic. do.

The first matching unit 11 is connected to the CBR interface 110, the CBR interface 110 for receiving and outputting CBR traffic from the outside or outputting the received CBR traffic to the outside, the ATM network interface device (ANI) MT-bus interface 111 for outputting the CBR traffic through the MT-bus according to the token signal input from the) 20, and outputs the CBR traffic received through the MT-bus to the CBR interface 110, and It is composed of a system bus interface 112 connected to the system bus to perform resource control.

The second matching unit 12 is a VBR interface 120 for transmitting and receiving VBR traffic with the outside, and a system bus interface connected to the VBR interface 120 and a system bus to transmit and receive VBR traffic or to perform resource control ( 121). An ATM network interface device (ANI) 20 outputs a token signal indicating a CBR traffic transmission time point to the first matching unit 11, and MT-bus management unit 21 for transmitting and receiving CBR traffic through an MT-bus, A system bus interface 22 connected to a system bus to transmit or receive VBR traffic, a packet memory unit 23 connected to the system bus interface 22 to store VBR traffic, and the MT-bus The CBR traffic stored in the management unit 21 is processed first, and if there is no CBR traffic to process, it is connected to the ATM processor unit 24 that processes the VBR traffic stored in the packet memory unit 23, and the ATM processor unit 24. It consists of an ATM physical layer 25 to perform the function of the ATM physical layer.

The token input / output signal is output from the MT bus management unit 21 of the ANI 20 and is extinguished from the MT bus management unit 21 via the MT bus interface 111.

The CBR traffic transmitted through the MT-bus is stored in the ANI transmit FIFO in the MT-bus management unit 21, and the VBR traffic transmitted through the system bus is stored in the packet memory unit 23 and is transferred from the ATM processor unit 24. Is processed.

At this time, the ATM processor 24 processes the ANI transmit FIFO with priority in order to process CBR traffic in real time, and performs two-step priority processing of serving the packet memory unit 23 only when the ANI transmit FIFO is empty. .

3 shows a detailed block diagram of the MT-bus interface (111 in FIG. 2) according to the present invention.

When the MT-bus interface 111 receives CBR traffic from the CBR interface 110, the MT-bus interface 111 stores and outputs the CBR traffic, and inverts the transmission ready signal from the transmission FIFO 31. A latch 32 for latching and outputting a token input signal at a point in time at which a token input signal is received, a first OR gate 33 for outputting a bus occupied signal by ORing the output of the latch 32 and the token input signal; A delay unit 34 for delaying output and a second AND gate 35 for ORing the inverted output of the first AND gate 33 and the delayed output of the delay unit 34 to output a token output signal; Counter 36 counts the output of the transmission FIFO 31 and outputs a transmission completion signal to the latch 32 when all transmissions are performed, and buffers the CBR traffic stored in the transmission FIFO 31 through the counter 36. The first logical sum A receiving buffer 37 for outputting to the MT bus by the bus occupied signal of the gate 33, a receiving buffer 38 for buffering and outputting CBR traffic received from the MT-bus, and a head from the receiving buffer 38. The head field checker 39 outputs a reception control signal signal for receiving CBR traffic stored in the reception buffer 38 and the output of the reception buffer 38, if the field is input and the head is inspected. A reception FIFO 40 is stored and output by the reception control signal of the head field inspector 39.

Looking at the operation of the MT-bus interface configured as described above with reference to Figure 7, first, the transmission process is as follows.

When CBR traffic is input from the CFI interface 110, the transmission FIFO 31 outputs a transmission ready signal as shown in FIG. 7 indicating that there is data to be transmitted.

The latch 32 latches and outputs a transmission ready signal of the transmission FIFO 31 when the inverted token input signal Token IN is input through the inverter 41.

The first AND gate 33 performs an OR on the output of the latch 32 and the input token input signal to output a bus occupancy signal OWN to the transmission buffer 37, and further to the first AND gate 33. The output is input to the second AND gate 35 through the inverter 42. That is, as shown in FIG. 7, the bus occupied signal is output while both the transmission ready signal and the token input signal are active 'low'.

Meanwhile, in order not to output a token output signal (Token OUT) until one cell is transmitted, one cell transmission enables the counter 36 to detect the completion of transmission using a cell byte counter.

The counter 36 generates a transmission completion signal and outputs it to the latch 32 when the cell stored in the transmission FIFO 31 is completed.

The latch 32 is cleared by the transfer completion signal of the counter 36 to release the bus occupied signal OWN, and a signal obtained by inverting the output of the first AND gate 33 through the inverter 42. And the token input signal delayed through the delay unit 34 through the second logical sum gate to output the token output signal, which becomes the token input signal, to the next MT-bus interface 111 as an active 'low'.

Next, referring to the reception process, the traffic received from the ATM physical layer transmission line is processed through the ATM processor, and the CBR is stored in the ANI reception FIFO of the MT-bus management unit 21 and the VBR is stored in the packet memory unit 23.

When a cell is completely stored in the ANI receive FIFO, the receive signal of the MT-bus is activated, and the receive buffers 38 of all MT-bus interfaces 111 receive this signal.

The head field checker 39 receives the head information from the output of the reception buffer 38 and outputs a reception control signal to the reception FIFO 40 if the address information stored in the head information is its destination cell, and outputs it from the reception buffer 39. Outputs the stored CBR traffic.

Since VBR traffic is transmitted and received using a general system bus-based message communication technique, description thereof is omitted.

4 shows a detailed configuration of the MT-bus management unit (21 in FIG. 2) according to the present invention.

The MT-bus management unit 21 receives and stores CBR traffic from the token signal generator 50 generating and outputting the token signal, the monitor 51 monitoring the circulation cycle of the token signal, and the ATM processor unit 24. A reception FIFO 52, a reception buffer 53 for buffering and outputting the output of the reception FIFO 52, a transmission buffer 54 for buffering and outputting CBR traffic transmitted from the MT-bus, and the transmission buffer ( 54 is composed of a transmission FIFO 55 which receives the output of 54) and outputs state information and CBR traffic to the ATM processor unit 24.

The token generator 50 circulates through the timer 56 generating the token start pulse at a predetermined cycle and the violation signal input from the monitor 51 and the token input signal circulated through the MT-bus interface 111. A flip-flop that receives an AND gate 57 for outputting a clear signal and a token start pulse of the timer 56 to a clock terminal, outputs a token signal, and is cleared by the clear signal of the AND gate 57. It consists of 58.

Token generator 50 is responsible for the generation and destruction of the token, the value of the number of the first matching unit 11 multiplied by the traffic bandwidth per first matching unit 11 is the physical layer transfer bit rate of the ATM network interface device 20 A token start pulse is generated in the timer 56 at a cycle time T that is faster than 1 / maximum traffic bandwidth under the condition of less than (Physical Transmission Bit Rate).

The token start pulse of the timer 56 is input to the clock terminal of the flip flop 58 so that the flip flop 58 outputs the token output signal to the MT-bus interface 111.

When the token input signal is input to the AND gate 57 through all MT-bus interfaces 111, the token is destroyed by deactivating the token output signal because the CBR service of one cycle is completed.

The monitor 51 for monitoring the cycle cycle monitors when the token does not return for more than a predetermined threshold time, forcibly releases the token signal and provides real time and bandwidth guarantees to the CBR traffic.

The ATM processor unit 24 of the ANI 20 first processes the CBR traffic and the VBR traffic so that real-time CBR traffic is processed first, and the VBR traffic is used only during the spare time. To this end, the token output signal generated from the token generator 50 is input to the VBR service prohibition signal indicating that the CBR period is input to the ATM processor unit 24 to prohibit the VBR service. CBR traffic received from the ATM processor unit 24 is input to the reception FIFO 52 and output to the MT-bus through the reception buffer 53, and the CBR traffic transmitted from the MT-bus transmits the transmission buffer 54. It is stored in the transmission FIFO 55 and output to the ATM processor unit 24 along with the status information.

5 is a conceptual diagram showing a section in which CBR and VBR traffic are mixed and serviced within a cycle time. One cycle is divided into a CBR section and a VBR section. If less, the utilization rate can be increased by allocating bands to VBR traffic.

6 illustrates a transmission data enable signal TKEN, a transmission data clock TDCLK, and transmission data TD0 to TD7 that are MT-bus signals when the first matching unit 11 acquires a token and transmits one CBR traffic. The timing diagrams of the transmission-related signal of the " 15 ", the reception data enable signal RDEN, the reception data clock RDCLK, and the reception-related signals of the reception data RD0 to RD7 15 are shown.

7 is a signal timing diagram of the MT-bus interface 111 in each first matching section 11 upon activation of the token input / output signal.

According to the present invention, the multi-channel traffic CBR or VBR is simultaneously processed to build a multimedia communication environment that is emerging in recent years, thereby bringing an effect of efficiently using expensive circuits.

Claims (9)

A plurality of first outputting CBR (Constant Bit Rate) traffic from the outside and outputting CBR traffic according to the token signal indicating the time of use of the bus, or receiving CBR traffic and outputting the same if it is the same as its header address. R-connection point interface module 10 comprising a matching means 11 and a plurality of second matching means 12 for receiving and outputting variable bit rate (VBR) traffic from outside or receiving and outputting VBR traffic to the outside. ; A multiplexed traffic bus (MT) bus coupled to the plurality of first matching means (11) to provide a fixed bandwidth for transmitting CBR traffic and to multiplex and transmit multiple channels; A system bus connected to the plurality of first and second matching means (11, 12) to transmit VBR traffic of the second matching means (12) and to transmit a resource control signal of the system; And outputting a token signal to the first matching means 11 to transmit the CBR traffic received through the MT-bus to an Asynchronous Transfer Mode (ATM) network, and transmitting the CBR traffic received from the ATM network to the MT-bus. Outputs to the plurality of first matching means 11, transmits VBR traffic input from the plurality of second matching means 12 through a system bus to an ATM network, and transmits VBR traffic received from the ATM network to the system. ATM network interface module (ANI) (20) for outputting to said plurality of second matching means (12) via a bus, characterized in that the asynchronous transfer mode (ATM) network matching device for multi-channel simultaneous processing. According to claim 1, The first matching means 11, CBR interface means 110 for receiving and outputting CBR traffic from the outside or outputting the received CBR traffic to the outside; It is connected to the CBR interface means 110 and outputs the CBR traffic through the MT-bus according to the token signal input from the ATM network interface module (ANI) 20, and the CBR traffic received via the MT-bus MT-bus interface means 111 for outputting to CBR interface means 110; And a system bus interface means (112) connected to the system bus to perform resource control. 2. The ATM network interface module (ANI) 20 according to claim 1, outputs a token signal indicating a transmission time of CBR traffic to the first matching means 11, and transmits and receives CBR traffic through an MT-bus. MT-bus management means 21; System bus interface means 22 connected to the system bus to transmit and receive VBR traffic or to transmit and receive resource control signals; A packet memory means (23) connected to said system bus interface means (22) for storing VBR traffic; ATM processor means (24) for first processing CBR traffic stored in the MT-bus management means (21) and processing VBR traffic stored in the packet memory means (23) if there is no CBR traffic to process; And an ATM physical layer means (25) connected to said ATM processor means (24) to perform the function of an ATM physical layer. 2. The apparatus of claim 1, wherein the second matching means (12) comprises: VBR interface means (120) for transmitting and receiving VBR traffic with an outside; And a system bus interface unit 121 connected to the VBR interface unit 120 and a system bus to transmit / receive VBR traffic or perform resource control. Network matching device. According to claim 2, MT-bus interface means (111), CBR traffic received from the CBR interface means 110, storing and outputting it, and a transmission FIFO (31) for outputting a transmission ready signal; A latch (32) for latching and outputting a transmission ready signal from the transmission FIFO (31) at the time point at which the inverted token input signal is received; A first AND gate 33 for ORing the output of the latch 32 and the token input signal to output a bus occupied signal; A delay unit 34 for delaying and outputting the token input signal; A second AND gate 35 for ORing the inverted output of the first AND gate 33 and the delayed output of the delayer 34 to output a token output signal; A counter (36) for counting the output of the transmission FIFO (31) and outputting a transmission completion signal to the latch (32) when all are transmitted; A transmission buffer (37) for buffering the CBR traffic stored in the transmission FIFO (31) through the counter (36) and outputting it to the MT-bus by the bus occupied signal of the first logical sum gate (33); A reception buffer 38 for buffering and outputting CBR traffic received from the MT-bus; A head field checker (39) for receiving a head field from the receive buffer (38) and inspecting the head and outputting a reception control signal signal for receiving CBR traffic stored in the receive buffer (38) if it is its destination cell; And a reception FIFO 40 for storing and outputting the output of the reception buffer 38 by the reception control signal of the head field inspector 39. Network matching device. 6. The apparatus as claimed in claim 5, further comprising: first inverting means (41) for inverting a token input signal and outputting it to the latch (32); And a second inverting means 42 for inverting the output of the first AND gate 33 and outputting the second OR gate 35 to the second OR gate 35. ) Network matching device. 4. The apparatus of claim 3, wherein the MT-bus management means (21) comprises: a token signal generator (50) for generating and outputting a token signal; A monitor 51 for monitoring a cycle of token signals; A reception FIFO (52) for receiving and storing CBR traffic from the ATM processor means (24); A reception buffer 53 for buffering and outputting the output of the reception FIFO 52; A transmission buffer 54 for buffering and outputting CBR traffic transmitted from the MT-bus; And a transmission FIFO (55) for receiving the output of the transmission buffer (54) and outputting status information and CBR traffic to an ATM processor (24). Network matching device. 8. The token generator of claim 7, wherein the token generator comprises: a timer (56) for generating a token start pulse at regular intervals; A logical AND gate 57 which circulates through the MT-bus interface means 111 and outputs a clear signal by ANDing the token input signal inputted from the violation signal inputted from the monitor 51; And a flip-flop 58 which receives a token start pulse of the timer 56 at a clock terminal, outputs a token signal, and is cleared by a clear signal of the AND gate 57. Asynchronous delivery mode (ATM) network matching device for simultaneous processing. The ATM network interface module of claim 8, wherein the token generation period of the timer 56 is obtained by multiplying the number of the first matching means 11 by the traffic bandwidth per first matching means 11. An asynchronous transfer mode (ATM) network matching device for multi-channel simultaneous processing, characterized in that a cycle time (T) faster than 1 / maximum traffic bandwidth under the condition that the physical transmission bit rate is less than.