KR0132483B1 - Data retrieving circuit for digital magnetic recording/reproducing system - Google Patents

Abstract

A data selection circuit for a digital magnetic record reproduction system includes: a three-value judgement part for performing a three-value judgement about an input signal; a pulse-width voltage converter for converting an output signal of the three-value to a voltage; a pulse width judgement part for comparing an output of the pulse width voltage converter with a set comparison level, and outputting a signal indicating a pulse of a specific width; a delay part for delaying a data output of the three-value judgement part for a processing period of both the pulse width voltage converter and the pulse width judgement part; and a data output part which makes the data from the delay part be synchronized to a clock by using an output signal of the pulse width judgement part. Accordingly, the data selection circuit deteremines whether the output signal of a comparator of the data selection part is T-width pulse or 2T-width pulse, accurately transmits the T-width pulse or the 2T-width pulse as an output terminal of the data selection part, thereby achieving an accurate data selection.

Description

Data Extraction Circuit of Digital Magnetic Recording & Reproduction System

1 is a block diagram of a conventional digital magnetic recording and reproducing system.

2 is a detailed circuit diagram of the data extraction unit of FIG.

3A is a detailed circuit diagram of the clock component extracting section of FIG.

3B is a waveform diagram of each part of the clock component extracting unit.

4 is a block diagram of a data extraction circuit of the digital magnetic recording and reproducing system according to the present invention.

FIG. 5 is a detailed configuration diagram of the pulse width voltage converter of FIG. 4. FIG.

6 is a detailed block diagram of the pulse width determining unit of FIG.

7 (a) to (c) are waveform diagrams of respective parts of the pulse width voltage converter of FIG.

8 is a comparative level explanatory diagram of the pulse width determining unit of FIG. 6;

* Explanation of symbols for main parts of the drawings

11: 3-valued judgment unit 12: pulse width voltage conversion unit

12a: switching section 12b: data holding section

13 pulse width determination unit 14 delay

15: data output unit

The present invention relates to a data extraction circuit of a digital magnetic recording and reproducing system, and more particularly, to determine whether an input is a T width pulse or a 2 T width pulse based on a comparison output between an input and a comparison level. A data extraction circuit of a digital magnetic recording and reproducing system is made.

FIG. 1 shows a block diagram of a reproduction portion of a general digital magnetic recording / reproducing system, which includes a magnetic recording medium 1, a reproduction amplifier 2, an equalizer 3, a data extractor 4, and a clock component. The extractor 5, the phase comparator 6, the loop filter 7, the voltage controlled oscillator (hereinafter referred to as VCO) 8, and the latch 9 are composed of.

Since the output of the magnetic recording medium 1, i.e., the disk or the tape, is a small signal, the frequency characteristic is corrected through the equalizer 3 after being amplified by the reproduction amplifier 2.

The output of the equalizer 3 is input to the data extraction section 4, and the ternary determination is performed by the comparators COMP1, COMP2 and OR gate OR1 of FIG.

That is, the comparator COMP1 compares the input level with the comparison level TH1 determined by the variable resistor VR1, and in the comparator COMP2 the input is inverted by the inverter INV1 and the variable resistor VR2. The comparison level TH2 determined by P is compared and then is ORed at the OR gate OR1 to be output.

If the input of the comparator COMP1 is smaller than the comparison level TH1, the output of the comparator COMP1 becomes high and vice versa because the value of the non-inverting input terminal (+) is greater than that of the inverting input terminal (-). Goes low.

Also, the comparator COMP2 also has a high output when the value of the inverting input terminal (-) is smaller than that of the non-inverting input terminal (+) and goes low when the output of the comparator CMOP1 is inserted high. When the output of the comparator COMP1 goes low, the comparator COMP2 outputs high by the inverter INV1. Therefore, the output of the OR gate OR1 becomes 1 when the input is ± 1.

That is, the data extraction section 4 has a three-value determination circuit as shown in FIG. 2 and outputs ± 1 as 1 and 0 as 0. FIG.

The output of the data extractor 4 is inputted to the clock component extractor 5, and is delayed by a half cycle of the clock in the delay unit 5a of FIG. 3a, through a clock component EX-OR1. Is extracted.

That is, in FIG. 3B, (a) is the output of the data extraction section 4, (b) is the output of the delay section 5a, and (c) is the output of the exclusive OR gate EX-OR1. It can be seen that the clock component is obtained.

In the region where the output of the clock component extractor 5 is high, the output of the VCO 8 and the phase comparator 6 are phase-compared, and then filtered by the loop filter 7 and then the loop filter 7. The output controls the frequency and phase of the VCO 8, latches the data to the latch 9 with a clock that is the output of the VCO 8, and outputs the final data.

However, the conventional data extraction as described above appears in the output of the comparator when the input is amplitude-changed or there is jitter in time due to the comparison operation of the comparator by the fixed comparison level. It becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to determine whether an input is a T width pulse or a 2T width pulse according to a comparison output of an input of a data extraction section and a comparison level wave, and accurately output the T width to an output of the data extraction section. The present invention relates to a data extraction circuit of a digital magnetic recording / reproducing system that outputs a pulse or a 2T wide pulse so that clock recovery and data extraction can be performed accurately.

Features of the present invention for achieving this object are three-value determination means for three-value determination of the input signal, pulse width voltage conversion means for converting the output pulse of the three-value determination means into a voltage, and the pulse width voltage conversion means Processing period of the pulse width voltage converting means and the pulse width determining means for outputting a signal indicating that the pulse is a specific width by comparing the output of the signal with a predetermined comparison level; A data extracting circuit of a digital magnetic recording / reproducing system, comprising: delay means for delaying and delay, and data output means for synchronizing and outputting data from the delay means to the output of the pulse width determining means.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described in detail.

First, the overall configuration diagram of the digital magnetic recording / reproducing system according to the present invention is the same as in the prior art, and only the data extraction section has a configuration different from that in the prior art as shown in FIG.

It comprises a three-valued judgment unit 11 for determining the input signal in three values, a pulse width voltage conversion unit 12 for converting the output pulses of the three-value determination unit 11 into voltage, and the pulse width voltage conversion unit 12. A pulse width determining unit 13 for outputting a T width pulse or a 2T width pulse by judging whether the output is a T width pulse or a 2T width pulse, and the pulse width voltage converting unit 12 and the pulse width determining unit 13 A delay unit 14 for delaying the output of the three-level determination unit 11 during the processing period, and a T width that is exactly the output of the pulse width determination unit 13 in synchronization with a clock. It consists of a data output part 15 which outputs the data of a pulse or a 2T width pulse.

The three-level plate 11 is configured in the same manner as in the prior art and uses the same reference numerals as in the conventional art.

The pulse width voltage converter 12 includes an inverter INV11 for inverting an input signal, a switching unit 12a switched according to an output of the inverter INV11, and the switching as shown in FIG. A capacitor? C1 charged and discharged in accordance with the output of the unit 12a, and a data hold unit 12b that outputs the charging voltage of the capacitor C1 at all times at the falling edge of the output of the inverter INV11.

The switching unit 12a is turned on when the output of the inverter INV11 is low so that the capacitor C1 is charged, and turned on when the output of the inverter INV11 is high, and the capacitor C1 is turned on. NMOS (N1) that provides a discharge passage of ().

As shown in FIG. 6, the pulse width determining unit 13 includes comparators COMP11-COMP14 having different comparison levels TH11 to TH14 determined by the variable resistors VR11 to VR14, and the comparator. AND gate AND11 for outputting 2T width pulses by ANDing the outputs of (COMP11) and (COMP12), and AND gate (AND12) outputting T width pulses by ANDing the outputs of the comparators (COMP13) and (COMP14). It consists of.

In the present invention configured as described above, the three-valued judgment unit 11 outputs ± 1 as 1 and 0 as 0 as in the related art, which is input to the pulse width voltage converter 12 and converted into a voltage value. Will be output.

That is, when the input of the pulse width voltage converter 12 is high, the output of the inverter INV11 goes low, so that the PMOS P1 is turned on and the NMOS N1 is turned off to charge the capacitor C1.

When the input is low, the output of the inverter INV11 becomes high, so the PMOS P1 is turned off and the NMOS N1 is turned on so that the capacitor C1 starts discharging through the NMOS N1 and is inputted. The data holding part 12b operates at the falling edge of the data waveform so that the charge-filled charge in the capacitor C1 is outputted to the pulse width determining part 13.

That is, when the input of the inverter INV11 is equal to (a) in FIG. 7, the waveform diagrams of nodes (a) and (b) are as shown in FIG. When the voltage of is held in the data holding unit 12b and the next voltage is input, the held value is output, and the output of the held value is controlled by the output signal line of the inverter INV11.

The output of the pulse width voltage converting section 12 is input to the pulse width determining section 13 to determine whether the input is a T width pulse or a 2T width pulse, and the pulse width determining section 13 uses a magnetic recording method. According to T width pulse, 2T width pulse, The reference value is set as a reference value, and if the input is a signal close to the T width pulse, the T width pulse is output.

In the present invention, only the case of T width and 2T width will be described as an example.

Therefore, four comparators of the pulse width determining unit 13 are used, and the comparison level (TH11-TH14) of each of the comparators (COMP11-COMP14) is acceptable in the case of a T width pulse and a 2T width pulse. The resistance is determined by the variable resistors VR11-VR14.

Here, the allowable error means a range value that can be recognized as a 2T pulse or a T width pulse even if the inputs are not 2T width pulses or T width pulses as shown in FIGS. 8A and 8B.

When the input of the pulse width determiner 13 is smaller than the comparison level TH13 of the comparator COMP13, the outputs of the comparators COMP11 and COMP12 are high and low, respectively, and the comparators COMP13 and COMP14. The outputs of and are low and high, respectively, and the outputs of AND gates AND11 and AND12 are low. Therefore, no output goes out to the pulse width determining unit 13. Here, as shown in FIG. 8, the size of each of the comparison levels TH11-TH14 is TH13TH14TH11TH12.

When the input of the pulse width determining unit 13 is the comparison level TH13 or TH14, the outputs of the comparators COMP11 and COMP12 are low and high, respectively, and the output of the AND gate AND11 is low. The outputs of the comparators COMP13 and COMP14 become high, and the output of the AND gate AND12 also becomes high, and the input is determined to be a T-width pulse.

In addition, when the input is between the comparison levels TH11 and TH12, the outputs of the comparators COMP13 and COMP14 are low and high, respectively, and the outputs of the ad gate AND12 are low, and the comparators COMP11 and ( As the output of COMP12 becomes high and the output of AND gate AND11 becomes high, it is determined that the input is a 2T wide pulse.

Accordingly, the pulse width determining unit 13 outputs a signal indicating that the input is a T width pulse or a 2T width pulse according to the outputs of the AND gates AND11 and AND12.

On the other hand, the output of the ternary judgment unit 11 is delayed during the processing periods of the pulse width voltage converter 12 and the pulse width determiner 13 by the delay unit 14 and input to the data output unit 15. .

The data output section 15 synchronizes the clock from the VCO with the T width pulse or the T width pulse or the T width pulse or the 2T width pulse output of the pulse width determining section 13 to exactly match the output of the T width pulse. Output by 2T pulse.

As described above, the present invention determines whether the output of the comparator of the data extractor is a T width pulse or a 2T width pulse, and outputs the T width pulse or the 2T width pulse to the output of the data extraction part to lock the width of the data accurately by the clock. Locking and narrow pulses due to noise are eliminated, thereby improving BER (Bit Error Ratio) and S / N ratio.

Claims (5)

A third determination means for determining the input signal in three values, a pulse width voltage converting means for converting the output of the third determination means into a voltage, and an output of the pulse width voltage converting means in comparison with a predetermined comparison level. Pulse width judging means for outputting a signal indicating a pulse of width, delay means for delaying the data output of the ternary judging means during the processing period of the pulse width voltage converting means and the pulse width judging means, and from the delay means. And data output means for outputting data in synchronization with a clock as an output signal of the pulse width determining means. 2. The apparatus of claim 1, wherein the pulse width voltage converting means comprises: an inverter for inverting an input signal, a switching unit switched according to the output of the inverter, a capacitor charged and charged according to the output of the switching unit, and polling of the inverter output. And a data hole head for outputting the charging voltage of the capacitor at the edge. 3. The data extraction circuit of claim 2, wherein the switching unit comprises a PMOS turned on when the output of the inverter is low, and an NMOS turned on when the output of the inverter is high. The first and fourth comparators of claim 1, wherein the pulse width determining unit has a different comparison level determined by the first to fourth variable resistors, and the first to logically multiply the outputs of the first and second comparators. And an AND gate and a second AND gate for performing an AND operation on the outputs of the third and fourth comparators. The data extraction circuit according to claim 1, wherein the signal indicating that the pulse width determination unit is a pulse having a specific width is determined according to a system.